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Digital Electronics Practical

Electronic and computer engineering, digital electronics lab manual

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darshandevarshi13122005
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43 views52 pages

Digital Electronics Practical

Electronic and computer engineering, digital electronics lab manual

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darshandevarshi13122005
Copyright
© © All Rights Reserved
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Vidya Prasarak Mandal’s Maharshi Parshuram College of Certificate Engineering (Affiliated to University of Mumbai) Hedvi Guhagar Road, At : Velneshwar, Taluka : Guhagar, District : Ratnagiri, Maharashtra 415 729. This sto certify that mr/yig. RUSKiKesh Tukttram Ghernekar of Branch E XTC {fj Semester 3 é Exam No. t has performed t above in the premises of the institution during the year. and has successfully completed all the practicals in the subject of as prescribed by University of Mumbai. lo, waP RACTICAL IN-CHARGE iafielis RollNo. _1 399 the experiment mentioned 20\5-20 Digital System Dertys ( om eyo HEAD OF DEPARTMENT 25|tolts DATE EXTERNAL EXAMINER Experiments in the Subject of Vidya Prasarak Mandal’s Maharshi Parshuram College of Engineering (Affiliated to University of Mumbai) Hedvi Guhagar Road, At Veineshwar, Taluka Guhagar, District : Ratnagiri, Maharashtra 415 729. INDEX Digital Dasign System Design Name of the Experiment Date Page No, Re 16-F-19 15 To Study behaviour af Misqive @ gattes - TO study implementa ton) 30-F-14 6-3 | ol NoT AN ,oR" Abing | Universa/ gate U B-8-15 9-12 To clesrgpn and implemen E ane YY Binany to Gr&sy ~ tool € oy BGrad fo Binany Code Coerter J -|Te implement base half Aaeley o/8/15| 13-16 substeactey and fel a adder SLéubstrae tor an Logic gate | Te desrgn and implement Gobi addey 4nd subs hactor feat) 1t-19 LAs ney Te Tamas + o To clexvgn and implemen(- 4-bil Comparator eS GI8}ig{o0~2 Ie ay 9 To Stuckey. 41 mult’ plexer o)\9 and olfmult plerer a 5— 94I- F a = Vidya Prasarak Mandal’s Maharshi Parshuram College of Engineering (Affiliated to University of Mumbai) eshwar, Taluka : Guhagar, District : Ratnagiri, Maharashtra 415 729 Hedvi Guhagar Road, At : Veln INDEX Digital Sy cme Design - Name of the Experiment Date Page No: leas Experiments in the Subject of Remarks Se No. joj1a| 29-24 g:| Stmuld ben | Eat? SI full sader. 16 =f acdder and LS r] Assign menpE. (Vor 2 oily [Ghee 24 eB | 2} Asagn Ment Noo PETE! 34-4) a a [Arg ment Alo 2 [eee ap = 44 G g/loftg| 45- 5°: Ss 4 Asean 2ot nlo- ty. = Maharshi Parshuram College of Engineering, Veineshwar Affiliated to University of Logie Gates Senceus Run Kesh Tukardm! @hinekar 6p 9 ap oe ~< SE year “Subject - Digital Syeter & Designo Branch - Electonics & Telecommupication Engineering. Tc and IC pumber:- + — __NAND gate Atm. NoR gate BHIpIO = dyajse doit iqueamesslsT 8 einedseiy <= doa ro : se ——+f 2220p ; ies 3 2 tee Maharshi Parshuram College of Engineering, Veineshwar Affiliated to University of Mumbai page Se : ‘a i ———— -_ —_ Leggie Gather ia Atm - To study behaviour 2h, logic gates a. 9 bread boa re), | amp» Apparatus- 5v DC power suppl PP monitor Te jabo. TC Tucr Ze F404 TC F408 167486, TCTH32, 1034266. ely Nor Gate Ge 404) =(x=4 ) Wihen the Tp is low ten 0/p is high Whew the Vp _is high dhe Op _is Jow. Thereby peda ole cai inverted R pulse Truth Table t/e oor . fs) OUAlLt a x=A © 1] ey 2) AND Gab Tre AND Gate is one of the haste gates can be combined +o form any | ea) D_gpte can have {v0 or more’ T7p and. J 5 what 15 known a5 logicat multiplication : 5 gate Wp x is big b J arr: Maharshi Parshuram College of Engineering, Velneshwar Affiliated to University of Mumbai & ¢' D_Gate (IC 7400). X= AB 3 A_NAND gate duce a low Up on | when all the J are high. Por a 2-I/p s b NAND gate, Yp x is low" on when | I — _ ASB ave high -X is High when erther “9 Aor ® 14 lot or when both ABB are low. SONS. 94 5 2) OR Gate - te 7482 ai SidBT dit z t o °o 1 P | a¢ Fo | Se Maharshi Parshuram College of Engineering, Velneshwar a 4 Yow when either filiated to University of Mumbai pageno_4_ Tuth Table: Th put F Gutpdbd| 9O-%4 _ AB Sad PoE te o hb 1 a ib ae ee ee ‘| iF | 1 sacl aa \ o 54 | cs ier ( re \ OR Gate (Teor) :- X= AB A_NOR gate produces alow Y%p when any of its 3p Wis High. For 4 2~ input Nok gate /p x is ue Aor YpB is high or when both ore ABB are high X- a Fath Table Eppat— | : A B X= A+B © agsvP ar $45p) Son> x4 oO \ Oo Keo 0 1 tt o | Ex-oR Gate (Te Fugees) w- excalutive a perfor ms module 0-2 addition for an ex Sve ~ OR gate-9 x * jp A is low § Typ BX is Kig b and — low Tp Ais high- X {5 low when | are both High or both low. Ex-oR Gat gi. Fe 1436 ug IT =: sidist di x o t | J | 4o pnb asdus ei . | 2i X q\, s46p Jol esi fe |. Tefcy 00! 5, 1, *X dpid 215 “Dear 2 dT dai Maharshi Parshuram College of Engineering, Velneshwar ‘Affiliated to University of Mumbai ‘iin —— = == A & | } O o_| 1 0 ) ’ ‘ \ oO 1 j p beivtesd eat, the S Cex Nok aie) (oc 74266) = x= ABtTAB = AoB : Ss an exclusive Nok gate op is low : hen Tn A ison O*)s BY high os when A low. X 15 high cohen ASS dre — - 38 high GG is __ both hig or both loa gic gates were Stu ahied and tables were Vented. Maharshi Parshuram College of Engineering, Velneshwar Affiliated to University of Mumbai pageNo_6 Experiment - Q } Aim To study the implementation abe AND t OR using Universal gates NAND and MOR gates ¥ Name- Rushiketh “1. Ghanekar Class - SE (ExT Subject — Digital System & Deasqu _(Ds0) saa ta GFen, eae ann Laser ee any (I Rave ugpunp LON (e ae8 any 12qe8 anvN nN Maharshi Parshuram College of Engineering, Velneshwar Ailiated to University of Mumbai page no_t Aim- To study the inplementation a NoT ANDO, o& gates Le nancies gates NAND and NoB gate A pparertus— \ NAND +400 S 2 Nor AYOr | Theory- > NAND qerte = The NAND gate can be useal = to generake tive NOT ean the AND functdn AB | the “oR function ane OWeeeEeHon : 7 % 5 oO d Implementing NOT using NAND gate :- o Ab Sindee Vinnie, mode Brin NAND gate \ & by connecting the Tp tteqether and actiag E in etget ES de Ep “ex a hoop .7 by Tmpleen-Hng AD function using NANID 4 ate: = Tie AND Aspects Can be “generated Pe only NAND a LEVIS generated fay Sing iMenting 9 5 NAND Sate ie. ra ni @ VO AB EAB OR. unction using NAND gate > A Action is genertrted uting only NANN- Liou - We Know Ha kb Galedne Cac esaton. is re AtB | ‘4 =AiB 5 ana 4 1 | | asia | | > Nox gate: : Lae 3) Not functfon uring NOR gate. — A+B =X BSaniop x A > Not Maharshi Parshuram College of Engineering, Velneshwar Affiliated to University of Mumbai Noe B gate yore Nok sade 5 ube) et/so a _caniversal “a2 te, it can Berused: eo generate the Not AND and OR junctions. ae a) Not fainction using Now gette:— A invertor can be made m_a No@ gate bs Connecting all o} 1 together snd) creating ain? eh Sa Singie Common Sp. by AND dunckon usin Woe ay Ary AND naton TS genera ted oes only NOR ae es atk lle Vd Feuk the Solea p e8sion for AND gate ts — Pte x B S ceeds arr ay OR Sunchop uxing Nog gate- An OR Sunchren can be generate) ting only Noe gate. Te cab be generated b simpli inverting out of, Nok Bess. d 3 ae ie. A+B TAB Versa coed yer NAND § Nor gates - Were: vr implementn SAND, 4 OR Sno Sin wiciie “resis benena sitio dibs tneth terbler . - Maharshi Parshuram College of Engineering, Velneshwar ‘Mtated to Universty of Mumbai ppt =——- Expenment - 3 < X Binary G Gray Gde Conversions. oT U Hi ame- Lushikesh Tukardm Ghanekar fist Branch — Electronics & Telecomunicatton Engineenny. nd i Paes no aaa Sng tal Spee ot ————————— kk-Map for Bs - k-Map for Ba — S60 | Sho. ert ae tn ~h Rd doe Bie s4.. aliov hevsto old Kg Bors: Oar OG) O40" a\' sat ne of o& 0S “Otto 9b SAB Rise 1000 Maharshi Parshuram College of Engineering, Velneshwar Affiliated to University of Mumbai Cocle - Fach one o te four roe ps Sepves ent 5 jeu output $ ol the penn asa function ol the gouv cuakneths inputs variables: TA. te - devel logic alia gram may be obtained Airectty bom the Boolean “enepvea sire derive J by ibe neue dikslebate woe glber possiblities fer a S ag I Hagram hati mp!ements Ps Cireait - “New the gate ehtee output Ts CHD bas been uted fo imple aS eS partially each of three outputs. Trdth Table = i d Sine te Gres Gode Convertet= Maharshi Parshuram College of Engineering, Velneshwar Affiliated to University of Mumbai PageNo,_\ 2 ay Gray to _ Bina, Copverter- 0 Gas (oes @ aes {Ra Bs] Bi] Bo o| o ° Lo| e|°2 |o ° o ° \ ee ° 2 {9 | O oO 1 ' o| oO ! ° E oO oO \ Oo | © \ fh oO 1 i [o ° \ Ope ° \ | ( } 1 Oo ! ° ile | * pe | lo] ° \ Oo o oO \ me \ | ! oO ro} 1 oO oO Oo It I ° i I o 1° | ea ! I I To: yO 1 I CEG | ° 1 J} o oO 1 ° | j fe) ! J »> Give logical inputs ais per trth table - 3) Observe the lgical outputs and verify with the ] 5) | ee yMaike Connectdns 45 per Cireuit chi agram | | truth table. | 4 e Binary fo Grey G Gray te Binary verter Gambina bona) Si reuits dre Gnsthw ao) (thsi truth table have been checkect. — 3 1 SEE LLU Maharshi Parshuram College of Engineering, Velneshwar Affliated to University of Mumbai pageNo._\® Experimen t-4 Name- _Rarchikegh TT Ghanekay class - Seand Year Brant - ExT¢e Subysect - Digeka] System Deatgn- VT y eee ee a Maharshi Parshuram College of Engineering, Velneshwar Affiliated to University of Mumbai Page No.4] Study of Baste Adder [Gubstra ctor ac Cirtuits | Aim - “To implement _ baste Hal} Adclew [Sabsteactor ane fal! adder /Substractor ating log gattes g Components - 7 Power Supply : 2 Experiment! Wit To t408-AND Gate y Te 1432 — OPGate Tc F4e6 -— ExX-°P Gate r oy Hall Radler A hal, cdder fs Combinertigne( _~ Circerit having 406 topets forthe teo bits fo be added 8 two o/P one m the sum ‘Ss’ ~ Sather oem the cary '(' into “the higher adder —- Posttion dnro truth, fabled + it is peated thea k ~ Wyrm opiects YP 15 EX:2 OP with the Bp ~ asAdey ohile the any ofp ig the AND’ 2p enith: Hb) ane m7 - 27 Kull Adder « A ombinatanal rad & i that dorms mettre sumo] inputs Ze - tensists «| Hice int Shoo op a fall Galdeh¥5 Udelal Jo add tivee bits zratime — Pp bee og halé “adder cantt do so inafal) - L_acleler, Sum output wil) pe taken from Fe-oR et as ha eoill fetken from or. gate. a pra Baer: pul! ato Eee COradt Gmbinabrndl the = Half Subs rb ene Bvt 6 inpul> wOtt Ye . Jt pds 4 n beroeen “the 20 8 bet : h & also produced a0 ff te has beet borrow’ In the cub atreacton 15 culled as fpuent bit and Bis substrictent bit 1003 in a Git three i/p 2° i Pibvand 8 “is sub shantnel Cin by the prevded step be uatng fote will ns of cach chips to D ips {te be dh psterctor— walfses— sub= 4 @8 A yy 0 3 [w1e | 2 | a Maharshi P; ineering, Velneshw: eax 'arshuram College of 4 ea Affiliated to Urea ae - ~ ee ay: pins ec woe pig alte — ae Dena skis. ® Observe tthe %p J cli fjerent T/ puke. - | tombintthans and “Tet went fy the [truth || tables for adcler Cire bee es Gr alsion - § D the Circnits for bald Adcler aswellas ~ gull ey and also z (ubsbactor FS - — 1S doi] Cubshrector “ran be builk using aKa gates. j 2 , 2 cam Cary ane bernw o/p r four ee Ppt ae ends On darreudae / Comm bina hones =) A fe | Fedlclexean be conshuetec). — a if caliper es Godel pem of Engineering, Velneshwar exe TS ram College of t- Maharshi Parshu b ‘fliated to university of Mumba a ExperimenE-S Tame - Pushikesh T- Ghanelea - ic E- Year. Rotl-no - Ts03 Digital System B Design: ) peice Maharshi Parshuram College of Engineering, Velneshwar Affiliated to University of Mumbai Page No_\ 8 4 - Bit Adder and Substractor Aim- Te desien and implement Abit dddew and Subsbitelor using Tc prs - Tg Apparatus - Tcw4es, Ex-oRgate Tcryss Patchcards- NOT gate 104404 | Regulated pewersup ley t f Theory - h- bik Binary Adder A binary adder is a digital ape ther + produces the aithmebe Sano al, two btnavy numbers. Tt can be consbucted with dull J adder 5 cannected in cascade sith the outpat- cay fee coh futladdet Conoected te the Tp cermy addex in chath - the eueg. ends bit A ce the addend bts oh cd cle Sig nated Sub sod pt pambers ro vigh to left Snes igs a denoting “the leet siqnifican E bits: a The camer ate Connected to chain “Hbnaugh the ladder .The Up Scivity te _the adder ate Co & Sis through the fol adder te Yp carry Cu. 4 Bit Brow Subetetor- The Cirait y subsbtieting A-B constst< al with tavertors, placed dala Lp Band the’ s«etpon | adelet l The ee cary Se must when v perchor Lag substractan . Y JT ee ee ee y 4B Acide uy ne 107483 - ee i site ek . (oust! 1 he 3 . ‘ oa v4 Percent By p Ao s\ Vitost So xp A \ inate Sa ost 6 a x]? Ps a end & 4 ‘4 ib te d % 4 3 3 il i A : 38i——Su > yo Brit substercter TOP SS Noe > Adeer iy | Maharshi Parshuram College of Engineering, Velneshwar Affiliated to University of Mumbai Page No. {5 4 Bit Bina Acide Substractor_ The _additfon and ce ene eration can be nected Into O02 Cireuit with me common btn Mede S/p M Controls thi 5 operation When te=o te free E is adder when Me! become substactor adder, he = Irth Tetble - 4 - Bik Binary Nader. qnectons as per the Crear Roitch on Vic and A vaKods cmb TP acerding te tet ble. reading for Aadex § Subshxctor- e u-brt elelcler and sabstreter Adve 8 { mplemented uatog TC IA2s- Maharshi Parshuram College of Engineering, Velneshwar Affiliated to University of Mumbai 20 Experment 6. Aam- To shidy 4:1) muth'p lexer J Demuthipleren. Name- Rushileesh TT Ghanekar. clerss - Se tend Year, Baneh = EXTC Pollno — #309. > Pin Diagram using TG+ tual Ge Te-TWi5SS Maharshi Parshuram College of Engineering, Veineshwar | Affiliated to University of Mum 2 ial ‘ ee Page No. y es ® et i ee Mul tip lexcer and De multiplexer pantie 4A To Stucky a Tod bi plescer ln el Demmul¥ ples Vpoaratas Keo ui ved ~ TC Tretiner Kit, Patch tards , Poors Say cory - bMult plexers- The form multiplexer Tens many fnto one. [tut biplenci n the yp ed S oh fans retin alae ae 1 ofocmatok over &] srone | [Fre . Aelige tat Math plence x (0x) ws 2 2 Cambinertond | cele: that selects one cligita! indarmertan from Senewa} Source’ And Reosmits the selechked indrmaton en a Signa! output line. rac tiplexer has Severe latte -Tn pat Wet ofp Mine. The Selechon 7 int cul tr iOpat Loe u's Contr lec | ndelecton Lines < The input [2n-< block. 2 multe lence with p ioput lenys, Zines and Ine 0 at ders Selechag Uinet alecicleg the number ; is equal fo i" the are cegtiivecl, fo Select’ cgua/ one in pat mes tole lop Anes, ct Hines dire reg tuiced and $o6n. er Acts Like a Legitally ton bol ea) itch Where bina pdé pliect to Maharshi Parshuram College of Engineering, Velneshwar ‘Afiated to University of Mumbai Page No,_9-2 will be Swi teheel on to the Cee Te ques - 4:1 Multiplexer. A Atl mat tiplercer Consist s_four clatter inp s Sine ema tke Dy, tiso Select lines as Soand Sy aod 4 Single output dine ¥- The select Lines Si§ Sa Selects one oF four input Lines fo connect the Output tine -The parirasler input (Po te Bi) to the Oukput - ae | Vea be lenwer when the maltip ~lerey Val ettool’s ¢ the 1 al thyugh celect- Ling \ale Carn uorite the at PER 518.0 as: S126 sand So=@~ then T= Do therefore Y= Do C1) CS) T) Si -6 aod! Sa=] then Yod, thereice Ye O, Cs Go Essie ag andso=6 , then Yo 02 therefre Y= Dz Cs) (G0) enw and S=! then Y= Ps e there fore M2 Da CS) Coed To get Phe totel late output fom the multiplexer ql) these nypcluck texms are lo be Summed And the ding | boolean funchon | ae pene rs mult plexer [5 given Us-_ = GP (so) +Pi (Si) so+ Ps, )Cso) + Dz Si So: Useca lly the enable enput ov shvbe can be kted to carscticle t20 ox more paul Eplexes IC, to wonstrct a mu tipleer worth large number inpets: mulb'plexer is sup pliech with SKparate. Zf/p ob again Of te? 4/53 - ‘ m gene Hae Is ee Maharshi Parshuram College of Engineering, Velneshwar B Pease a Nai Affiliated to University of Mumbai age = ——- ——) hi Be mult Dlexe re: - Fee The word clemulbiplexer mean one & et inte many Demulbpleming fs the process o tyking een tan fen one input ane transro alg the Same over several Outputs . 7 t A demultiplexer peo logre Cixcerit that Yecerves info an a single input and heansmits » T * the seme info. over one af severe | (2) Op liner. LO. FaIS 5 4:1 Demultiplexers AH'| chemultiplexers has a single T)p (bd) dour outputs Qo se) andstsc ek Tr put I C& $s.) The truth table BL thc ey cle met tin ) ~lever is Shown in table. tthe trieth < ib ts clear that sate Tp ap: “owen 12 0 3 S,20 § date pemanncctec) to Yee iy ahen S) 26° So Sper: is Gonected to Sp Ye G1 When S21 F i=! BSo=0 eee ec — Maharshi Parshuram of , Veineshwar College of Engineering, ‘to University of Mumbai Page No_ 2‘) =. No = 5 So GS ee eee Ss Cy pee Se 1 a [Pe Ye ei .s6 fp A_N4 demultiplexer can be _implementedt uiiin four Z-ioput “AND gets § two eT gates. Here , the Tp latte Line 45 Gonnectecl foal) AND gets: The jeep Sinelect< inst. s, aSbhenghle, sou, one gate at a time ane the gata that eas on Wp sine asset through tHe Slecte gitte , to the Bssoc Artec) 7 6utPut Bner. — f 7Bemuthplewer ts the Cire h whteh selec: -ts the oo. for its only input « f [25 TC seal 15 74155. TH has isd elects inputs Aod- Whfch__sleetdes the detol Do, 0; Da, De. - at is low When enablee! otherwise high. ‘ C ecEy The (Bi kare Pen Circuf t Ohi Agvetty onthe ~pouer ae oki ent Combrnathons 1 Obse rve- ~ tenapave ine Ja ere bruth Maharshi Parshuram College of Engineering, Velneshwar ‘Affiiated to University of Mumbai Page no_25 [ a oe Experiment ae . I Aim- TO __Jearyn B implement 4- bit magnitude t Gmparator “SY Tc uo I Name Rushikesh US AB eR es 1 class= Se wad Teer Branca -— ExT Roline- _T3°I+ ant gcv giv Tt ese Oe ope — | ' i Maharshi Parshuram College of Engineering, Velneshwar Afiliatod to University of Mumbai Pagstie 24 4. BFE Magnitude Comparttor Arn- To degn and implement 4- brk magnitude - T Com paverter wang Tc 14R86- f ‘ Apparatus Requivect= Rese oes Caparator TCWLS TC hatner tet, Pateh Cards . Theovy- The Wmparision of hoo fumbers is aN © aperthan thet determines one Humber 16 greater a. or leas than ore ug! toothen number. I A megnitude Bmperetor js q wMdbinatony) egret that compares foo no. AFB $F cleterm vines their teldbve _porgnituct ¢ che bettome o| the Compara ter rs Speci hed by three bon ary vandbles that incdiurte Whether AYB A=R | [ ce) ALB. 4- bit roagnitude Comparator - The TCVUeS isy U-bit meqnitude bom potratoy the (%H_b- Cac pte to almost ah length: TE compares keo 4 BF by Biea, FBLD ov other Mions= a fomve Codes and Bsnble Mx hitude results ce Aebrk inputs ave wtgh teal ad (Ro-Bs) Where Az § Bs axe Most in/e__ daArD cand TAcB are the pifcant bits ophons when usexl dy Senes the Av® A=68 §ALB outputs of the least : fo locreaponcins Tare Maharshi Parshuram College of Engineering, Velneshwar ‘Affiliated to University of Mumbai page No T= GdG uae & inputs of the Next Aigner skige Tt A= AxArAiAo B= Bs 2 B: Bo “The equality o] the og numbers 8 Q fs bie plasyeo! in a Cobkensbonell Grete. ecleni gael bs hz. Sy mnbo! (a= B) This indicates A quetie s tha B then inspeels the reltitive magniluc< a pairs 6 significant cligtts shewtin 4rym Mos sig neh dnt position A 7s O 8 Ht of 8 isO. Ale have ACB the Sequentia) amp nS 9 gan he expaneled! as A> B= Az Bs +X za Be Xe ¥2 A,B + %s Xo %X% Ao Bo - A2ZBS Ay Bs +¥5 Pa Bo tXq Xo Mi By +X 3 %X) Ao Be The same cirtutt cen be uted to G@mpare the pee mesh ole oh two BoD hig: tte Where i expeindecl, as A, Nat (Aas Bs) (a+ Ba) @r4 8) Cao? be) wy! xo Xt Ba Thoth Tetble - Maharshi Parshuram College of Enaineerina Vatnach=--- Maharshi Parshuram College of Engineering, Velneshwar Affiliated to University of Mumbai Page No. Procecluve- 1) Connect the sireutt diced the Bebit bine, words Ao A, As,As $86, B,8:,B, m_ the laxic Input” switehes Beaune of e485 Should be at logic 1 to encthle Compare openetHon Os Observe the 0. ut A>B™A=B , ALB on logee indbicertors . the output? must be Lor O weipcclively . ay Repeat the slep 42,3 dor veious top Ao, Ar, As, As § Bo, 8,82, By GF observe the abr. ssi ARS AS BISA < B Griclise nl ST bE magnitude compar -ettor cireeutt is implementect her, use. o ee Bice. ctgugeatenna® Hales == as SS SEE Maharshi Parshuram College of Engineering, Velneshwar Affiliated to University of Mumbai Page No. 22 Bip ceithedt-Senivofit 2 ai wn! Simulation doy Hall Adden & Full Acer ‘ t Aim- pTo simulate alh Adder uring behaviour] Modeling - ee 4 ~To simulate ful! Adicler Pans behavoriet! modeling. | 8} To slmatete full Adder vting bso half + Adeler uring Shucturer! meeleling. Sojtoare uted - YXiling TSE Simatatoy (4:2 coy = a) HalpAdcler = A Hall Adler 1S _2 Combination Gb cited hawng feo Vp fee the two bits tebe Adelee! and feo Sp pone kexm the Sam '4! gnel other doukn dhe camry ‘C’ into the Aiphes adlclifidod positrn feo the truth table given belns, ddelex js a combinatrone) avithmetrc gum o fay Amor 2 Block haga? of A sum i Full o por Cont Rejuatoms Sum = ABOU law = ABO “(CA@B) - cr Bloc bapem en ful) adeler wring >: age! Adder Maharshi Parshuram College of Engineering, Velneshwar \ Affiliated to University of Mumbai Page: wo Sum YP will be taken fom Execs tgeite Scary Se wil dake From Rgate. it Truth Table - i Bl Go | Carns [Sur al | o oral ° © Olo ! | (23 ae oO Il 3 35 ! | I oO I ' - ! 6 | —@ [77> 6 oe a | vl I ke No { | Oo Vy 0 1 Bees 1 WI cp Ru) adder using Hal cher A full Adeler can be lwostriettel yp tee alg adelors L zxet two _inpuks ie Jc te the First hall Adder ‘The gam Sp the frst hal adder 75 given to ‘A! input of Second hate Addex And Cin given Ets ‘Bin put ana her pat delcler -The sum Spo Se cae Adder js Of, pte ) deter, The cabs Zp ot full Geller 7g ken by * oR’ pate Whose Be te tet ve cay I ™ bald acletey : hevdasave Deca phon Laagusg, ee Inteqredee) hee). a s | The ent Maharshi Parshuram College of Engineering, Veineshwar Affiliated to University of Mumbai — = gh units fh voi Pageo._*?- Sb Entity “2b Arehibecturs tS the name plate o| the deviqn-It sp —ices the types as pacts ise, input & o/p paxts alheacrrahrieceste Spbutices that the Rey | te cle ar wbat S going Dapper ionele the cieuerl. Thar - es Spec Fes Bees Cirot going & behave ox deunchaon g Styles of Mocleling the architecture: Behavioral WSbuctual <> Bala Flow, The streturt] peadelen S date Modeling axe Used ~ when the intemal ennechong ave clen Khowwn ane Sheught forwsave “they are enere lly ucecl fx ami tena © gps. for larger dibens He expecttd behewiour a] the ~ lesign 7K known Sheree behawaret! macleli [eekeae oendinabron of the th

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