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Split-SAR ADCs: Improved linearity with power and speed optimization

Article in IEEE Transactions on Very Large Scale Integration (VLSI) Systems · February 2014
DOI: 10.1109/TVLSI.2013.2242501

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372 IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, VOL. 22, NO. 2, FEBRUARY 2014

Split-SAR ADCs: Improved Linearity With

Power and Speed Optimization
Yan Zhu, Chi-Hang Chan, U-Fat Chio, Sai-Weng Sin, Seng-Pan U, Rui Paulo Martins, and Franco Maloberti

Abstract— This paper presents the linearity analysis of The binary-weighted capacitive DAC is widely used in
a successive approximation registers (SAR) analog-to-digital SAR ADCs. However, the capacitance of the DAC array
converters (ADC) with split DAC structure based on two increases exponentially with the resolution, which imposes
switching methods: conventional charge-redistribution and
V cm -based switching. The static linearity performance, namely larger consumption of switching energy, area, and settling
the integral nonlinearity and differential nonlinearity, as well as time. A valuable substitute is the split capacitive DAC,
the parasitic effects of the split DAC, are analyzed hereunder. In which has been recently reconsidered for medium resolution
addition, a code-randomized calibration technique is proposed [13]–[18]. Its key limitation lies in the parasitic capacitors
to correct the conversion nonlinearity in the conventional SAR that destroy the desired binary ratio of the capacitive DAC
ADC, which is verified by behavioral simulations, as well as
measured results. Performances of both switching methods are array, thus degrading the conversion linearity. However, by
demonstrated in 90 nm CMOS. Measurement results of power, using the metal-insulator-metal (MIM) capacitor or/and DAC
speed, and linearity clearly show the benefits of using V cm -based mismatch calibrations [19]–[22], the split structure can become
switching. suitable for a medium-resolution target. On the other hand,
Index Terms— Linearity analysis, linearity calibration, SAR the conversion linearity is also directly correlated with the
ADCs, split DAC, V cm -based switching. switching sequences of the DAC array [12], [23], where the
I. I NTRODUCTION conventional charge-redistribution switching results in worse
conversion linearity and more energy losses. A Vcm -based

S UCCESSIVE approximation registers

analog-to-digital converters (ADCs) [1]–[4], as an
(SAR)

alternative to the pipelined ADCs [5]–[9] has become popular

switching technique has been recently proposed [24], which
achieves a significant switching energy saving when compared
with set-and-down [3] and charge-recycling [25] switching
for battery-powered mobile applications, such as DVB-T, approaches.
DVB-H and TDMB [10], [11] which require medium speed This paper analyzes the conversion nonlinearities, induced
(10 MS/s–100 MS/s) and medium-resolution (8–10 b). SAR by supply noise, switching methods, and parasitic effects
ADCs [2]–[4] achieve very low power consumption due to in SAR ADCs. The static nonlinearities based on the
their simple architecture and operation. However, the SAR conventional and Vcm -based [24] switching methods are
conversion relies basically on the performance of a capacitive theoretically analyzed, and the mathematical models are
DAC that subtracts the reference voltage from the input developed to verify the effectiveness of the Vcm -based
signal. The kT/C noise, capacitor mismatches, and parasitic approach. Experimental results on a 90 nm CMOS 10 b
of the split DAC [12] affect the conversion accuracy. As for 65 MS/s SAR ADC with conventional switching and a 10 b
medium resolution, the kT/C noise requirement is fulfilled 100 MS/s SAR ADC with Vcm -based switching demonstrate
with small capacitance, while other nonidealities like parasitic the performance benefits in terms of speed, power, and
and nonlinearity, whose effect depends on the structure and linearity by using Vcm -based switching.
the switching approach of the DAC, becomes significant. In addition, the internal node parasitic in the split DAC
Manuscript received May 29, 2012; revised December 13, 2012; accepted is also analyzed, as it degrades the conversion linearity. The
January 8, 2013. Date of publication February 14, 2013; date of current above limitation can be fixed by a code-randomized digital
version January 17, 2014. This work was supported in part by the Research calibration technique proposed here to improve the differential
Committee of the University of Macau and the Macao Science and Technology
Development Fund. nonlinearity (DNL) and integral nonlinearity (INL).
Y. Zhu, C.-H. Chan, U. F. Chio, S. W. Sin, and S. P. U are with Section II presents the overall SAR ADC architecture;
the State-Key-Laboratory Analog and Mixed-Signal VLSI, Faculty of Section III introduces the conventional and Vcm -based
Science and Technology, University of Macau, Macao 853, China (e-mail:
[email protected]). switching approaches. Section IV provides an analytical
R. P. Martins is with the State-Key-Laboratory Analog and Mixed-Signal analysis of the static nonlinearity due to the capacitor
VLSI, Faculty of Science and Technology, University of Macau, Macao 853, mismatch and the parasitic effects in the two methods, and
China, and also with the Instituto Superior Técnico/TU, Lisbon 1049-001,
Portugal (e-mail: [email protected]). it also includes the behavioral simulations for confirmation
F. Maloberti is with the Department of Electronics, University of Pavia, of results. Finally, a DNL and INL calibration technique for
Pavia 27100, Italy (e-mail: [email protected]). parasitic nonlinearity in split DAC is proposed in section V.
Color versions of one or more of the figures in this paper are available
online at http://ieeexplore.ieee.org. The measurement results of two integrated SAR ADCs and the
Digital Object Identifier 10.1109/TVLSI.2013.2242501 conclusions are presented in Sections VI and VII, respectively.
1063-8210 © 2013 IEEE. Personal use is permitted, but republication/redistribution requires IEEE permission.
See http://www.ieee.org/publications_standards/publications/rights/index.html for more information.
ZHU et al.: SPLIT-SAR ADCs 373

Bit 9 Bit 0 However, it would be beneficial if it can be avoided to save

switching energy.
CLK=100M
The Vcm -based switching method proposed in [24] halves
SAR Logic
the array capacitance leading to around 90% energy saving
when compared with the conventional one. Fig. 2(b) details
S np Snn
the Vcm -based switching algorithm. In the global sampling
Vinn n phase 1 , Vin is stored in the capacitor array. During the
p VDACp conversion phase 2 , all the capacitors’ bottom-plates are
Vinp switched to the Vcm first, to give rise to the voltage −Vin at
Capacitor V DACn the output. The sign of Vout determines the MSB as the logic
Vcm network
VDD properly controls Sm,k−1 . If −Vin < 0, Sm,k−1 goes to Gnd
Gnd while the other switches Sm,k−2 , …, Sl,0 remain connected to
Vcm . If −Vin > 0, Sm,k−1 is switched to VDD . The cycle will
Fig. 1. Block diagram of the ADC architecture. be repeated for n − 2 times.
The Vcm -based approach performs the MSB transition
by connecting the differential arrays to Vcm . The power
II. OVERALL ADC A RCHITECTURE dissipation is just derived from what is needed to drive the
bottom-plate parasitic of the capacitive arrays, while in the
Fig. 1 shows the architecture of the 10 b ADC. It is
conventional charge-redistribution where the necessary MSB
a conventional SAR ADC [24] consisting of a differential
“up” transition costs significant switching energy and settling
capacitive network a comparator and SA control logic.
time. Moreover, as the MSB capacitor is not required anymore,
The SAR logic includes shift registers [26] and switch
it can be removed from the n-bit DAC array. Therefore, the
drivers which control the DAC operation by performing a
next n − 1 b estimation is done with an (n − 1) bit array
binary-search algorithm during the conversion cycle. The
instead of its n-bit counterpart, leading to half capacitance
capacitive DAC array is the basic structure of the SA ADC,
reduction with respect to the conventional method.
which serves both to sample the input signal and subtract
Using supplies as reference voltages prevents static power
the reference. A reference-buffer-free technique [24] is used
dissipation from reference buffers [3], [17], [24], although
to improve the power dissipation and DAC settling. As the
the conversion becomes very sensitive to the supply ripple
supplies VDD and Gnd are used directly as reference voltages,
due to the switching effect. For 10-b accuracy the supply
the conversion sensitivity to supply variation is quantitatively
variation needs to be suppressed within ±0.049% of the full
analyzed in the Appendix.
supply rail, or the supply ripple ±588 μV for a 1.2 V supply.
The detailed analysis of conversion sensitivity to supply noise
III. S WITCHING M ETHODS is presented in the Appendix. As the Vcm -based switching
charges 75% less capacitance, simultaneously, when compared
When using the supplies as reference, the switching power
with the conventional switching, it can effectively reduce the
is dynamic, which is correlated with the switching sequence
under-shoot of the supply or reference buffer (when used). The
Fig. 2(a) shows a conventional single-ended n-bit split [k-bit
inductive ringing effect can be well suppressed by minimizing
most significant bit (MSB) and i -bit LSB sub-array] DAC
the bonding inductance, e.g., multiple bonding, through the
structure and its switching timing diagram. During the global
addition of a damping resistor and an on-chip decoupling
sampling phase, the input signal Vin is stored in the entire
capacitor Cdecp . On the other hand, to overcome this problem
capacitor array. The algorithmic conversion then begins by
an effective approach might be the use of a SA searching
switching only the MSB capacitor to VDD and the others to
algorithm like nonbinary conversion [27] that relaxes the
Gnd. Accordingly, Vout settles to −Vin and the comparator
settling accuracy requirement during large switch transients.
output Out_{comp}in the first MSB decision will be

0 Vin > 0 IV. L INEARITY A NALYSIS
Out {comp} = (1)
1 Vin < 0. A. Effect of Switching Schemes on the Linearity
The comparator output decides the switching logic of the MSB To analyze the conversion linearity of the conventional and
capacitor. If Out_{comp} is low Sm,k is switched back to Gnd the Vcm -based switching methods in a binary-weighted DAC
If Out_{comp}is high, then Sm,k is kept to VDD. For either (shown in Fig. 3) each of the capacitors is modeled as the sum
decision, simultaneously, the Sm,k−1 (the MSB/2) switches to of the nominal capacitance value and the error term
VDD for the next bit comparison. The above process will be
repeated for n − 1 cycles. Cn = 2n−1 C + δn (2)
The conventional charge-redistribution method is not very considering that all the errors are in the unit capacitors,
power effective [25], especially when discharging the MSB whose values are independent-identically distributed Gaussian
and charging the MSB/2 capacitor is required (bit decision random variables, and have a variance of
back from “1” to “0”) This is unnecessary in general, but
it is required for that specific technique to operate properly. E[δn2 ] = 2n−1 σ 2 (3)
374 IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, VOL. 22, NO. 2, FEBRUARY 2014

MSB Array LSB Array

Ca
CPA A CPB
Vout B

2k-1C 2k-2C C 2i-1C C C

Φ1
Sm,k Sm,k-1 Sm,1 Sl,i Sl,1 Sl,0
Φ1{ Vcm
Vin
Φ2 {VDD
Gnd

Sample Φ1

Comp.

Convert Φ2 Sm,k VDD VDD/Gnd

Sm,k-1 Gnd VDD VDD/Gnd

(a)

V cm -b a se d sw itch in g re m o ve s
th e M S B ca p a cito r in D A C
MSB Array LSB Array
Ca
CPA A CPB B
Vout
2k-1C 2k-2C C 2i-1C C C
Φ1
Sm,k Sm,k-1 Sm,1 Sl,i Sl,1 Sl,0
Φ1 Vin
Vcm
Φ2 { VDD
Gnd

Sample Φ1

Comp.

Convert Φ2 Sm,k-1 Vcm VDD/Gnd

Sm,k-2 Vcm VDD/Gnd

(b)

Fig. 2. Single-ended n-bit and (n − 1)-bit split capacitive DAC arrays with their switching timing diagrams (n = k + i). (a) Conventional switching.
(b) Vcm -based switching.

Vout discharged (Vin = 0). The analog output of the k-bit capacitive
2k-1 C 2k-2 C C C DAC with conventional switching can be calculated as
k
Sk Sk-1 S1 S0 (2n−1 C + δn )Sn + (C + δ0 )S0
Vout (X) = n=1  · VDD (4)
Vcm 2k C + kn=0 δn
Vin where the DAC digital input X = [Sn …S0 ], with Sn equal
VDD to 1, 1/2 or 0 represents the DAC connecting VDD , 1/2 VDD
Gnd
(i.e., Vcm ) or Gnd for bit n. For a single channel SAR ADC,
Fig. 3. k-bit binary-weighted DAC.
the comparator offset and linear gain error in the DAC are
acceptable, thus closed form calculations of INL and DNL are
specified with respect to a bestfit line. In the SAR conversion,
and where σ is the standard deviation of the unit capacitor. the comparator offset appears as an offset error and does not
The Vcm -based method achieves half capacitance reduction cause nonlinearity, therefore, excluding the offset term, the
when compared with the conventional one, while the switching INL and DNL are [28]
linearity comparison between the two switching methods Vout (X)/A − Vidl (X)
INL = (5)
should be addressed in the same capacitive DAC, with the LSB
same value of capacitor mismatch as well as predictable gain [Vout (X) − Vout (X − 1)]/A − LSB
DNL = (6)
errors caused by unbalanced array capacitance. Accordingly, LSB
to perform the Vcm -based switching method in the k-bit DAC 2n−1
X =0 Vout (X) · Vidl (X)
array of Fig. 3, both S0 and S1 are kept connected to Vcm A= 2n−1 2 (7)
during bits cycling. X =0 Vidl (X)
To calculate a given digital input X with its corresponding where A indicates the linear gain error of the DAC, Vidl (X) is
DAC output Vout (X), the array is considered initially the nominal value for the digital input X and LSB = 1/2k VDD .
ZHU et al.: SPLIT-SAR ADCs 375

From (7), it can be deduced that the linear gain error A is as

input X dependent, which implies that the gain error Acon for 
C + δk − k−1 n=1 δk
conventional switching and ACM for Vcm -based one are not V (X) − V (X − 1) = k
2 C
equivalent. However, Acon and ACM values are quite close as 
δk − k−1 n=1 δk
1000-time Monte Carlo simulations running in a 10-b DAC, ·VDD = LSB + · LSB (13)
where unit capacitors are Gaussian random variables with C
standard deviation of σ (C/C = 1%), lead to variances of thus, its DNL yields
gain δAcon = ± 41e−5 and δACM = ± 4.2e−5. Hence, to 
δk − k−1 n=1 δn
simplify the analysis, it will be assumed that the prospective DNLcon = (14)
linear gain A and the δ terms in the denominator of (4) will C
be neglected. and with its variance
The INLs of the two switching methods represent the (2k − 1)σ 2
conversion error that combines together all the errors in each
2
E[δDNLcon ]= . (15)
C2
bit. Considering that in Vcm -based switching, the transitions In the Vcm -based switching the MSB “up” transition is
are Vcm related (with capacitors connected to Vcm ), it follows replaced by an initial reset of all the capacitors to Vcm (with
that the INLs of the two switching methods must be different. the middle digital input X equal to [1/2…1/2]). There exist
First, the worst INL in conventional switching happens at two consecutive worst DNLs occurring at the steps above
the MSB transition [23], where only the MSB is pre-charged (X + 1) = [0, 1…1] and below (X − 1) = [1, 0…0] the
to VDD , leaving other capacitors to Gnd. For the Vcm -based MSB transition. One of the worst DNLCM with two digital
switching MSB transition is performed by level shifting all inputsX = [1/2…1/2] and (X − 1) = [0, 1…1] is obtained
capacitors to Vcm , which is input independent and ideally similarly as
always achieves an INL of 0 LSB in the middle. The worst INL  
of Vcm -based switching happens at the step below the MSB 1/2 kn=0 δn − k−1 n=0 δn
V (X) − V (X − 1) = LSB + · LSB
transition, where the input digital code is X = [10…0]. The C
corresponding input digital code of conventional switching (16)
k−1
is X = [10…1] The DAC outputVout (X) and INL of the 1/2δk − 1/2 n=0 δn
conventional method INLcon are calculated as DNLCM = (17)
C
2k−1 C + δk + C + δ1 with variance
Vout (X) = · VDD (8) 2k σ 2
2k C 2
E[δDNL ] = . (18)
CM
4C 2
δk + δ1 VDD δk + δ1 Equations (15) and (18) show that the proposed method can
INLcon = k
· = (9)
2 C LSB C achieve a DNL that is two times better in comparison to
with variance conventional switching. It can also be found that the error
terms are decreased by  half, which can be attributed to the
(2k−1 + 1)σ 2 cancellation of the terms k−1
2
E[δINLcon ]= . (10) n=0 δn in (16). In fact, this happens
C2 because the capacitors contributing to two-bit transitions are
The INL of the Vcm -based method INLCM and its variance correlated, which are switched fromVcm to VDD . In contrast,
2
E[δINLCM ] can be similarly derived as follows: in the conventional method the capacitors connected to
VDD in two-bit transitions are completely different, and the
δk VDD δk error terms in (13) are summed together instead of being
INLCM = k
· = (11)
2 C LSB C cancelled.
2 2k−1 σ 2
E[δINLCM ] = . (12)
C2 B. Effect of Parasitic Capacitors on Linearity of a Split DAC
Comparing the results of (10) and (12) it proves that the The inherent linearity errors become worse when the split
conventional and Vcm -based switching have similar INLs at DAC array is used [12], [29]. The parasitic capacitance
the step below MSB transition. In reality, Vcm -based switching CPA and CPB in nodes A and B [shown in Fig. 2(a)] will
is insensitive to the input common mode noise. deteriorate the desired voltage division ratio and degrade the
The maximum DNL for the conventional method is conversion accuracy. The analog output Vout (X) of a split
expected to occur at the step below the MSB transition. DAC with CPA and CPB taken into account can be calculated
With X = [10…0] and (X − 1) = [01…1], the as shown in (19) at the bottom of the page, where CSL and
difference between the voltage errors can be calculated CSM is the sum of the capacitance in LSB and MSB arrays,

Vout (X)
 

i 
k 
k
Ca 2n−1 C Sl,n +C Sl,0 + 2n−1 C Sm,n +(C SL +C PB ) 2n−1 C Sm,n
n=1 n=1 n=1
= C a (C SL +C SM +C PA +C PB )+(C SL +C PB )(C SM +C PA ) ·VDD
(19)
376 IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, VOL. 22, NO. 2, FEBRUARY 2014

respectively. The parasitic capacitor CPB in the numerator TABLE I

changes the value of second term. The CPA and CPB in the S WITCHING L INEARITY C OMPARISON B ETWEEN C ONVENTIONAL &
denominator cause a gain error which is irrelevant in the VCM-BASED M ETHODS
analysis. Subtracting the nominal value, the error term of the
MSB/2 transition (X = [010…0]) in the conventional method
is given by
CPB 2k−2 C
Verr (X)con = · VDD . (20)
Ca (CSL + CSM ) + CSL CSM
Correspondingly, for the Vcm -based method, the error term at
the MSB/2 transition (X = [0, 1/2…1/2]) is obtained as
C PB (2k−1 −1)C VDD
Verr (X)CM = C a (C SL +C SM )+C SL C SM · 2
C PB (2k−2 −1/2)C
= C a (C SL +C SM )+C SL C SM · VDD . (21)
From (20) and (21), it can be concluded that the Vcm -based
and the conventional switching have a similar INL.
The increased DNL due to the CPB is expected to
happen at the step below the last bit transition of the

Standard Deviation of INL(LSB)

0.18
MSB array. Considering the 10-b split DAC of Fig. 2(a) 0.16
with 5 b of MSB array and 5 b of LSB array, two 0.14
consecutive digital inputs for the conventional method are: 0.12
MSB/2
Transition
X = [0000100000]→ → (X − 1) = [0000011111], and 0.1
for the Vcm -based are: X = [0000, 1/2, 1/2, 1/2, 1/2, 1/2, 0.08
MSB Transition

1/2] → → (X − 1) = [0000011111]. On the other hand, 0.06

the error term CPB in (19) is only correlated with the bits 0.04 Vcm-based
in the MBS array. Accordingly, the difference between the 0.02
Conv.
two voltage errors is only caused by the bit Sm,1 in X. In
0
conclusion, the voltage errors for conventional and Vcm -based 0 100 200 300 400 500 600 700 800 900 1000
switching can be simply derived as Input Digital Code X
(a)
CPB C
Verr,con = · VDD
Standard Deviation of DNL(LSB)

(22) 0.35
Ca (CSL + CSM ) + CSL CSM Vcm-based
CPB C VDD 0.3 Conv.
Verr,CM = · . (23)
Ca (CSL + CSM ) + CSL CSM 2 0.25

As a consequence of (22) and (23), Vcm -based switching 0.2

reduces the DNL by half when compared with the conventional
0.15
switching. This benefit can be explained by the switching
nature of the Vcm -based method, which divides half of the 0.1
voltage contribution from the last bit of the MSB array, which 0.05
is CPB related, to all the capacitors in the LSB array that are
0
irrelevant to CPB . Table I summarizes the switching linearity 0 100 200 300 400 500 600 700 800 900 1000
of the two methods. Input Digital Code X
(b)
C. Behavioral Simulations
Fig. 4. Behavioral simulation comparing the DNL and INL of conventional
To verify the previous analysis, behavioral simulations were and Vcm -based 10-b SAR ADCs.
performed which modeled the conversion linearity of the
conventional and Vcm -based switching methods in a 10 b split
DAC array with 5 b MSB and 5 b LSB arrays. The values of MSB and MSB/2. The DNL plot shown in Fig. 4(b)
of the unit capacitor are Gaussian random variables with a confirms the presented analysis of Vcm -based switching that
standard deviation of σ (C/C = 1%), and the parasitic denotes two consecutive high DNLs at the middle. Their value
capacitance is not considered. Fig. 4 illustrates the result of is two times lower than its conventional counterpart.
1000-sample Monte Carlo runs, where the standard deviations The simulation estimates the effect of the parasitic capacitor
of DNLs and INLs with respect to a best fit line are plotted in the split structure supposing 10% top-plate parasitic with
versus the DAC input code at 10-b level. As expected, two matched capacitor. The DNLs and INLs results of conventional
methods have similarly large INLs, while Vcm -based switching and Vcm -based switching methods obtained by 100 000 points
has lower INLs at the transitions where the input code is more with sine wave input are shown in Fig. 5. The maximum DNLs
relevant to Vcm . This happens in the cases like the transitions and INLs of conventional and Vcm -based switching are 2.9
ZHU et al.: SPLIT-SAR ADCs 377

ADC Digital O utput

(before Cal .)
V in
Vout
D n+ 1
Dn
D n -1

Dn

Dn D ca l?
(a)
Y es No

R a n d o m C o d e D r w ith (D U D )
P(Dr;Dn-1,D n,D n+1)= 1 /3

Dr Dn

ADC Digital O utput

(after Cal .)
V in
Vout
D n+1
Dn
D n -1
(b)

Fig. 5. Behavioral simulation results of DNLs and INLs for 10-b SAR ADCs
with CPB . (a) Conventional switching. (b) Vcm -based switching.
Fig. 6. Code-randomized calibration algorithm. Dr has discrete uniform
distribution (DUD), which implies the probability (P) of any outcome Dr
LSB/1.5 LSB and 1.4 LSB/1.4 LSB, respectively. In Fig. 5, it from three possible values Dn − 1 , Dn , Dn + 1 is 1/3.
can be found that the ratio mismatch between the MSB and
LSB arrays, caused by CPB , results in the large quantization
errors, which happen periodically at the carry from LSB array From Fig. 5, it can be seen that the nonlinearity is a static
to the MSB array. Consequently, the interval between two conversion error, which happens periodically corresponding to
large quantization steps is 25 . Vcm -based method has two the number of bits distributed in the LSB array. Therefore, the
times better DNL than conventional while the INLs of the foreseeable static linearity errors can be potentially calibrated
two methods are quite similar. in the digital domain.
Ideally all the quantization levels of the n-bit ADC are
V. DNL AND INL C ALIBRATION T ECHNIQUE uniformly spaced, but due to nonideal elements in the actual
In practice, the conversion nonlinearity gets worse when the circuit implementation the code transition points in the transfer
conventional switching is used. Since there is a large switching function will be moved shown in Fig. 6. To calibrate the
transient in its “down” transition, caused by switching two linearity error, a code-randomized calibration is proposed,
capacitors simultaneously, the large switching transient causes which provides a plausible digital post-processing to fix the
the excessive supply voltage undershoot as well as potentially large quantization errors. This is achieved by redistributing
exacerbates an overdrive condition of the preamplifier, which the steps with statistically equally over the step’s ± LSB
will finally result in a wrong decision on the comparator’s range. The calibration algorithm is shown in Fig. 6. The digital
output. In contrast, Vcm -based switching prevents occurrence outputs used to find the DNL and INL errors are compensated
of such large switching transient. In every bit cycle, only one values, where the comparator offset and linear gain errors
capacitor is switched to obtain a voltage value by successive will not appear. First the calibration will determine whether
approximation of the input voltage without wasting energy the ADCs digital output needs to be corrected. For an n-bit
and settling time. Moreover, the mismatches of the attenuation ADC with the split DAC shown in Fig. 2(a) there are m
capacitor, as well as, the routing parasitic capacitance in (m = 2n /2i − 1) digital codes (Dcal = [D1 , D2 , …, Dm ]),
the internal node of the DAC, cause conversion nonlinearity. where large quantization steps happen and they are subject
378 IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, VOL. 22, NO. 2, FEBRUARY 2014

Fig. 9. Die microphotograph of the SAR ADC with Vcm -based switching.

Fig. 7. Calibrated DNL and INL of SAR ADC with conventional switching.

(a)

Fig. 8. Die microphotograph of the SAR ADC with conventional switching.

to be calibrated. When the ADCs digital output Dn matches (b)

any of the digital code in Dcal , the random number generator
will outcome a new digital output Dr . The randomized output Fig. 10. FFTs of the digital outputs with input at 1.8 MHz. (a) Conventional
SAR ADC sampled at 65 MS/s. (b) Vcm -based SAR ADC sampled at
Dr has one of the three possible values Dn and its two 100 MS/s.
adjacent quantization levels Dn − 1 and Dn + 1 , which are
equally spaced with an identical probability of 1/3. The
VI. M EASUREMENT R ESULTS
randomized solution transfers the nonlinearity into increased
average quantization noise power. Therefore, the large DNL Two 1.2 V 10-b SAR ADCs were fabricated in 90 nm
and INL errors can be calibrated with signal-to-noise distortion CMOS for conversion linearity comparison. The first chip
ratio (SNDR) of the ADC dropping slightly. Verified by a is a 10-b 65 MS/s SAR ADC with conventional switching,
behavior simulation of a 10 b level, the SNDR with and while the second chip is a 10-b 100 MS/s SAR ADC with
without code-randomized calibration is 56.2 and 55.6 dB, Vcm -based switching. The die micrographs of the two ADCs
respectively (32 768 samples are taken in a 10-b SAR ADC are shown in Figs. 8 and 9. 10-b (conventional) and 9-b
with 10% top-plate parasitic CPB , while ADC is otherwise (the MSB capacitance is removed due to the advantages of
ideal). Vcm -based switching) split DAC arrays were implemented to
The code-randomization calibration is used to calibrate the verify switching efficiency. The unit capacitance of a MIM
DNL errors shown in Fig. 5(a). For example, when the output capacitor is 50 fF, and the value of the attenuation capacitor
digital code D31 is detected, the system will auto-generate a Ca is 53.3 fF that is 16/15 unit. The Cs capacitor shown in
new digital output selected from the codes D30 , D31 , and D32 . Figs. 8 and 9 is used to implement the reference-buffer-free
Fig. 7 exhibits the calibrated DNL and INL results, where the technique [24] with a capacitance of 400 fF. On the other
maximum DNLs and INLs of the conventional method are hand, MIM capacitors exhibit very low top-plate parasitic,
both improved from 2.9 LSB to 1.3 LSB and 1.5 LSB to 1.4 estimated to be < 5%. The active areas of the conventional
LSB, respectively. and Vcm -based ADC are 0.56 and 0.18 mm2 , respectively.
ZHU et al.: SPLIT-SAR ADCs 379

TABLE II
S UMMARY OF P ERFORMANCE

Switching Method Conventional Vcm -Based

Technology 90-nm CMOS 90-nm CMOS
Resolution 10-b 10-b
Sampling Rate 65-MS/s 100-MS/s
Supply Voltage 1.2 V 1.2 V
1.2VPP
Full Scale Analog Input 1.2VPP differential
differential
SNDR 54.7 dB 56.6 dB
SFDR 66 dB 71 dB
ENOB 8.8-b 9.1-b
+ 0.79/- 0.27
DNL + 3/–1 LSB
LSB
+ 0.86/- 0.78
Fig. 11. Measured INL and DNL of 10-b SAR ADC with conventional INL + 2.8/–1.6 LSB
switching. LSB
DNL after Cal. + 0.9/–0.7 LSB N/A
INL after Cal. + 1/–1.1 LSB N/A
Power Consumption
Sampling&DAC 1.7 mW 600$\muW$
Comparator 3.3 mW 800$\muW$
CLK Gen & SA Log 3.2 mW 1.6 mW
Total Power 8.2 mW 3 mW
FOM = Power/2ENOB∗fs 280 fJ/conv-step 55 fJ/conv-step

Fig. 12. Measured INL and DNL of 10-b SAR ADC with Vcm -based
switching.

Fig. 10 shows output spectrums of the two ADCs with the

input frequency at 1.8 MHz. The conventional SAR ADC can
achieve 8.6 b ENOB at a sampling rate of 65 MS/s. When the
Vcm -based approach is utilized, the ADC can achieve100 MS/s
sampling rate and the ENOB is improved to 9.1 b.
The measured DNL and INL of the ADC with conventional
and Vcm -based switching are illustrated in Figs. 11 and Fig. 13. Measured INL and DNL of 10-b SAR ADC with conventional
12, respectively. The experimental measurements verify the switching after calibration.
benefits of Vcm -based switching approach that exhibits a lower
DNL and INL when compared with the conventional one. By
utilizing Vcm -based switching, the maximum DNL and INL is not a dominant factor in this design and the proposed
are improved from 3 to 0.79 LSB and from 2.8 to 0.86 LSB, digital calibration technique is applied to correct all the
respectively. The INL from Fig. 12 is s-like and is minimized large nonlinearity codes. The calibrated DNL and INL results
in the middle, while in Fig. 11, it is quite large in both MSB are presented in Fig. 13, where the large DNL and INL
and MSB/2 transitions. The advantage of Vcm -based switching can be significantly reduced from 3 to 0.9 LSB and from
stems from the MSB decision’s independence of the capacitor 2.8 to 1.1 LSB, respectively. The SNDR drops by 0.5 dB
mismatch. This was discussed in Section IV-A. upon the calibration. For the second SAR ADC, due to the
Fig. 11 shows that the high spikes are not symmetrically advantages of Vcm -based switching, no missing codes are
distributed. This is mainly caused by the large switching presented implying that calibration is not necessary.
transients leading to insufficient DAC settling and supply The measured performances of the two prototype
ripples. The effect of parasitic capacitors of a split DAC SAR ADCs are summarized in Table II. The second
380 IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, VOL. 22, NO. 2, FEBRUARY 2014

TABLE III
I SOTHERMAL S OLIDIFICATION R EACTION R ATE C ONSTANTS E STIMATED U SING DSC D ATA

[3] VLSI’09 [6] ISSCC’08 This paper

[2] ISSCC’08 [9] ISSCC’09
[24] JSSC’10
Architecture SAR SAR Pipelined Pipelined SAR
Technology (nm) 90 130 65 180 90
Resolution (bit) 9 10 10 10 10
Sampling rate (MS/s) 40 50 100 50 100
Supply voltage (V) 1 1.2 1.2 1.8 1.2
SNDR (dB) 53.3 52.8 59 58.2 56.6
ENOB (bit) 8.6 8.5 9.5 9.4 9.1
DNL (LSB) + 0.7/–0.45 + 0.88/–1 + 0.1/–0.1 N/A + 0.79/–0.27
INL (LSB) + 0.56/–0.65 + 2.2/–2.09 + 0.2/–0.2 + 0.7/–0.8 + 0.86/–0.78
Power (mW) 0.82 0.92 4.5 9.9 3
FOM = Power/2ENOB∗fs
54 52 62 300 55
(fJ/conv-step)

design consumes 5.2 mW lower power than the first, inductive switching noise due to the current transient of the
of which 2.7 mW is the benefit from the Vcm -based DAC becomes the critical and dominating contribution for
switching due to the reduction of switching power as the total reference noise. Thus, it is necessary to analyze the
well as the digital power from switching buffers. Another reference safety margin to guarantee the expected conversion
2.5 mW of power reduction is due to the utilization of the accuracy.
dynamic comparator. Considering all the power benefits, the The differential DAC for conventional and Vcm -based
figure-of-merit (FoM) of the second design is improved from switching with the simplified power networks are shown in
280 fJ/conv-step to 55 fJ/conv-step. Table III benchmarks the Fig. 14. In Vcm -based switching after (n − 1) bit cycling, the
prototype Vcm -based SAR ADC (Fig. 9) with state-of-the-art DACs will finally settle to a value for LSBs decision. The
ADCs. The design achieves competitive FoM for high-speed differential DAC output is quite sensitive to supply variations,
implementation. especially in the most critical case where the bottom plates
of all the DAC capacitors (on the signal side) are connected
VII. C ONCLUSION to VDD . Since the operation is differential, considering one of
Two 1.2 V 10-b SAR ADCs operating at tens of MS/s the corresponding cases: all bits in Vop1 are “1” and all bits in
with conventional and Vcm -based switching were presented. Von1 are “0,” the differential output Vout of the DACs can be
The linearity behaviors of the DACs switching and structure represented as
were analyzed and verified by both simulated and measured Vout = Vop1 − Von1
results. The Vcm -based switching technique provides superior  n−1 
2 −1 1 1
conversion linearity when compared with the conventional = (VDD + V ) + n−1 Vcm ] − n−1 Vcm
method because of its array’s capacitors correlation during 2n−1 2 2
each bit cycling. The proposed code-randomized calibration (24)
can eliminate the large DNL and INL errors in the where V is the variation of the supply. Equation (24) is
conventional switching. Measured results demonstrated that independent of Vcm , since the differential operation cancels the
both higher speed and lower power is achieved by using relative terms. Consequently, the voltage error Verr is obtained
Vcm -based switching. as
2n−1 − 1
Verr = V ≈ V. (25)
A PPENDIX 2n−1
A. Sensitivity to Supply Noise It requires that the error term |V |due to the
Using supply as a reference, removes not only the static supply-noise needs to be suppressed within
power required in the resistive ladder and high-speed voltage 1/4 LSB (LSB = 1/2 n VFS = 1/2 n − 1 VDD ). Then,
buffer, but also their noise contribution. However, the package leading to
|V | 1
bonding inductor will generate switching noise with undesired < n+1 . (26)
ringing effect. In modern SoC design, the analog circuitry will VDD 2
be normally biased by a dedicated linear voltage regulator or For 10-b accuracy, the supply variation needs to be
LDO to isolate the large system digital noise. Commercial suppressed within ± 0.049% of the full supply rail. It means
low-noise voltage regulator products achieve around several that the supply ripple <± 588 μV for a 1.2 V supply. The
tens of μV RMS within a bandwidth of hundreds of KHz supply ripple due to the switching effect is not problematic
[30]. The proper placement of the decoupling capacitor can for a low speed SAR, since the DAC settling time is large
effectively attenuate the high-frequency noise. Therefore, the enough. However, in high-speed designs, the request becomes
ZHU et al.: SPLIT-SAR ADCs 381

Conv.
Vcm-based
R R

VDD-Gnd

1.2V
460μV

3.4mV

10n t

Fig. 16. Supply waveform of performing the conventional and Vcm -based
switching in a 10 b SAR ADC with the unit capacitance of 50 fF.

Fig. 14. Simplified supply network and differential DACs to perform

Vcm -based and conventional switching.

Fig. 17. Simulated supply variations versus sweeping of CP and supply

inductance in a 10 b Vcm -based SAR ADC (9-b split DAC is used with a
unit capacitance of 50 fF).

applied to a 10-b and 9-b split DAC with a unit capacitance

of 50 fF).
The inductive ringing effect can be well suppressed by
minimizing the bonding inductance, e.g., multiple bonding,
Fig. 15. Behavioral simulation of SNDR versus the supply noise in a 10-b
SAR ADC (10-b split DAC is used with a unit capacitance of 50 fF). adding damping resistor, and on-chip decoupling capacitor
Cdecp . Fig. 17 presents a plot of supply variation versus the
sweeping of Cdecp and bonding inductance in a 10 b Vcm -based
quite stringent. The design of a 10-b SAR running at 100 MS/s SAR. It can be deduced that to achieve 10-b accuracy, with
involves an overall time, available to determine each bit, 2–5 nH bonding inductance, it would be necessary to have a
which is < 1 ns, including the time for comparison, SR decoupling capacitor with an approximate value of 500 pF, to
logic delay, and DAC settling. A behavioral simulation shows suppress the switching reference noise. This value penalizes
that the conversion sensitivity to supply variation of a 10-b the die area, e.g., using typical pMOS as the decoupling
100 MS/s SAR ADC is within ± 600 μV, as illustrated capacitor with W × L equal to 5 × 5 μm, the area for 500 pF
in Fig. 15. According to the switching sequences of the would be close to 0.04 mm2 . On the other hand, some SA
binary-searched algorithm, the most critical transition happens searching algorithm like the nonbinary conversion [27] that
at the charging of the largest capacitor. Since the Vcm -based relaxes the settling accuracy requirement during large switch
switching charges 75% less capacitance, simultaneously, when transients would be the effective approach to overcome this
compared with the conventional switching, it can effectively problem.
reduce the under-shoot of the supply or reference buffer (when
used). The supply waveforms of conventional and Vcm -based ACKNOWLEDGMENT
methods with a switching frequency of 1 GHz are illustrated The authors would like to express their sincere appreciation
in Fig. 16 (Conventional and the Vcm -based switching are to H. Venkatesan for the language editing and proofreading.
382 IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, VOL. 22, NO. 2, FEBRUARY 2014

R EFERENCES [21] Y. Zhu, C.-H. Chan, U.-F. Chio, S.-W. Sin, U. Seng-Pan, and
R. P. Martins, “A voltage feedback charge compensation technique for
[1] J. Craninckx and G. V. Plas, “A 65 fJ/conversion-step 0-to-50 MS/s split DAC architecture in SAR ADCs,” in Proc. IEEE Int. Symp. Circuits
0-to-0.7 mW 9b charge-sharing SAR ADC in 90 nm digital CMOS,” Syst., May 2010, pp. 4061–4064.
in IEEE Int. Solid-State Circuits Conf., Dig. Tech. Papers, Feb. 2007, [22] S. Wong, Y. Zhu, C.-H. Chan, U.-F. Chio, S.-W. Sin, U. Seng-Pan,
pp. 246–247. and R. P. Martins, “Parasitic calibration by two-step ratio approaching
[2] V. Giannini, P. Nuzzo, V. Chironi, A. Baschirotto, G. Van der Plas, and technique for split capacitor array SAR ADCs,” in Proc. IEEE SoC
J. Craninckx, “An 820 μW 9b 40 MS/s noise-tolerant dynamic-SAR Design Conf. Int., Nov. 2009, pp. 333–336.
ADC in 90 nm digital CMOS,” in IEEE Int. Solid-State Circuits Conf., [23] B. P. Ginsburg and A. P. Chandrakasan, “500-MS/s 5-bit ADC in 65-nm
Dig. Tech. Papers, Feb. 2008, pp. 238–610. CMOS with split capacitor array DAC,” IEEE J. Solid-State Circuits, vol.
[3] C. C. Liu, S.-J. Chang, G.-Y. Huang, and Y.-Z. Lin, “A 0.92 mW 10-bit 42, no. 4, pp. 739–747, Apr. 2007.
50-MS/s SAR ADC in 0.13 μm CMOS process,” in Symp. VLSI Circuits [24] Y. Zhu, C. H. Chan, U-F. Chio, S.W. Sin, U. Seng-Pan, R. P. Martins,
Dig. Tech. Papers, Jun. 2009, pp. 236–237. and F. Maloberti, “A 10-bit 100-MS/s reference-free SAR ADC in 90
[4] P. Harpe, Z. Cui, W. Xiaoyan, G. Dolmans, and H. de Groot, “A 30 nm CMOS,” IEEE J. Solid-State Circuits, vol. 45, no. 6, pp. 1111–1121,
fJ/conversion-step 8b 0-to-10 MS/s asynchronous SAR ADC in 90 nm Jun. 2010.
CMOS,” in IEEE Int. Solid-State Circuits Conf., Dig. Tech. Papers, [25] B. P. Ginsburg and A. P. Chandrakasan, “An energy-efficient charge
Feb. 2010, pp. 388–389. recycling approach for a SAR converter with capacitive DAC,” in Proc.
[5] M. Boulemnakher, E. Andre, J. Roux, and F. Paillardet, “A 1.2V 4.5 mW IEEE Int. Symp. Circuits Syst., May 2005, pp. 184–187.
10b 100 MS/s pipeline ADC,” in IEEE Int. Solid-State Circuits Conf., [26] U.-F. Chio, H.-G. Wei, Y. Zhu, S.-W. Sin, U. Seng-Pan,
Dig. Tech. Papers, Feb. 2008, pp. 250–251. and R. P. Martins, “A self-timing switch-driving register by
[6] S. T. Ryu, B. S. Song, and K. Bacrania, “A 10b 50 MS/s opamp-sharing precharge-evaluate logic for high-speed SAR ADCs,” in Proc. IEEE
pipeline A/D with current-reuse OTAs,” IEEE J. Solid-State Circuits, Asia Pacific Conf. Circuits Syst., Dec. 2008, pp. 1164–1167.
vol. 42, no. 3, pp. 475–485, Mar. 2007. [27] F. Kuttner, “A 1.2-V 10-b 20-Msample/s nonbinary successive
[7] K. Chandrashekar and B. Bakkaloglu, “A 1.8-V 22-mW 10-bit 30MS/s approximation ADC in 0.13-μm CMOS,” in IEEE Int. Solid-State
pipelined CMOS ADC for low-power subsampling applications,” Circuits Conf. Dig. Tech. Papers, Feb. 2002, pp. 176–177.
IEEE Trans. Very Large Scale Integr. (VLSI) Syst., vol. 19, no. 2, [28] M. Gustavsson, J. J. Wikner, and N. Tan, CMOS Data Converters for
pp. 1610–1616, Sep. 2011. Communications, Norwell, MA, USA: Kluwer, 2000.
[8] I. Ahmed, J. Mulder, and D. A. Johns, “A 50 MS/s 9.9 mW pipeline ADC [29] Y. Zhu, U.-F. Chio, H.-G. Wei, S.-W. Sin, U. Seng-Pan, and
with 58dB SNDR in 0.18 μm CMOS using capacitive charge-pumps,” R. P. Martins, “Linearity analysis on a series-split capacitor array for
in IEEE Int. Solid-State Circuits Conf., Dig. Tech. Papers, Feb. 2009, high-speed SAR ADCs,” in Proc. IEEE Midwest Symp. Circuits Syst.,
pp. 164–165. Aug. 2008, pp. 922–925.
[9] J. Hu, N. Dolev, and B. Murmann, “A 9.4-bit, 50-MS/s, 1.44-mW [30] Datasheet of Low Dropout Linear Regulator (2012). Standard
pipelined ADC using dynamic residue amplification,” in Symp. VLSI ADP1752/ADP1753.
Circuits Dig. Tech. Papers, Jun. 2008, pp. 216–217.
[10] O. A. Adeniran, A. Demosthenous, C. Clifton, S. Atungsiri, and R. Soin,
“A CMOS low-power ADC for DVB-T and DVB-H systems,” in Proc.
IEEE Int. Symp. Circuits Syst., vol. 1. May 2004, pp. 209–212.
[11] U.-F. Chio, H.-G. Wei, Z. Yan, S. Sai-Weng, U. Seng-Pan, R. P. Martins,
and F. Maloberti, “Design and experimental verification of a power
effective Flash-SAR subranging ADC,” IEEE Trans. Circuits Syst. II, Yan Zhu (S’10–M’12) received the B.Sc. degree in electrical engineering
Exp. Briefs, vol. 57, no. 8, pp. 607–611, Aug. 2010. and automation from Shanghai University, Shanghai, China, in 2006, and the
[12] Y. Zhu, U.-F. Chio, H.-G. Wei, S.-W. Sin, U. Seng-Pan, and M.Sc. and Ph.D. degrees in electrical and electronics engineering from the
R. P. Martins, “A power-efficient capacitor structure for high-speed University of Macau Macao, China, in 2009 and 2011, respectively.
charge recycling SAR ADCs,” in Proc. IEEE Int. Conf. Electron. Circuits She is currently a Post-Doctoral Researcher with the State Key Laboratory
Syst., Aug.–Sep. 2008, pp. 642–645. of Analog and Mixed-Signal VLSI, University of Macau, Macao, China. Her
[13] Z. Cao, S. Yan, and Y. Li, “A 32 mW 1.25 GS/s 6b 2b/step SAR ADC current research interests include low-power and wideband high-speed Nyquist
in 0.13 μm CMOS,” in Int. Solid-State Circuits Conf. Dig. Tech. Papers, A/D converters as well as digitally assisted data converter designs.
pp. 542–543, Feb. 2008.
[14] M. Saberi, R. Lotfi, K. Mafinezhad, and W. A. Serdijn, “Analysis
of power consumption and linearity in capacitive digital-to-analog
converters used in successive approximation ADCs,” IEEE Trans. Circuit
Syst. I, Regular Papers, vol. 58, no. 8, pp. 1736–1748, Aug. 2011.
[15] Y.-K. Cho, Y.-D. Jeon, J.-W. Nam, and J.-K. Kwon, “A 9-bit 80 MS/s Chi-Hang Chan (S’12) received the B.Sc. degree from the University of
successive approximation register analog-to-digital converter with a Washington, Seattle, WA, USA, and the M.Sc. degree from the University
capacitor reduction technique,” IEEE Trans. Circuit Syst. II, Exp. Briefs, of Macau, Macao, China, in 2012, where he is currently pursuing the Ph.D.
vol. 57, no. 7, pp. 502–506, Jul. 2010. degree.
[16] M. S. W. Chen and R. W. Brodersen, “A 6b 600 MS/s 5.3-mW He was an intern in Synopsys-Chipidea Microelectronics, Macau,
asynchronous ADC in 0.13-μm CMOS,” in IEEE Int. Solid-State during his undergraduate studies. His current research interests include
Circuits Conf. Dig. Tech. Papers, Feb. 2006, pp. 574–575. gigahertz-range ADCs with low and moderate resolution, comparator, dynamic
[17] Y. Chen, S. Tsukamoto, and T. Kuroda, “A 9b 100 MS/s 1.46 mW SAR circuit design, and mixed-signal layout consideration.
ADC in 65 nm CMOS,” in Proc. IEEE Asian Solid-State Circuits Conf.,
Nov. 2009, pp. 145–148.
[18] A. Agnes, E. Bonizzoni, P. Malcovati, and F. Maloberti, “A 9.4-ENOB
1V 3.8μW 100 kS/s SAR ADC with time-domain comparator,” in Int.
Solid-State Circuits Conf. Dig. Tech. Papers, Feb. 2008, pp. 246–247.
[19] Y. F. Chen, X. Zhu, H. Tamura, M. Kibune, Y. Tomita, T. Hamada, U-Fat Chio received the B.Sc. degree in electrical engineering and the M.Sc.
M. Yoshioka, K. Ishikawa, T. Takayama, J. Ogawa, S. Tsukamoto, and degree in communications engineering from National Sun Yat-Sen University,
T. Kuroda, “Split capacitor DAC mismatch calibration in successive Kaohsiung, Taiwan, in 2002 and 2004, respectively, and the Ph.D. degree from
approximation ADC,” in Proc. IEEE Custom Integr. Circuits Conf., the University of Macau, Macao, China, in 2012.
Sep. 2009, pp. 279–482. He was with Den MOS Technology Inc., Hsinchu, Taiwan, from 2004 to
[20] M. Yoshioka, K. Ishikawa, T. Takayama, and S. Tsukamoto, “10b 2005. He is currently a Post-Doctoral Fellow with the State Key Laboratory
50 MS/s 820 μW SAR ADC with on-chip digital calibration,” in of Analog and Mixed-Signal VLSI, University of Macau. His current
IEEE Int. Solid-State Circuits Conf. Dig. Tech. Papers, Feb. 2010, research interests include high-speed analog-to-digital converters and power
pp. 384–385. management circuit designs.
ZHU et al.: SPLIT-SAR ADCs 383

Sai-Weng Sin (S’98–M’06) received the B.Sc., M.Sc., and Ph.D. degrees He has been with the Department of Electrical and Computer Engineering
(with highest honor) in electrical and electronics engineering from the (DECE)/IST, TU of Lisbon, since October 1980. Since 1992, he has been
University of Macau, Macao, China, in 2001, 2003, and 2008, respectively. on leave from IST, TU of Lisbon, and is also with the Department of
He is currently an Assistant Professor with the Faculty of Science and Electrical and Computer Engineering, Faculty of Science and Technology
Technology, University of Macau, Macao, China, and is the Coordinator of the (FST), University of Macau (UM), Macao, China, where he has been a Full
Data Conversion and Signal Processing (DCSP) Research Line in State-Key Professor since 1998. At FST, he was the Dean of the Faculty from 1994 to
Laboratory of Analog and Mixed-Signal VLSI, University of Macau. He has 1997 and he has been Vice-Rector of the University of Macau since 1997.
authored one book, entitled Generalized Low-Voltage Circuit Techniques for From September 2008, after the reform of the UM Charter, he was nominated
Very High-Speed Time-Interleaved Analog-to-Digital Converters (Springer) after open international recruitment as Vice-Rector (Research) until August
and over 70 technical journals and conference papers in the field of 31, 2013. Within the scope of his teaching and research activities, he has
high-performance data converters and analog mixed-signal integrated circuits. taught 21 bachelor and master courses and has supervised (or cosupervised) 25
Dr. Sin has been a member of the Technical Program Committee theses, Ph.D. (11) and Masters (14). He has published 12 books, coauthoring
of IEEE Sensors 2011 and IEEE RFIT 2011–2012 Conference, Review five and coediting seven, plus five book chapters, 230 refereed papers, in
Committee Member of Prime Asia 2009 Conference, Technical Program, scientific journals and conference proceedings, as well as other 70 academic
and Organization Committee of the 2004 IEEJ AVLSI Workshop, as well works, in a total of 317 publications. He has coauthored four U.S. Patents
as the Special Session Co-Chair and Technical Program Committee Member (two issued in 2009 and two in 2011) and with another six pending. He
of 2008 IEEE APCCAS Conference. He is currently the Secretary of the has created the Analog and Mixed-Signal VLSI Research Laboratory of UM,
IEEE Solid-State Circuit Society (SSCS) Macau Chapter and IEEE Macau elevated in January 2011 to State Key Lab of China (the 1st in Engineering in
CAS/COM Joint Chapter. He was the co-recipient of the 2011 ISSCC Silk Macao), being its Founding Director. He is the financial manager, recognized
Road Award, Student Design Contest winner in A-SSCC 2011 and the 2011 by the European Union, of a Jean Monnet Chair in “EULaw-Facing the
State Science and Technology Progress Award (second-class), China. Constitution and Governance Challenges in the Era of Globalization”, unique
in the universities from HK & Macao, for the period 2007 to 2012.
Prof. Rui Martins was the Founding Chairman of the IEEE Macau Section
Seng-Pan U (S’94–M’00–SM’05) received the B.Sc. and M.Sc. degrees in from 2003 to 2005 and of the IEEE Macau Joint-Chapter on Circuits And
1991 and 1997, respectively, and the joint Ph.D. degree (with highest honor) in Systems (CAS)/Communications (COM) from 2005 to 2008 (2009 World
high-speed analog IC design from the University of Macau, Macao, China, the Chapter of the Year of the IEEE Circuits nd Systems (CAS) Society). He was
Instituto Superior Técnico, Universidade Técnica de Lisboa, Lisbon, Portugal, the General Chair of the 2008 IEEE Asia-Pacific Conference on Circuits And
(IST/UTL) in 2002. Systems- APCCAS’2008, and was the Vice-President for the Region 10 (Asia,
He has been with the Department of Electrical and Electronic Engineering, Australia, the Pacific) of the IEEE CAS Society for the period 2009 to 2011.
Faculty of Science and Technology (FST), University of Macau, since He was elected recently to the position of Vice-President (World) Regional
1994, where he is currently a Professor and Deputy Director of State-Key Activities and Membership also of the IEEE CAS Society for the period
Laboratory of Analog & Mixed-Signal VLSI of UM. From 1999 to 2001, 2012 to 2013. He has been an Associate Editor of the IEEE T RANSACTIONS
he was also on leave to the Integrated CAS Group, Center of Microsystems, ON C IRCUITS AND S YSTEMS II: E XPRESS B RIEFS since 2010. He was the
IST/UTL, as a Visiting Research Fellow. In 2001, he co-founded the Chipidea recipient of two government decorations: the Medal of Professional Merit from
Microelectronics (Macau), Ltd., Macau, and was the Engineering Director and Macao Government (Portuguese Administration) in 1999, and the Honorary
since 2003 the corporate Vice-President of IP Operations Asia Pacific and Title of Value from Macao SAR Government (Chinese Administration) in
site General Manager of the company for devoting in advanced analog and 2001. In July 2010 he was unanimously elected, as a Corresponding Member
mixed-signal Semiconductor IP (SIP) product development. Chipidea Group of the Portuguese Academy of Sciences (in Lisbon), being the only Portuguese
was acquired in May 2009 by Synopsys Inc. (NASDAQ: SNPS), the world academician living in Asia.
leading EDA and IP provider, he is currently the corporate Senior Analog
Design Manager and Site General Manager. He holds five U.S. patents and has
co-authored Design of Very High-Frequency Multirate SC Circuits—Extending
the Boundaries of CMOS AFE Filtering, Analog-Baseband Architectures
and Circuits for Multistandard and Low-Voltage Wireless Transceivers, and Franco Maloberti (A’84-SM’97-F’96) received the Laurea degree in physics
Generalized Low-Voltage Circuit Techniques for Very High-Speed TI ADCs (summa cum laude) from the University of Parma, Parma, Italy, in 1968, and
(Springer), and the foremost one was selected in 2007 by China Science Press the Dr. Honoris Causa degree in electronics from Inaoe, Puebla, Mexico, in
for republication in The Overseas Electronics & Information Book Excellence 1996. He was a Visiting Professor with ETH-PEL, Zurich, in 1993 and with
Series. EPFL-LEG, Lausanne, in 2004.
Dr. U was the recipient of various scholarship and R&D grants He was a Professor of Microelectronics and Head of the Micro
and published more than 120 scientific papers in IEEE/IET journal and Integrated Systems Group University of Pavia, Pavia, Italy, TI/J.Kilby Analog
conferences. He has received 20_ research & academic/teaching awards and is Engineering Chair Professor with the Texas A&M University and the
also the advisor for 20_ various international student paper award recipients, Distinguished Microelectronic Chair Professor with University of Texas at
e.g., ISSCC Silk-Road Award, IEEE DAC/ISSCC Student Design Contest, Dallas. Currently, he is a Professor with the University of Pavia, Pavia, Italy,
A-SSCC Student Design Contest, ISCAS, MWSCAS, and IEEE PRIME. He and Honorary Professor with the University of Macau, Macao, China. He has
also received, at the first time from Macau, the Scientific and Technological written more than 450 published papers, five books, and holds 30 patents.
Innovation Award of Ho Leung Ho Lee Foundation in 2010, and The State He has been responsible for many research programs including ten ESPRIT
Scientific and Technological Progress Award in 2011. In recognition of his projects and served the European Commission in many European Initiatives.
contribution in high-technology research & industrial development in Macau, He served the Academy of Finland on the assessment of electronic research.
he was awarded by Macau SAR government the Honorary Title of Value He served the National Research Council of Portugal for the research activity
in 2010. He is currently the Industrial Relationship Officer of IEEE Macau assessment of Portuguese Universities. He is the Chairman of the Academic
Section, the Chairman of the IEEE Macau CAS/COMM chapter, and the Committee of the State Key Laboratory of Analog and Mixed-Signal VLSI,
founding Chairman of the IEEE Macau SSC Chapter. He has been with University of Macau, Macao, China.
technical review committee of various international scientific journals and Prof. Maloberti was VP Region 8 of the IEEE Circuits and Systems
conferences for many years, e.g., JSSC, TCAS, IEICE, and ISCAS. He was (CAS) Society (1995-1997), Associate Editor of the IEEE T RANSACTIONS
the Chairman of the local organization committee of IEEJ AVLSIWS’04, ON C IRCUITS AND S YSTEMS -II: E XPRESS B RIEFS , President of the IEEE
the Technical Program co-Chair of IEEE APCCAS’08, ICICS’09 and Sensor Council (2002-2003), an IEEE CAS BoG member (2003-2005), and
PRIMEAsia’11. He is currently the Technical Program Committee of RFIT, VP Publications for IEEE CAS (2007-2008). He was a Distinguished Lecturer
VLSI-DAT, and A-SSCC. for the IEEE Solid-State Circuits Society (2009-2010) and presently is a
Distinguished Lecturer for the IEEE CAS Society. He received the 1999
IEEE CAS Society Meritorious Service Award, the 2000 CAS Society Golden
Rui Paulo Martins (M’88-SM’99-F’08) was born on April 30, 1957. He Jubilee Medal, and the IEEE Millenium Medal. He received the 1996 IEE
received the B.Sc, M.Sc. and Ph.D. degrees, as well as the Habilitation for Fleming Premium, the ESSCIRC 2007 Best Paper Award and the IEEJ
Full-Professor, in electrical engineering and computers from Instituto Superior Workshop 2007, and 2010 Best Paper Award. He is IEEE Fellow. In 1992,
Técnico (IST), TU of Lisbon, Lisbon, Portugal, in 1980, 1985, 1992, and 2001, he was a recipient of the XII Pedriali Prize for his technical and scientific
respectively. contributions to national industrial production.

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