Feature of Microprocessor 8086 ‘It is upgraded microprocessor from 8085. 8086 has following features: D 8086 has 16 bits ALU. [Older version 8085 has & bits of ALU.] So, operating speed 8086 have increased significantly well. 8086 has 16 bits of Data bus. So in one machine cycle it can transfer 2 bytes. [Older version 8085 has 8 bits of data bus.) C8086 has 20 bits of Address bus. With 8086 we can interface total memory by 2?°= 1MB [Older version 8085 has 16bits Address bus.) £086 has two internal hardware units. B1U — Bus Interface Unit & EU ~ Execution Unit. D 8086 supports pipelining. So Multiple instructions can be executed in parallel to increase execution speed of microprocessor. Gi Four 16 bits general purpose registers (AX, BX, CX & DX). We can use it with 8 bits also (AH, AL, BH, BL, CH, CL, DH, DL). Two 16 bits Index registers (SI and Di). Two 16 bits stack pointers (SP and BP). 8086 supports memory segmentation. (CS, DS, ES and SS) 16 bie flag register.Architecture of Microprocessor 8086Bus Interface Unit of Microprocessor 8086 4 BIU is responsible for establishing communications + Instruction Queue with external peripheral devices and memory via! I BIU prefetches six instruction bytes in advance system bus. from memory. ‘> Main Purpose of BIU serves is as followed G. The prefetched instructions are stored in a group of Itfetches the instructions from Memory high speed registers known instruction queve. Bheeede be weaiiees THisinstruction queve works on FIFO oder. 2 ttwrites data into 10 and Memory Biv and EU works in paratiel, G1 It provides the address relocation facility G Tin Geatteees cpentien of OU ont Os BIU contains three main parts eae ems Ree ere 2 irsreton ue Te process of fetching the next instrcion In Bipsoeee advance while the EU Is executing the current instruction is pipelining o cme Instruction Stream Byte QueueBus Interface Unit of Microprocessor 8086 ‘+ Segment Register of BIU {+ Segment Register of BIU is used to store the The 8086 MP has the capability of addressing 1MB _ starting address of Memory segment. memory, which is divided into 16 local segments, | + BIU generates 20 bits address using segment Each segment contains 64KB memory register and Offset pointer registers. ut any instant 8086 works with only four 64x | PA=SRX 10H + OP segments. “+ Instruction Pointer of BIU ” ‘® Each segment associated with segment register CIP holds the address of next instruction which is to D Code Segment Register CS~16bits bbe executed next. 1D Data Segment Register DS. 16bits It contains the OFFSET value of next Address. Stack Segment Register SS ~ 16bits Extra Segment Register ES— 16bitsExecution Unit of Microprocessor 8086 ‘+ EU informs BIU from where the next instruction or ! «+ ALU of EU data to be fetched. 1 ttperforms all the arithmetic and logical operations. ‘The EU performs folowing functions: |B Results may be stored in general purpose registers or It picks up the instruction from the instruction Index registers. queue of BU. OD Itupdates Flag register after every instructions. It decode the instructions and then executes the | & General Purpose Registers & Pointer of EU Instruction. EU have four general purpose registers. 1 Itupdates the status of flag register. These registers are used for accessing data very fast. control Unit EV have SP and BP for stack. Itis controlling and coordinating all the activities of | 1 Index registers are SI and I for data and Extra sub units segments, respectively. 1 Itfetches, decodes and executes instructions. It gives controt signals tke read, write et.Pin Diagram of Microprocessor 8086 BBBBBESES 22k—ReaDy RESET ®icry Ra/cT) (ocx) & (@sy (as),Pin Diagram of Microprocessor 8086 4 Address Data Bus — [(ADO-AD15] ‘A00-A015 C1 8086 has 20 nes for Address bus and 16 Data Lines. aegis i Here, ADO ADIS are time multiplexed Address Data /s3 Lines and can be separated by ALE terminal. 7 COIFALE = 1 then it carries Address [AO-A15] and If ALE = Othen it carries data (D0-D15}. Address Status Lines ~ [A19/S6-A16/S3] 18086 has 4 time multiplexed Address status lines [A19/S6 ~ A16/S3. and can be separated by ALE terminal. IF ALE = 1, then it carries Address [A19-A16] and If ‘ALE = 0 then it carries Status signals [56-53]. ‘ Status signals {57/53} ss & S4 indicates which segment is accessed by 8085 during current bus cycle. 55 reflects IF fag register. Sis always zero. 57s always one.Pin Diagram of Microprocessor 8086 G ‘© Bus High Enable ~ (BHE/S7) 1D This line is used to enable 015-08 of 015-D0. — Its used by Microprocessor for memory banking. Apo ADIs Lid ‘& Non Maskable Inte st — [NMI] = ion Mashable interrupt ~ aie. 1D This line is used give highest priority interrupt to - Microprocessor 8086. 1D Itean not be disabled by the software. som 1D itis postive edge triggered interrupt. When tocar, Type 2 Interrupt occursin the 886. Tura * Interrupt Request —[INTR] 1D This s level riggered hardware interrupt. O It depends of status of Interrupt Flag. INTR= 1, the 8086 gets interrupted. SG itiF=0,imTR= 1, then NTRS disabled.Pin Diagram of Microprocessor 8086 “System Clock ~ [CLK] ADO-ADIS Clock i given to 8086 for internal timings. A1s/ss- 1 Clock with 8086 is Swi, MHz & 20Mhz. At6/S3 + Minimum & Maximum Mode [MN/BIX] {For Minimum Mode connected with Ve. With Minimum Mode 8086 will work as single ‘microprocessor. 1 For Maximum Mode connected with ground. ana D With Maximum mode 8086 will works with multiple NTR coprocessor, INTA —_& Ready Signal [READY] This input is used to insert the wait state into timing, cycle of microprocessor 8086. ax if the ready pin is at logic 4, it has no effect on the nsx ‘operation. Ready IF itis logic 0, 8086 enters into the wait state lke idle. =D iis used to synchronize slow peripheral devices. “ Read (RD) COM it is logic 0, Microprocessor reads data from ‘Memory or 10 devices.Pin Diagram of Microprocessor 8086 “+ System Reset [RESET] {This input will reset microprocessor 8086. if it held logic 1 for minimum of 4 elock cycles then ‘microprocessor will get RESET. Gl atfter RESET of 8085, CS an: ized to FFFFH and 0000H, so physical address will be FFFFOH. Remaining registers initialized to zero. Test (TEST) 1 Itis used for synchronization. When this input is logic 0, 8086 executes WAIT Instruction. * Power Supply [Vec & Ground] C8086 is given with 5 Volt DC supply. 1 Allowed variation is 10%. 8086 has two ground pins. This two ground pins are there to have less power dissipation. e