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Digital Logic Design

leaked question paper for practice DSD

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Anurag Jaiswal
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36 views2 pages

Digital Logic Design

leaked question paper for practice DSD

Uploaded by

Anurag Jaiswal
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PDF, TXT or read online on Scribd
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Course Code : EDT 202 / ENT 202 CXDW/RW – 18 / 5029

Third Semester B. E. ( Electronics Design Technology / Electronics


Engineering ) Examination

DIGITAL LOGIC DESIGN

Time : 3 Hours ] [ Max. Marks : 60

Instructions to Candidates :—
(1) All questions carry marks as indicated against them.
(2) Assume suitable data wherever necessary.

1. (a) Do the conversions and complete the following table.


Decimal Binary Hexadecimal Octal
23.8 ? ? ?
? 1111.0011 ? ?
? ? C.82 ?
? ? ? 3.07
6 (CO 1)
(b) Express ( – 45 ) in 8 bit 2's complement form. 2 (CO 1)

(c) Represent (26)10 into its Gray equivalent. 2 (CO 1)

2. (a) Perform ( – 75 )10 + (26)10 using 8 bit 1's complement method. 3 (CO 1)
(b) Explain following terms :—
(a) Fan In and Fan out
(b) Power dissipation. 3 (CO 4)

(c) Explain operation of TOTEM pole NAND Gate. 4 (CO 4)

CXDW/RW - 18 / 5029 Contd.


3. (a) Reduce following expression using K – Map :—
(i) f ( A , B , C , D , E ) = t m ( 0 , 5 , 6 , 8 , 9 , 10 , 11 , 16 , 20 , 42 , 25 ,
26 , 27 )
(ii) f ( A , B , C , D ) = Π M ( 3 , 6 , 8 ,11 , 13 , 14 ) . d ( 1 , 5 , 7 , 10 )
6 (CO 2)

(b) Implement Octal to Binary Encoder using Logic gates. 2 (CO 3)


OR

Enlist applications of multiplexer and De – multiplexer. 2 (CO 3)


(c) Simplify following Boolean expression.
—
f = (B + BC) (B + BC) (B + D) 2 (CO 2)

4. (a) Design Odd bit Parity Generator for 4 bit input. 5 (CO 2 , 3)
(b) Implement 4 bit Adder – Subtractor circuit and explain its operation.
5 (CO 2 , 3)

5. (a) Differentiate Latch and flip flop. 2 (CO 3)


(b) Convert JK Flip flop into SR flip Flop. 4 (CO 2 , 3)
(c) Illustrate 4 bit Bidirectional shift register with suitable diagram.
OR

Illustrate the operation of 4 bit Ring Counter using D flip flop.


4 (CO 3)

6. (a) Design MOD – 9 synchronous counter using T flip flop. 6 (CO 2 , 3)


(b) What is FSM ? Differentiate Mealy and Moore FSM. 4 (CO 3)

CXDW/RW - 18 / 5029 2 305

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