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VLSI, SP Interview Questions

These are VLSI interview questions Pdf and Machine Learning Project files.

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itsontopayush
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© © All Rights Reserved
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Download as PDF, TXT or read online on Scribd
17 views

VLSI, SP Interview Questions

These are VLSI interview questions Pdf and Machine Learning Project files.

Uploaded by

itsontopayush
Copyright
© © All Rights Reserved
Available Formats
Download as PDF, TXT or read online on Scribd
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Technical Interview

AMD Role: VLSI

Tell me about yourself


1. Draw frequency domain plot of sine 100Mhz and 400MHz signal
2. Why frequency domain of sin wave and cos wave are different. explain this difference in their freq domain representation
3. What is Intersymbol Interference{ISI}
4. Methods to avoid Intersymbol Interference. Explain with practical example
5. Write verilog code for D-flip flop with Synchronous and asynchronous reset
6. Difference between blocking and non blocking statements.
7. Draw and show what circuit will be synthesised (using D flip flop), when Verilog code for following two snippets are synthesised . 1} a=b; b = c; 2} a<=b; b<=c
8. Interviewer drawn 3 different waveforms and asked to design a digital circuit which can take 1st and 2nd waveform as input and produce 3rd waveform as output
9. Draw circuit for rising edge and falling edge dectector
10.Say atleast 2 different ways in which clock signal can be generated in testbench. Write verilog code for it and show.
11. Write a Verilog code to generate clock signal, where the clock frequency should reduce 10% every 10 seconds.
12. Do you know any one scripting Language? (TCL or Shell or Perl)

ARM Embedded Technologies

c programming, 2 algorithm to code were asked in round 1


Digital design, Computer architecture, verilog, puzzles were asked in round 2

Intel
1. First they asked me about my project which was vending machine??
2. They gave some states ie 1rs denimation,2Rs denomination and an undefined state he asked me to modify your state diagram??
3.They asked to draw AND functionality using 2*1 Mux??
4. They asked me about universal Gates??
5. They asked draw not gate using exor gate??
6.Write the truth table of exor Gate??
7. Difference between latch vs flip flop??
8. Difference between combinational vs sequential??
9. What is D in d flip flop??
10.What is STA??
11.What is setup and hold time violation??
12.Write down any timing constraint equation in STA??
3) Draw full adder.
Given one sequence and asked to draw the state diagram to detect that sequence, taking two bits at a time.
Design inverter using MUX.
What is synchronous reset and asynchronous reset.
Write the code of synchronous reset and asynchronous reset.

Siemens EDA Role: Developing Verilog Compiler and Digital circuit optimizer (backend of Tools like Mentor graphics, Cadence)

Skills required: Knowledge in Digital Design, Verilog, C, C++, Data structures, Shell or TCL scripting
1. Intro talks about role and team for which they are hiring
2. Tell me about yourself
3. Do you know about shell or TCL scripting
4. Write Verilog code for D flip flop with Asynchrononous reset
5. Take a simple D flip flop without any Reset pin in it. Now using external gates design circuit to make it a asynchronous reset D flip flop.
6. You know about Graphs?
7. Consider an array of length N with random integers. From the array return the first number which dont have its addition complement of 6 in the entire array.
Note: For 4, its addition complement of 6 is 2 (4 + 2 = 6)
For 7, its addition complement of 6 is -1 (7 + (-1) = 6)
Provide an optimized solution for the above question. Solution with O(N^2) compexity not required
Note: O(N^2) solution - Solution using nested for loops
8. Consider cost of a 15 bit adder is Rs.100 and cost of a 2:1 MUX is Rs.1
Can you construct a 15bit adder only using mux, without any external gates in a cheaper price? If so how much cost you can reduce?

Texas Instruments 1] Was asled about the work done in internship. Later was asked to implement in python.
2] Circuit was shown and asking what is the functionality of the circuit. It was a BCD counter.
3] 8x1 mux was asked to implement using minimum number of 2x1 mux.
4] Setup and hold time was asked. A circuit was given and asked to explain setup and hold timing.
5] I was asked to draw cmos invertor and asked to explain all possible cases.
6] A load capacitance was added and asked its effect. Now the capacitance is increased 10 times and asked its effect.
7] RC circuit was given and asked to show the variation of C and 10C.
what are universal gates
Design a calculator which can perform addition, subtraction, multipliction and division using logic gates
Written Test

ARM - Embedded Engineer digital electronics,70


computer
marks architecture,
70 minutes
C,c++ , 8085 micro processor and a
aptitude 30 marks 30 minutes

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