BCD to Binary Converter

ECE 2700 Final Project

Colston El-Hayek, Kyle Al-Attar, Robert Kayfish, Andrew Picklo

Electrical and Computer Engineering Department
School of Engineering and Computer Science
Oakland University, Rochester, MI
e-mails: [email protected], [email protected],
[email protected], [email protected]

Abstract- The purpose of the project is to design and II. M​ETHODOLOGY

implement a 12 bit Binary Coded Decimal (BCD) to
A. Top Level Design
binary converter on an FPGA board through use of a
keyboard input as well as 7-segment displays and LED
outputs. The 12 typed bits are stored through the use of For this design, a PS/2 keyboard is connected to an
D-Flip Flops, which are controlled by a Finite State FPGA board via a USB port; the user then types in a 12
Machine (FSM). The 12 BCD bits are then converted digit Binary Coded Decimal. The circuit then stores all 12
into a 10 bit unsigned output using an algorithm. The bits using a FSM. At this point, the circuit implements an
project was completed well within the group’s initial algorithm that uses adders and multipliers to convert the
expectations and tested with a high degree of success. BCD to its decimal and binary equivalents, with the Binary
The project could be improved by using a multiplexer to
make the full output displayed all at once, rather than equivalent shown on 10 LEDs and the decimal equivalent
changing every time a 1 or 0 is pressed on the keyboard. shown on three 7 segment displays. The top level block
diagram is shown in Figure 1.
I. I​NTRODUCTION
This report covers the design and implementation of a
BCD to binary converter. The 12 bit BCD is typed into a
PS/2 keyboard, and a field-programmable gate array
(FPGA) board shows its binary and decimal equivalents.
The next sections of the report give an overview of the top
level design, a detailed description of the individual circuit
components, as well as a summary of the results obtained
from experimental trials.

The motivation behind this project was for the group to

demonstrate their knowledge of digital circuits, as well as
Very High Speed Integrated Circuit Hardware Description
Language (VHDL) coding. All knowledge necessary to
carry out this project was taught in class. The project was
designed using components such as FSM, encoders, adders,
Flip Flops, and counters. Additionally, the design is Figure 1: Top Level Block Diagram
implemented in VHDL using a myriad of commands such as
generic and port map statements.

BCD is commonly used in computer memory through

address numbers [1]. In Addition, BCD is becoming
increasingly useful in embedded microprocessors and are
still used in real-time clock chips [1]. This project allows for
the conversion of any 12 digit BCD to its binary equivalent.
B. Keyboard Reader each bit of the output signals being connected to the “D”
and “E” signals, respectively, of 12 separate D-Flip Flops. A
The keyboard reader portion of the project consists
Block Diagram of the FSM is shown in Figure 3.
of an already made file taken from the class notes, the
main FSM for the entire project, the binary encoder, and
12 D-Flip Flops, as shown in Figure 2, in Appendix A.
The file, called my_ps2keyboard, consists of the two
main components: ps2read and ps2keyboard. When a
key is pushed on the keyboard, the ps2read component
reads the hexadecimal scan code associated with the
pressed key and outputs a 10-bit binary number in the
form of TTL communication[2]. This 10-bit output then
has its two most significant bits (MSB) dropped. This is
because those two bits are the stop bit and the parity bit,
which are not needed for the purposes of this project [6].
The resulting 8-bit hexadecimal number is then fed into Figure 3: Main FSM Block Diagram
a D-Flip Flop and a FSM. The enable to the D-Flip Flop
is controlled by the FSM and also feeds into a counter The FSM contains 12 states, with one state for each
that outputs a 1-bit “done” signal once the count is typed number[4]. To start off, the “resetn” input is set to 0,
reached. and the FSM remains in State 1. Once the “done” input is
high, the FSM moves to State 2. When this happens, the
Once the 8-bit number is put through the D-Flip Binary Encoded Input is outputted from the FSM, and it
Flop, it then feeds into a binary encoder that outputs a becomes the “D” input to the most significant flip flop, and
1-bit input into the main FSM along with the 1-bit only the MSB of the FSMs “E” output is high. This way,
“done” signal from the previously mentioned counter. each typed value can be stored into its appropriate flip flop,
The FSM then controls which of the 12 D-Flip Flops and the entire 12 bit typed input can be saved. For example,
will be storing which digits. These D-Flip Flops store all if the FSM is at State 2 and it receives a “done” signal, the
of the 12 typed inputs. 2nd MSB of “D” is set to the Binary Encoded input. In
addition, the 2nd MSB of “E” is set to ‘1’ and the rest of the
C. Binary Encoder bits of E are set to ‘0’. As a result, the value of the second
bit typed into the keyboard will be stored only into the
When the user types the number ‘1’ into the second flip flop, as the rest of the flip flops are not enabled.
keyboard, the 8 bit scan code 0x16 is outputted from the This cycle repeats until all 12 states have been completed,
keyboard receiver block. Similarly, when the user types meaning that all 12 typed numbers have been input into the
in ‘0’ into the keyboard, the scan code 0x45​ ​is outputted keyboard. At that point, the FSM moves to State 1 and the
from the keyboard receiver block [4]. The binary process repeats. An Algorithmic State Machine (ASM) chart
encoder is responsible for converting these scan codes of the FSM is shown in Figure 4 in Appendix B.
into the digit that was typed into the keyboard (either 0
or 1). That way, the circuit can store the actual typed
digits, rather than their hexadecimal scan codes, into the
D-Flip Flops.
E. 7 Segment Displays
D. Main FSM
The seven segment display portion of the project
If the user types in more than one digit into the uses 3 different components: a counter, a FSM, and a
keyboard, the previous scan code is overridden and replaced hex-to-7 segment converter. This portion of the project
with the scan code of the newly typed digit. As a result, 12 consists of code from a provided example. Its XDC file,
D-Flips Flops are required to store all the 12 typed digits counter, and number of active displays were modified to fit
into memory. In order to control the storing of all the typed the project’s desired specifications. Its FSM has an input of
digits, a FSM was used. In addition to receiving a clock and 3 nibbles, which are taken from the 12 bit output of the
“resetn” signal, the FSM receives a one bit signal from the D-Flip Flops from the keyboard receiver block, along with
binary encoder, which represents the digit typed into the an input from the counter. The input from the counter
keyboard. The FSM also receives a one bit “done” signal controls both the “AN” and “segs” signal. The AN signal is
from the keyboard receiver block, which indicates that the responsible for controlling which seven segment displays
scan code output of the keyboard receiver block is valid. are turned on. The “segs” signal maps to the hex-to-7
The FSM outputs 12 bit signals named “D” and “E”, with segment converter, which then maps directly to the currently
active 7-segment display in order to show the correct
nibble[4]. The FSM changes both the “AN” signal and
“segs” signal during the same clock tick so that the
7-segment displays show their corresponding numbers. A
block diagram of the 7-segment display is shown in Figure
5.

Figure 6: BCD Converter Block Diagram

III. E​XPERIMENTAL​S​ETUP
Figure 5: Seven-Seg Display Block Diagram To verify the functionality of the project, a testbench
was written in VHDL, through Vivado, in order to simulate
F. BCD to Decimal Conversion Algorithm the converter’s behavior. Additionally, an external interface
test was performed on an FPGA board in order to test the
The BCD to Decimal converter uses a pair of multiplier project.
blocks and a pair of 10 bit adders. The block takes a 12 bit
BCD input, which is divided into three 4 bit nibbles named For the behavioral simulation, the keyboard reading
“nib0-2”. “Nib0” gets six 0's concatenated to it to become a block was removed, and a pair of simulated keyboard inputs
10 bit "nib0a" signal. “Nib1” gets multiplied by ten, then were provided to the BCD converter and 7-segment blocks.
gets two 0's concatenated to it to become a 10 bit "nib1b" The BCD converter was expected to correctly convert the 12
signal. “Nib2” receives three 0's concatenated to it, then is bit BCD input to a 10 bit binary signal , and the 7-segment
multiplied by 100, producing a 14 bit "nib2b" signal. displays were expected to correctly display the decimal
Because “nib2” can take on values from 0-9, the largest equivalent
value “nib2b” can take is 900, which requires 10 bits in
Binary. Thus, the leading four digits are always '0' and can For the external interface test, the project code was
be removed to create a 10 bit "nib2c" signal. The “nib1a” programmed onto a Basys 3 FPGA board, and a PS/2
and “nib2b” signals are then fed into a 10 bit adder, with the keyboard was connected to the board via a USB port. A set
output and “c” signals feeding into a second 10 bit adder, of five sample 12 bit BCD test inputs were used to test the
along with the “nib2c” signal. The result of this calculation functionality of the board. The five inputs were randomly
is a 10 bit unsigned binary output [3][4]. A block diagram of selected to determine how the code would perform given a
the BCD converter is shown below in Figure 6. variety of inputs. Each test input was then typed into the
PS/2 keyboard (MSB to LSB) for the circuit to interpret and
convert. The FPGA was expected to show the correct binary
equivalent on the LEDs and the correct decimal equivalent
on the 7-segment display.
IV. R​ESULTS
The results from the external interface test were well
within expectations and are viewable in the linked video
provided in Appendix A. For each of the five external
interface trials, the decimal outputs on the seven segment
displays matched the hand-calculated values that were
computed using the skills learned in class. Similarly, the
binary outputs matched the hand-calculated values that were
computed using the skills learned in class. One unexpected
result that occurred while checking the LED results was that
one of the hand-calculated binary values was incorrect; the the signals from a PS/2 keyboard. This project also showed
project was used to correct said value. The only time the that a serializer is necessary to correctly display multiple
LED binary values deviated from normal values was when digits at a time on a seven segment display on the Basys 3
an invalid BCD was input into the keyboard, since the board. One issue that remains to be solved would be coding
maximum value of a 4 bit BCD cannot exceed 1001. The a testbench file that includes the keyboard reader block.
BCD to binary conversion code was not designed to Simulating the testbench with the keyboard reader block
correctly handle these types of inputs, so it output proved to be difficult, so it was more efficient to test the
meaningless data to the FPGA’s LEDs. By using knowledge keyboard reader block using an external interface rather
gained from class, the group ensured that both tests did not than a coded testbench.
contain any invaild BCD values.
The project could be improved by changing the design to
The second set of results were obtained from a test display the final converted output of the circuit all at once,
bench file run in Vivado. For these test results, the keyboard rather than sequentially as each individual bit of the BCD
reader block was removed, so that a 12 digit BCD could be input is typed. A multiplexer could have been used to
directly input into the BCD to binary converter. The results accomplish this, with a signal from the main FSM
from this test are shown in Appendix B in Figure 7.The controlling the selector signal.
results from this test were also as expected. For each 12 bit
BCD input, the correct 10 bit binary output was observed. Despite these potential improvements, the project was
These results prove the statement made in class that BCD is still completed with a high degree of success and the
a less efficient way to store data, since a 12 bit BCD value knowledge gained through this project can be applied
can be represented with only 10 bits when converted to towards the group member’s continued learning experience.
binary. While setting up the test, the group determined that
it was beneficial to avoid meaningless data, so only valid R​EFERENCES
BCD numbers were used as inputs. As a result, all binary
value outputs had an explainable reason as to how they were [1] What is BCD and How is it Used in Automation?
calculated in the code. (2020, March 23). Retrieved December 12, 2020, from
https://realpars.com/bcd
C​ONCLUSIONS
[2] Skill Level: Beginner, & Jimblom | November 23, 2.
This project was able to successfully convert a 12 bit (n.d.). Retrieved December 12, 2020, from
BCD input from a PS/2 keyboard to a displayed binary https://www.sparkfun.com/tutorials/215
output on a set of LEDs, as well as a decimal output on the
seven segment displays of a Basys 3 FPGA board. [3] Lecture Notes - Unit 4
[4] Lecture Notes - Unit 5
Through the knowledge gained in class, it was [5] Lecture Notes - Unit 6
determined that a binary encoder, an FSM, and a set of [6] Lecture Notes - Unit 7
D-Flip Flops were necessary to correctly read and interpret
 A​PPENDIX​A

(​https://drive.google.com/file/d/1vA4av1TpVnwTqaM3dTbfXN0yEs8A_fMb/view?usp=sharing​)

A​PPENDIX​B

Figure 2: Keyboard Reader Block Diagram

Figure 7: Keyboard Reader Block Diagram

 A​PPENDIX​B (​CONT​.)

Figure 4: ASM Chart of Main FSM