Direct Memory Access (DMA) Controller in Computer Architecture
Direct Memory Access (DMA) Controller in Computer Architecture
Computer Architecture
Last Updated : 18 Jul, 2023
DMA Controller is a hardware device that allows I/O devices to directly access memory with
less participation of the processor. DMA controller needs the same old circuits of an interface
to communicate with the CPU and Input/Output devices.
Single-Ended DMA
Dual-Ended DMA
Arbitrated-Ended DMA
Interleaved DMA
Single-Ended DMA: Single-Ended DMA Controllers operate by reading and writing from a
single memory address. They are the simplest DMA.
Dual-Ended DMA: Dual-Ended DMA controllers can read and write from two memory
addresses. Dual-ended DMA is more advanced than single-ended DMA.
Interleaved DMA: Interleaved DMA are those DMA that read from one memory address
and write from another memory address.
Address register – It contains the address to specify the desired location in memory.
Word count register – It contains the number of words to be transferred.
Control register – It specifies the transfer mode.
Note: All registers in the DMA appear to the CPU as I/O interface registers. Therefore, the
CPU can both read and write into the DMA registers under program control via the data bus.
The figure below shows the block diagram of the DMA controller. The unit communicates
with the CPU through the data bus and control lines. Through the use of the address bus and
allowing the DMA and RS register to select inputs, the register within the DMA is chosen by
the CPU. RD and WR are two-way inputs. When BG (bus grant) input is 0, the CPU can
communicate with DMA registers. When BG (bus grant) input is 1, the CPU has relinquished
the buses and DMA can communicate directly with the memory.
Working Diagram of DMA Controller
Explanation: The CPU initializes the DMA by sending the given information through the
data bus.
The starting address of the memory block where the data is available (to read) or
where data are to be stored (to write).
It also sends word count which is the number of words in the memory block to be
read or written.
Control to define the mode of transfer such as read or write.
A control to begin the DMA transfer
Burst Mode: In Burst Mode, buses are handed over to the CPU by the DMA if the
whole data is completely transferred, not before that.
Cycle Stealing Mode: In Cycle Stealing Mode, buses are handed over to the CPU by
the DMA after the transfer of each byte. Continuous request for bus control is
generated by this Data Transfer Mode. It works more easily for higher-priority tasks.
Transparent Mode: Transparent Mode in DMA does not require any bus in the
transfer of the data as it works when the CPU is executing the transaction.