Digital Electronics

(ELC2130)

Prof. M. Shah Alam

Department of Electronics Engineering
AMU Aligarh
E-mail: [email protected]

Starting: 7th January 2019

..About your
teacher
2002: Doctorate Degree (Ph.D)
(Electronics Engineering)

2010: Post Doctorate (Nano-electronics)

Under Commonwealth Fellowship, UK

For More details:

http://www.amu.ac.in/dshowfacultydata2.jsp?
did=32&eid=3208

1988: Bachelor of Engineering

(Electronics & Communication Engineering)

1991: Master of Engineering (Electronics

& Communication Engineering)
2
Course
Structure
 Course deals with…

Digital + Electronics
System

◆ Digital Systems: Fascinated human

being due to their widespread use;
◆ Electronics: Cover related electronics
and their design issues.
Evolving Perceptions!

Digital is better than

anolog !

Craze for digital solution!

5
 Possible
reasons..
 Ex:
Internet Access Entertainment

Health Care e.g. a wireless sensor implanted

under your skin detects a fluids buildup in your lungs and
alert your doctor…Who decide about the right kind of
medication

…And many more

These services are further improved with launch of

new mobile technology e.g. 3G, 4G 5G etc.
 Initiative !
⧫ Part of B. Tech/M. Tech (Electronics)
curriculum in major Indian universities/IITs;
⧫ This course is introduced in B.Tech with sole
purpose:

What are the recent advancements in digital

technology
To learn about digital circuits electronics and what
are specialized skills required in design such
circuits
“Digital Electronics" course is an attempt in this
direction. More specifically ….
 Objectives!
What are ADCs/DACs? Specialized
circuits required to carry out required
conversion ---Unit-IV

Objective 5
What’s role memory play in digital
system ---an inside story ---Unit-III

Objective 4
Why MOSFET is a popular choice for
digital circuits ---Unit-II

Objective 3
Possible options available to
realize digital circuits--Unit-I

Objective 2
Fundamental
Concepts
Objective 1
 Evaluation !
Course
Work, 15%

Students take
interest and give
due attention to
Mid
Semester
what is being
Exam, 25%
Final
Semester
Taught in the class
Exam, 60%
Keep their
notes updated..

Course work:
o Quiz , Home work etc.
 Books
◼ Ronald J. Tocci, Neal Widmer, Greg Moss, Digital
Systems: Principles and Applications, 10th ed.
Pearson Education, N. Delhi, 2009
◼ A.S. Sedra and K.C. Smith, Microelectronic
Circuits, Oxford University Press, 5th Edition,
2004.
◼ J. Millman and Grabel, Microelectronics, McGaw
Hill, 1987.
Digital IC Terminology
⚫ Logic Circuits and Systems not only
to be understood by their logical
behavior only.
⚫ There other consideration such as:
− Voltage/Current Level
− Noise Margin
− Fan-Out/In
− Power Consumption
− Propagation Delay
− Current Sourcing/Sinking
12
8-1 Digital IC Terminology

Voltage/Current Levels
8-1 Digital IC Terminology

Ex.
 Noise Margin
• Noise immunity refers to the circuit’s ability to
tolerate noise without changes in output voltage.
– A quantitative measure is called noise margin.

VNH = VOH - VIH VNL = VIL - VOL

 Fan Out
• A logic circuit output is specified to drive a
certain fixed number of logic inputs.
• The fan-out (also called loading factor) is
defined as the maximum number of
standard logic inputs that an output can
drive reliably.
• For example, a logic gate specified to have
a fan-out of 10 can drive 10 standard logic
inputs. If this number is exceeded, the
output logic level voltages cannot be
guaranteed.
 Ex.
+5V
IOH IIH
0
0
VOH
IIH

• Gate 1 output acts as a current source

supplying a total current IOH that is the sum of
the IIH currents of each TTL input.
• If too many loads are being driven, IOH will
increase thereby bringing VOH below VOH(min).
This will in turn could cause VOH to go into the
indeterminate range.
 Cont…
• Fan-out refers to the load drive capability of an
IC output
– A TTL output has a limit on how much current it can
sink in the LOW state, or source in the HIGH state.
– Exceeding these currents will result in output voltage
levels outside specified ranges.
• Determining fan out
– Add the IIH for all inputs connected to an output.
• Sum must be less than the output IOH specification.
– Add the IIL for all inputs connected to an output.
• Sum must be less than the output IOL specification.
 Propagation Delay
• A logic signal always experiences a delay going
through a circuit.
– The two propagation delay times are defined as:
 Fan-In
⚫ Fan-in is the number of inputs to a logic gate.
⚫ It is limited by
− Silicon area
− Input capacitance
⚫ Thus, when designing a logic circuit, we must
consider the practical limit on the fan-in of
the logic gates.
− Cannot assume that an n-input logic gate is
available
⚫ where n is large.
 Power Requirements
• Every IC requires a certain amount of electrical
power to operate.
– Supplied by one or more power-supply voltages
– Current drawn from the supply varies depending
on logic states of the circuits.
 Current Sourcing

• Current-sourcing action.
– When the output of gate 1 is HIGH, it supplies
current IIH to the input of gate 2.
• Which acts essentially as a resistance to ground.
– The output of gate 1 is acting as a source of
current for the gate 2 input.
 Current Sinking

• Current-sinking action.
– When gate 1 output goes LOW, current will flow from
the input circuit of gate 2 back through the output
resistance of gate 1, to ground.
• Circuit output that drives the input of gate 2 must be
able to sink a current, IIL , coming from that input.
 Background
• Early families (DL, • Gate/transistor ratio is
RTL) roughly 1/10
• TTL • Integration Level
– NAND & AOI – SSI < 12 gates/chip
• Evolution of TTL family – MSI < 100 gates/chip
– Schottky TTL – LSI ..1K gates/chip
– Open collector & Tri- – VLSI ..10K gates/chip
state TTL
– ULSI ..100K gates/chip
• ECL Family
– GSI ..1Meg gates/chip
– OR/NOR Gate 24
 The TTL Logic Family
• The basic gate realized in this family is a NAND
gate
– Utilizes Multiple-Emitter Transistor
• The input will be applied at the emitter of
transistor
– A HIGH input turn off the B-E junction.
• Only a leakage current flow.
– A LOW input turns on the junction.
• Relatively large current flow.
• TTL circuits generally utilizes Totem-pole Output
configuration to reduce power dissipation.
 The TTL NAND Circuit

Diode Equivalent for Q1

The TTL Gates Analysis
Inputs are High
One of the Input Low
 PULL Down Transistor
• A TTL output acts as a current sink in the LOW
state because it receives current from the input of
the gate that it is driving.
Q4 is performing a current-
sinking action—deriving its
current from the input
current (IIL) of the load gate.

Q4 is often called the current-

sinking transistor or pull-
down transistor because
it brings the output voltage
down to its LOW state.
 PULL Up Transistor
• A TTL output acts as a current source in the HIGH
state—because it supplies current from the output
of the gate that it is driving.

Transistor Q3 is supplying the

input current (IIH) required
by Q1 of the load gate.

Q3 is often called the current-

sourcing or pull-up transistor.
 TTL Evolution
Schottky TTL
• A major slowdown factor in BJTs is due to transistors
going in/out of saturation
• Shottky diode has a lower cut in/forward bias
(0.25V)
• When b-c junction become forward biased, the
Schottky diode bypasses the current, thus preventing
the transistor from going into deep in saturation

31
 The TTL ICs
• The first TTL ICs was the 54/74 series from Texas
Instruments—Introduced in 1964.
• Manufacturers use the same numbering system.
– Prefix indicates manufacturer.
• SN – Texas Instruments.
• DM – National Semiconductor.
• S – Signetics.
• Data sheets contain electrical characteristics,
switching characteristics, and OTHER operating
conditions.
 TTL Family Evolution

Legacy: NOT in Use Widely used Today

33
8-4 TTL Series Characteristics
Comparison of TTL Series Characteristics.
8-11 Open Collector/Open Drain Outputs

TTL Totem -Pole Outputs

should never be connected to the same point.
 Ex.

I=(5-1.1)/130
=31.5mA

Totem-Pole Outputs should never be tied together

8-11 Open Collector/Open Drain Outputs
Solution!

OPEN Collector TTL

 Circuit Configuration
8-11 Open Collector/Open Drain Outputs

CMOS outputs modified this way

are called OPEN DRAIN outputs
8-11 Open Collector/Open Drain Outputs
Wired-AND Operation
Using Open-Collector Gates.
 Applications
• A common use of open-collector/drain outputs is as
a Buffer/Driver.
– Logic circuit designed to have a greater output current
and/or voltage capability than an ordinary logic circuit.
• They allow a weaker output circuit to drive a heavy load.

An open-collector buffer/driver drives a high-current, high-voltage load.

 8-11 Open Collector/Open Drain Outputs

IEEE Symbol uses a distinctive

notation to identify open-collector/drain outputs.

Standard IEEE designation

for an Open-Collector/Drain output
is an underlined diamond.
 Tristate TTL
• Tristate circuit arrangement takes advantage of the
high-speed operation of the Pull-up/ Pull-down
output.
– While allowing outputs to be connected together to share a
common wire.

• Called tristate because it allows three possible

output states.
– HIGH, LOW, and High-Impedance (Hi-Z).

• Hi-Z is a condition in which both Pull-up & Pull-

down transistors are turned OFF.
– The output terminal is a high impedance to both SUPPLY
VOLTAGE and GROUND.
Circuit Configuration

X =High/Low ; OE=1

=High-Impedance
(Hi-Z) ; OE=0
A
N
A
L
Y
S
l
S
 Fn. Diagram
• Devices with tristate outputs have an enable input.
– Often labeled E for enable or OE for output enable

• When OE = 1, the circuit operates as a normal

INVERTER because the HIGH logic level at OE
enables the output.
– Output will be either HIGH or LOW, depending
on the input level.
 Cont..
• Outputs of tristate ICs can be connected
together without sacrificing the performance
– When tristate outputs are connected together,
only one of them should be enabled at one time.
• Two active outputs could fight for control of the
common wire.
• Many ICs are designed with tristate outputs.
– 74LS374 is an octal D-type FF register IC with
Tristate Outputs.
 Tristate Buffer
• A tristate buffer is a circuit used to control the
passage of a logic signal from input to output
– Some tristate buffers invert the signal as passes.
8-12 Tristate (Three-State) Logic Outputs

IEEE Symbol

A triangle pointing downward

 Common Bus
Applications!
1
a
0

1 b
How to
0 ??
avoid
‘Regular TTL or CMOS’ Bus
• There is Bus Contention issues when two
Contention?
outputs try to drive the bus to different
states.
• Value on the bus may be indeterminate;
• Damage possible (Sinking Large Current b!!)
• On a PC data bus, can cause PC to crash
Solution!
 The ECL Logic
• The Emitter-Coupled Logic (ECL) family
operates on the principle of current
switching whereby…..
– A fixed bias current less than IC (sat) is switched
from one transistor’s collector to another.
– The ECL family is fastest of all logic families.
– Also, referred to as current-steering logic.
However, ECL logic circuits consume more power.
8-14 The ECL Digital IC Family
The ECL Current Switching
(Differential Amplifier)
 The basic ECL Gate
8-14 The ECL Digital IC Family

This circuit produces

complementary outputs: VOUT1 ,
equal to VIN , and VOUT2 , equal
to VIN.

The basic ECL circuit is used as an INVERTER if the output is taken at VOUT1.
 Features of ECL
8-14 The ECL Digital IC Family
8

• Very fast switching with typical propagation

delay of 360 ps—faster than TTL or CMOS.
• The standard ECL logic levels are nominally
-0.8 V and 1.7 V for logical 1 and 0
respectively.
• Worst-case noise margins approximately 150
mV.
• ECL logic gates usually produce an output and
its complement, eliminating the need for
inverters.
• Current flow remains constant, eliminating
noise spikes
Concluding Remarks!
Explained the Importance of this
course.

Various Logic Families have been

discussed.

A detail perspectives including circuit

aspects of these logic families were
covered.