22EC301-Microcontrollers

3rd Year 1st Semester ECE

Dr. V. Vijayaraghavan, M.E., Ph.D.,
Associate Professor-ECE,
Associate Dean - AAA,
VFSTR (Deemed to be University)
 Module-2 : Unit - 2
LPC 2148 Peripherals-2

UART 8L+8T+8P=24Hrs

USB

I2C Bus Controller

Vector Interrupt Controller

Dr. V.Vijayaraghavan, Associate Professor-ECE, VFSTR, Guntur

 UART (Universal Asynchronous Receiver/Transmitter)
UARTs:
 The LPC2148 contain two UARTs. In addition to standard transmit and receive data
lines, the LPC2148 UART1 also provides a full modem control handshake interface.
 Compared to previous LPC2000 microcontrollers, UARTs in LPC2148 introduce a
fractional baud rate generator for both UARTs, enabling these microcontrollers to
achieve standard baud rates such as 115200 with any crystal frequency above 2 MHz.
 In addition, auto-CTS/RTS flow-control functions are fully implemented in hardware.
Features:
 16 Byte Receive and Transmit FIFOs.
 Receiver FIFO trigger points at 1 B, 4 B, 8 B, and 14 B
 Built-in fractional baud rate generator covering wide range of baud rates without a need for
external crystals of particular values. (50 to 448000 baud)
 Mechanism that enables software and hardware flow control implementation.
o Transmission FIFO control enables implementation of software flow control (XON/XOFF) on
both UARTs.
o LPC2148 UART1 equipped with standard modem interface signals. This module also provides
full support for hardware flow control (auto-CTS/RTS).
Dr. V.Vijayaraghavan, Associate Professor-ECE, VFSTR, Guntur
UART0 and UART1 pin description
 RXD0 – Input - Serial Input, Serial receive data.
 TXD0 – Output - Serial Output, Serial transmit data.
 RXD1 – Input - Serial Input, Serial receive data.
 TXD1 – Output - Serial Output, Serial transmit data.
 DTR1 – Output - Data Terminal Ready, indicates that the UART1 is ready to
establish connection with external modem.
 DSR1 – Input - Data Set Ready, indicates if the external modem is ready to
establish a communications link with the UART1.
 RTS1 – Output - Request To Send, indicates that the UART1 would like to
transmit data to the external modem.
 CTS1 – Input - Clear To Send, indicates if the external modem is ready to
accept transmitted data via TXD1 from the UART1.
 RI1 – Input - Ring Indicator, indicates that a telephone ringing signal has been
detected by the modem.
 DCD1 – Input - Data Carrier Detect, indicates if the external modem has
established a communication link with the UART1 and data may be exchanged.
Dr. V.Vijayaraghavan, Associate Professor-ECE, VFSTR, Guntur
UART 0/1….. RBR, and THR Registers
UART0 Receiver Buffer Register – U0RBR

UART0 Transmit Holding Register – U0THR

UART0 Transmit Enable Register – U0TER

Dr. V.Vijayaraghavan, Associate Professor-ECE, VFSTR, Guntur

UART 0/1….. U0LCR - UART0 Line Control Register

Bit 1:0 - Word Length Select Bit 3 - Parity Enable

00 = 5-bit character length 0 = Disable parity generation and checking
01 = 6-bit character length 1 = Enable parity generation and checking
10 = 7-bit character length Bit 5:4 - Parity Select
11 = 8-bit character length 00 = Odd Parity
Bit 2 - Number of Stop Bits 01 = Even Parity
0 = 1 stop bit 10 = Forced “1” Stick Parity
1 = 2 stop bits 11 = Forced “0” Stick Parity
Bit 6 - Break Control Bit 7 - Divisor Latch Access Bit (DLAB)
0= Disable break transmission 0 = Disable access to Divisor Latches
1 = Enable break transmission 1 = Enable access to Divisor Latches

Dr. V.Vijayaraghavan, Associate Professor-ECE, VFSTR, Guntur

UART 0/1….. U0LSR - UART0 Line Status Register

Bit 0 - Receiver Data Ready Bit 5 - Transmitter Holding Register Empty

0 = U0RBR is empty 0 = U0THR has valid data
1 = U0RBR contains valid data 1 = U0THR empty
Bit 1 - Overrun Error Bit 6 - Transmitter Empty
0 = Overrun error status inactive 0 = U0THR and/or U0TSR contains valid data
1 = Overrun error status active 1 = U0THR and U0TSR empty
Bit 2 - Parity Error Bit 7 - Error in RX FIFO (RXFE)
0 = Parity error status inactive 0 = U0RBR contains no UART0 RX errors
1 = Parity error status active 1 = U0RBR contains at least one UART0 RX error
Bit 3 - Framing Error This bit is cleared when U0LSR is read.
0 = Framing error status inactive
1 = Framing error status active
Bit 4 - Break Interrupt
0 = Break interrupt status inactive
1 = Break interrupt status active
Dr. V.Vijayaraghavan, Associate Professor-ECE, VFSTR, Guntur
UART 0/1….. DLL, DLM and FDR Registers
UART0 Divisor Latch Registers – DLL & DLM

UART0 FDR Register

 It decides the clock pre-scalar for baud rate generation.

0 < MULVAL ≤ 15
0 ≤ DIVADDVAL ≤ 15

Dr. V.Vijayaraghavan, Associate Professor-ECE, VFSTR, Guntur

UART 0….. Block diagram

Dr. V.Vijayaraghavan, Associate Professor-ECE, VFSTR, Guntur

UART 1….. Block diagram

Dr. V.Vijayaraghavan, Associate Professor-ECE, VFSTR, Guntur

UART 0…..

Registers

Dr. V.Vijayaraghavan, Associate Professor-ECE, VFSTR, Guntur

UART 1…..

Registers

Dr. V.Vijayaraghavan, Associate Professor-ECE, VFSTR, Guntur

 UART… (Programming-1)

void UART0_init(void) #include <lpc214x.h>

{ #include <stdint.h>
PINSEL0 = PINSEL0 | 0x00000005; /* Enable UART0 Rx/Tx pins */ #include "UART.h"
U0LCR = 0x83; /* DLAB = 1, 1 stop, 8-bit character length */
int main(void)
U0DLM = 0x00; /* baud rate of 9600 with Pclk = 15MHz */
U0DLL = 0x61; /* 97 decimal*/
{
U0LCR = 0x03; /* DLAB = 0 */ char receive;
} UART0_init();
while(1)
unsigned char UART0_RxChar(void) /*receive a byte on UART0 */ {
{ receive = UART0_RxChar();
while( (U0LSR & 0x01) == 0); /*Wait till RDR becomes 1*/ UART0_SendString("Received:");
return U0RBR; UART0_TxChar(receive);
}
UART0_SendString("\r\n");
void UART0_TxChar(char ch) /*send a byte on UART0 */
}
{ }
U0THR = ch;
while( (U0LSR & 0x40) == 0 ); /* Wait till THRE bit = 1 */
}
Dr. V.Vijayaraghavan, Associate Professor-ECE, VFSTR, Guntur
 UART… (Programming-2)
#include <lpc214x.h>
void initClocks(void); void initUART0(void)
void initUART0(void); {
void U0Write(char data); PINSEL0 = 0x5;
void Send_String(char* StringPtr); U0LCR = 0x83;
char String[]="Hello from BINARYUPDATES.COM !!! \n\r\n"; U0DLL = 110;
unsigned int delay; U0DLM = 1;
int main(void) U0FDR = 0xF1;
{ U0LCR &= 0x0F;
initClocks(); // Set CCLK=60Mhz and PCLK=60Mhz }
initUART0();
while(1) void U0Write(char data)
{ {
Send_String(String); //Pass the string to the USART_putstring while (!(U0LSR & (1<<5)));
function and sends it over the serial U0THR = data;
for(delay=0; delay<500000; delay++); // delay }
}
}
Dr. V.Vijayaraghavan, Associate Professor-ECE, VFSTR, Guntur
UART… (Programming-2 continued)
void initClocks(void)
{
PLL0CON = 0x01; //Enable PLL
PLL0CFG = 0x24; //Multiplier and divider setup
PLL0FEED = 0xAA; //Feed sequence
PLL0FEED = 0x55;
while(!(PLL0STAT & 0x00000400)); //is locked?
PLL0CON = 0x03; //Connect PLL after PLL is locked
PLL0FEED = 0xAA; //Feed sequence
PLL0FEED = 0x55;
VPBDIV = 0x01; // PCLK is same as CCLK i.e.60 MHz
}

void Send_String(char* StringPtr)

{
while(*StringPtr != 0x00){
U0Write(*StringPtr);
StringPtr++;}
}
Dr. V.Vijayaraghavan, Associate Professor-ECE, VFSTR, Guntur
 UART… (Not required for Exam)
RS232C

Max-232 is a IC used
to make the voltage
compatible between
RS232 and TTL logic.

Dr. V.Vijayaraghavan, Associate Professor-ECE, VFSTR, Guntur

Vectored Interrupt Controller
(VIC)
 Interrupt Controller (VIC)
When interrupt occurs,
 VIC identifies the source of interrupts
 Passes requests on interrupt request pins as per the configuration
 If more than one interrupt occurs at a time VIC resolves priority
• 32 interrupt request inputs, LPC2148 uses 23 of 32 interrupts (22 sources).
• Categories
• Fast Interrupt Request (FIQ)
• Vectored Interrupt Request (IRQ)
• Non-vectored IRQ as defined by programmable settings.
 Interrupt Controller……
• Interrupts from the various peripherals dynamically prioritized
• High priority for Fast interrupt request (FIQ) – one at a time
• Fast, low latency interrupt handling

• What happens if more than one request to FIQ?

• The VIC combines the requests to produce the FIQ signal to the ARM processor.
• FIQ service routine will read a word from the VIC that identifies which FIQ source(s) is
(are) requesting an interrupt.

• Medium priority given for Vectored IRQs

• Total 16 registers available
• Slot 0 has high priority and slot 15 has low priority
• Priority can be changed by changing the slot for the interrupt
 Interrupt Controller……
• Non-vectored IRQs have the lowest priority.
• The VIC combines the requests from all the vectored and non-vectored IRQs to produce
the IRQ signal to the ARM processor.
• The IRQ service routine can start by reading a register from the VIC and jumping there.
• Priority based service address routine provision
• If no VIRQ is present default routine for common address is provided

Configuring an Interrupt
• Enable global interrupts
• Set the priority of the interrupt
• Enable the interrupts we want to use
• Programs can handle 1 FIQ, 16 VIRQ,
1 NVIRQ Interrupt sources
VIC…… Software Interrupt register (VICSoftInt)
 Read/Write register, 22 interrupt sources are there here.
Bit# 31 30 29 28 27 26 25 24
IRQ - - - - - - - -

Bit# 23 22 21 20 19 18 17 16
IRQ - USB AD1 BOD I2C1 AD0 EINT3 EINT2

Bit# 15 14 13 12 11 10 9 8
IRQ EINT1 EINT0 RTC PLL SPI1/SSP SPI0 I2C0 PWM

Bit# 7 6 5 4 3 2 1 0
IRQ UART1 UART0 TIMR1 TIMR0 ARMC1 ARMC0 - WDT
Dr. V.Vijayaraghavan, Associate Professor-ECE, VFSTR, Guntur
VIC…… Interrupt registers
Software Interrupt Clear register (VICSoftIntClear)

 Write only register, 22 interrupt sources are there here.

 Write 1 means, clear the interrupt. 0 Means unchanged.

Raw Interrupt status register (VICRawIntr)

 Read only register, 22 interrupt sources are there here.

 Reads out the state of 32 interrupt requests & software interrupts.

Interrupt Enable register (VICIntEnable)

 Read/Write register, 22 interrupt sources are there here.

 Controls the 32 interrupt requests and software interrupts.

Dr. V.Vijayaraghavan, Associate Professor-ECE, VFSTR, Guntur

 Interrupt Registers
1) VICIntSelect (R/W) :
• This register is used to select an interrupt as IRQ(0) or as FIQ(1)
2) VICIntEnable (R/W) :
• This is used to enable interrupts(1) (writing 0 does not effect)
3) VICIntEnClr (R/W) :
• This register is used to disable interrupts(1) (writing 0 does not effect)
4) VICIRQStatus (R) :
• This register is used for reading the current status of the enabled IRQ interrupts.
5) VICFIQStatus (R) :
• Same as VICIRQStatus except it applies for FIQ
6) VICSoftInt :
• This register is used to generate interrupts using software (write 1 to manually
enable interrupt)
7) VICSoftIntClear :
• This register is used to clear the interrupt request that was triggered(forced) using
VICSoftInt (Writing a 1 will release)
 Interrupt Registers
8) VICVectCntl0 to VICVectCntl15 (16 registers in all) :
• Registers to control the priority
• 3 parts
 {Bit0 to bit4} - Number of Interrupt
 {Bit 5} – Enable the vectored interrupt
 {and rest of the bits} – reserved
9) VICVectAddr0 to VICVectAddr15 (16 registers in all) :
• Address of the function for the interrupt/ ISR
10) VICVectAddr :
• Holds the address of the associated/active ISR
11) VICDefVectAddr :
• This register stores the address of the “default/common” ISR that must be
called when a Non-Vectored IRQ occurs.
VIC block diagram
 Interrupt Programming
To use interrupt in our example project. We’ll use Timer to show usage of interrupt in LPC2148 ARM7 Microcontroller. As we’ve
seen Timer in our previous post. I believe our brain is still warm with it. To keep simplicity in our example project we’ll blink LED
when interrupt is generated after every 0.5 Sec.
#include <lpc214x.h> void initTimer0(void)
void initClocks(void); {
T0CTCR = 0x0; //Set Timer Mode
void initTimer0(void);
T0PR = 60000-1; //Increment T0TC at every 60000 clock cycles
__irq void timer0ISR(void); T0MR0 = 500-1; //Zero Indexed Count-hence subtracting 1
int main(void) T0MCR = (1<<0) | (1<<1);//Set bit0 & 1 to Interrupt & Reset
VICVectAddr4 = (unsigned )timer0ISR; //Pointer Interrupt
{ VICVectCntl4 = (1<<5) | 4; //(bit 5 = 1)->to enable Vectored
initClocks(); // Initialize PLL to setup clocks IRQ slot //bit[4:0]) -> this the source number
initTimer0(); // Initialize Timer0 VICIntEnable = (1<<4); // Enable timer0 interrupt
T0TCR = (1<<1); // Reset Timer
IO0DIR = (1<<10); // Configure pin P0.10 as Output }
IO0PIN = (1<<10);
T0TCR = (1<<0); // Enable timer
while(1); // Infinite Idle Loop
}
Interrupt Programming…..
__irq void timer0ISR(void)
{
long int readVal;
readVal = T0IR; // Read current IR value
IO0PIN ^= (1<<10); // Toggle LED at Pin P0.10
T0IR = readVal; // Write back to IR to clear Interrupt Flag
VICVectAddr = 0x0; // End of interrupt execution
}

void initClocks(void)
{
PLL0CON = 0x01; //Enable PLL
PLL0CFG = 0x24; //Multiplier and divider setup
PLL0FEED = 0xAA; //Feed sequence
PLL0FEED = 0x55;
while(!(PLL0STAT & 0x00000400)); //is locked?
PLL0CON = 0x03; //Connect PLL after PLL is locked
PLL0FEED = 0xAA; //Feed sequence
PLL0FEED = 0x55;
VPBDIV = 0x01; //PCLK is same as CCLK i.e.60 MHz
}
 Interrupt Programming…..
#include <lpc214x.h>
#include <stdint.h>
char rx;
__irq void UART0_Interrupt(void);
void UART0_init(void)
{
PINSEL0 = PINSEL0 | 0x00000005;
U0LCR = 0x83;
U0DLM = 0x00; /* baud rate 9600,Pclk 15MHz */
U0DLL = 0x61;
U0LCR = 0x03; /* DLAB = 0 */
U0IER = 0x00000003;/* Enable THRE and RBR interrupt */
}
__irq void UART0_Interrupt(void)
{ int main(void)
int iir_value; {
iir_value = U0IIR; UART0_init();
while ( !(iir_value & 0x01) ); VICVectAddr0 = (unsigned) UART0_Interrupt;
if( iir_value & 0x00000004 ) VICVectCntl0 = 0x00000026; /* UART0 IRQ slot */
{ rx = U0RBR; } VICIntEnable = 0x00000040; /* UART0 interrupt */
U0THR = rx; VICIntSelect = 0x00000000; /* UART0 config as IRQ */
while( (U0LSR & 0x40) == 0 ); while(1);
VICVectAddr = 0x00; }
}
Universal Serial Bus
(USB)
USB (Universal Serial Bus) USB 2.0 device controller
 The USB is a 4-wire serial bus that supports communication between a host and a
number (127 max) of peripherals.
 The host controller allocates the USB bandwidth to attached devices through a
token based protocol.
 The bus supports hot plugging, unplugging, and dynamic configuration
of the devices. All transactions are initiated by the host controller.
 The LPC2148 is equipped with a USB device controller that enables
12 Mbit/s data exchange with a USB host controller.
 It consists of a register interface, serial interface engine, endpoint buffer memory
and DMA controller.
 The serial interface engine decodes the USB data stream and writes data to the
appropriate end point buffer memory. The status of a completed USB transfer or error
condition is indicated via status registers. An interrupt is also generated if enabled.
 A DMA controller can transfer data between an endpoint buffer and USB RAM.
USB…..
The host schedules transactions in 1 ms frames. Each frame
contains SoF marker and transactions that transfer data to/from
device endpoints. Each device can have a maximum of 16 logical or
32 physical endpoints.
There are 4 types of transfers defined
 The control transfers are used to configure the device.
 The interrupt transfers are used for periodic data transfer.
 The bulk transfers are used when rate of transfer is not critical.
 The isochronous transfers have guaranteed delivery time but no error
correction.
 Double buffer implementation for bulk and isochronous endpoints

USB Pins:
 D+, D-, VBUS, UP_LED, CONNECT
 These two functions (SoftConnect and GoodLink LED indicator) are sharing one pin.
USB….. Fixed Endpoint Configuration….
USB….. Fixed Endpoint Configuration….
USB….. USBTxData & USBRxData Registers
USB….. USBCtrl Register
USB….. USBCmdCode & USBCmdData Registers

This register is used for writing the commands. The commands written here will get
propagated to the Protocol Engine and will be executed there. After executing the command,
the register will be empty, and the “CCEMTY” bit of the Interrupt Status register is set high.

This is a read-only register which will carry the data retrieved after executing a command.
When this register is ready, the “CD_FULL” bit of the Device Interrupt Status register is set.
USB….. Registers List
USB….. Block diagram
USB…..
Data Flow:
 USB is a host controlled protocol, i.e., irrespective of whether the data
transfer is from the host to the device or device to the host, transfer
sequence is always initiated by the host.
 During data transfer from device to the host, the host sends an IN token
to the device, following which the device responds with the data.
It supports 32 physical (16 logical) endpoints.
 Data Flow from USB Host to the Device.
 Data Flow from Device to the Host.
 Slave Mode Transfer.
 DMA Mode Transfer.

Dr. V.Vijayaraghavan, Associate Professor-ECE, VFSTR, Guntur

Inter Integrated Circuit
( 2
IC )
 Features of I2C - Bus Serial I/O controller
 I2C (Inter Integrated Circuit) is serial bus interface connection protocol first invented
by Philips Semiconductor (NXP Semiconductors). It is also called as TWI (two wire
interface) since it uses only two wires for communication. I2C uses handshaking
mechanism for communication. Hence, it is also called as acknowledgment based
communication protocol.
Features:
 Standard I2C bus interfaces may be configured as Master, Slave, or Master/Slave.
 Arbitration is handled between simultaneously transmitting masters without
corruption of serial data on the bus.
 Programmable clock allows adjustment of I2C transfer rates.
 Data transfer is bidirectional between masters and slaves.
 Serial clock synchronization
• Allows devices with different bit rates to communicate via one serial bus.
• Used as handshake mechanism to suspend and resume serial transfer.
 I2C-bus can be used for test and diagnostic purposes

Dr. V.Vijayaraghavan, Associate Professor-ECE, VFSTR, Guntur

Features of I2C - bus serial I/O controller……

I2C-I2C bus configuration:

Dr. V.Vijayaraghavan, Associate Professor-ECE, VFSTR, Guntur

 Features of I2C - bus serial I/O controller……

• Two types of data transfers

 Master to slave
 Slave to master
• Master transmits serial clock, start and stops

I2C-pin Description
Pin Type Description

SDA0/1 Input/Output I2C Serial Data

SCL0/1 Input/Output I2C Serial Clock

Dr. V.Vijayaraghavan, Associate Professor-ECE, VFSTR, Guntur

Features of I2C - bus serial I/O controller…… I2CnCONSET Register

I2C0CONSET (I2C0 Configuration Set Register)

It is an 8-bit read-write register, used to control the operation of the I2C0 interface.
 AA (Assert Acknowledge Flag) - When set to 1, Acknowledge (SDA LOW) is returned
during acknowledge clock pulse on SCL. Otherwise, Not acknowledge (SDA HIGH) is returned.
 SI (I2C Interrupt Flag) - This bit is set when the I2C state changes. Else it remains reset.
 STO (Stop Flag) - In Master Mode, setting this bit causes the I2C interface to transmit a STOP
condition. In Slave Mode, setting this bit causes recover from an error condition if any. This bit is
cleared by hardware automatically.
 STA (Start Flag) - Setting this bit causes the I2C interface to enter in master mode and transmit
a START condition or transmit a repeated START condition if it is already in master mode.
 I2CEN (I2C Interface Enable) - Set this bit to enable I2C interface.
Dr. V.Vijayaraghavan, Associate Professor-ECE, VFSTR, Guntur
Features of I2C - bus serial I/O controller…… I2CnCONCLR Register

I2C0CONCLR (I2C0 Configuration Clear Register)

• It is an 8-bit write only register.

• Bit 2 – AAC (Assert Acknowledge Flag Clear)

o Setting this bit clears the AA bit in I2C0CONSET register.
• Bit 3 – SIC (I2C Interrupt Flag Clear)
o Setting this bit clears the SI bit in I2C0CONSET register.
• Bit 5 – STAC (Start Flag Clear)
o Setting this bit clears the STA bit in I2C0CONSET register.
• Bit 6 – I2CENC (I2C Interface Disable)
o Setting this bit clears the I2CEN bit in I2C0CONSET register.
Dr. V.Vijayaraghavan, Associate Professor-ECE, VFSTR, Guntur
Features of I2C - bus serial I/O controller…… Data & Addr Register

I2C0DAT (I2C0 Data Register)

• It is an 8-bit read-write register, It contains the data to be transmitted or received.
• This register can be read or written to only when SI = 1.

I2C0ADR (I2C0 Slave Address Register)

• It is an 8-bit read-write register, It is only used when device is in Slave Mode.
• Bit 0 – GC (General Call)  When this bit is set, the general call address (0x00) is recognized.
• Bit 7:1 – Address  It contains the I2C device address for slave mode.

Dr. V.Vijayaraghavan, Associate Professor-ECE, VFSTR, Guntur

Features of I2C - bus serial I/O controller…… SCLL & SCLH Registers
I2C0SCLL (I2C0 SCL Low Duty Cycle Register)
• It is an 16-bit register, It contains the value for SCL Low time of the cycle.

I2C0SCLH (I2C0 SCL High Duty Cycle Register)

• It is an 16-bit register, It contains the value for SCL High time of the cycle.

Dr. V.Vijayaraghavan, Associate Professor-ECE, VFSTR, Guntur

Features of I2C - bus serial I/O controller……

I2C Operating Modes:

• Master Transmitter mode
• Master Receiver mode
• Slave Receiver mode
• Slave Transmitter mode

Dr. NVR Vikram G, Assistant Professor-ECE, VFSTR, Guntur

Features of I2C - bus serial I/O controller……

I2C Operating Modes…

• Master Transmitter mode

Format of Master Transmitter mode

Dr. NVR Vikram G, Assistant Professor-ECE, VFSTR, Guntur

Features of I2C - bus serial I/O controller……

I2C Operating Modes…

• Master Receiver mode

Format of Master Receive mode

Dr. NVR Vikram G, Assistant Professor-ECE, VFSTR, Guntur

Features of I2C - bus serial I/O controller……

I2C Operating Modes…

• Master Receiver / Transmitter mode with repeated start

A master receiver switch to master Transmitter after sending repeated START

Dr. NVR Vikram G, Assistant Professor-ECE, VFSTR, Guntur

Features of I2C - bus serial I/O controller……

I2C Operating Modes…

• Slave Receiver mode

Format of Slave Receiver mode

Dr. NVR Vikram G, Assistant Professor-ECE, VFSTR, Guntur

Features of I2C - bus serial I/O controller……

I2C Operating Modes…

• Slave Transmitter mode

A master receiver switch to master Transmitter after sending repeated START

Dr. NVR Vikram G, Assistant Professor-ECE, VFSTR, Guntur

 REFERENCE BOOKS
 Andrew N Sloss, Dominic Symes and Chris Wright, “ARM system developer’s
guide”, Elsevier - Morgan Kaufmann Publishers, 2008.
 Joseph Yiu, “The Definitive Guide to the ARM CORTEX-M3”, 2nd Ed, Elsevier-
Newnes, 2010.
 Steve Furber, “ARM System on Chip Architecture”, 2nd edition, Pearson
education, 2000.
 Martin Trevor, “The Insider’s Guide to the ARM7 based microcontrollers”, Hitex
Ltd., 2006.
 William Hohe and Christopher Hinds, “ARM Assembly Language”, 2nd edition,
CRC Press, 2015.
 David Seal, “ARM Architecture Reference Manual”, Addison-Wesley, 2001.
 “LPC214x User Manual (UM10139)”, Volume 1, Philips Semiconductors, 2015.
 https://www.engineersgarage.com/arm-projects/how-to-start-programming-
arm7-based-lpc2148-microcontroller
 http://www.electronicwings.com/arm7/lpc2148-pwm
Dr. V.Vijayaraghavan, Associate Professor-ECE, VFSTR, Guntur
Thank You!
Any questions?

Dr. V. VIJAYARAGHAVAN,
Associate Professor - ECE,
VFSTR (Deemed to be University),
Vadlamudi, Guntur, AP.