Scribd
Upload
7 views

Analog Assignment 3 - 24MVD0059

Excellent

Uploaded by

19b110
Copyright
© © All Rights Reserved
Available Formats
Download as PDF, TXT or read online on Scribd
7 views

Analog Assignment 3 - 24MVD0059

Excellent

Uploaded by

19b110
Copyright
© © All Rights Reserved
Available Formats
Download as PDF, TXT or read online on Scribd
You are on page 1/ 17

Fall Semester 2024-2025

Analog IC Design
Practice Lab Report

Assessment 3:
Experiment 05 & Experiment 06
(Assessment No.03)
Course Code: MVLD504P
Slot: L47+L48

Submitted by: Nandagopan KM


Reg. No: 24MVD0059
Submitted to: Dr. Abdul Majeed KK
Experiment 05: Common Source Amplifier
Design Using Gm over Id Method

AIM:

➢ To design a common source amplifier with resistive load with specifications,


➢ Voltage Gain Av = 4,
➢ Unit gain Bandwidth = 100MHz
➢ Given, Load capacitance = 5pF

Tool: Cadence

Schematic Diagram:

Figure 1 : Schematic diagram of CS Amplifier


Figure 2 : Schematic diagram of CS Amplifier for width calculation

Procedure:

1. Invoke CADENCE tool

2. From the NMOS characteristics Schematics (Figure 2) Calculate RD for the required
gain and bandwidth.

3. Using the RD find the Id, Gm for the required value, and Gm/Id

4. From the Gm Over Id plot and Id over W plot, find the Vgs and Id/W plot for the
calculated Gm/Id.

5. From the Id/W value calculate the W for the required Id

6. Using the RD and W values creates a new schematic of the CS amplifier as shown in
Figure 1.

7. Launch ADE L >> AC analysis >> Variable Frequency (1 to 100GHz), Logarithmic


scale 1000 points>> Apply>>Ok

8. Output >> To be plotted >> Select On the design >> Select the Output Voltage and
Input Voltage.

9. Run the simulation, Results >> Direct Plot >> AC Phase and Gain

10. From the Plot find the Maximum gain, Max-3dB frequency, Unit gain frequency, and
3dB Frequency.
Design and Analysis:
Output Graphs:

Figure 3 : Maximum Gain

Figure 4 : 3dB Frequency


Figure 5 : Unity gain Frequency

Figure 6 : Pole Zero Locations


Result and Inference:
Experiment 6: Design And Implementation
of Simple and Cascade Current Mirrors
AIM:

➢ To design a Simple Current mirror and Cascade Current Mirror with


specifications,
➢ I = 100𝛍 A
➢ Using the designed values, design a new Cascade Current mirror with 5I.

Tool: Cadence

Schematic Diagram:

Figure 7 : Schematics- Simple Current Mirror


Figure 8 : Schematics- Cascade Current Mirror
Procedure:

1. Invoke CADENCE tool

2. From the NMOS characteristics Schematics (Figure 3) find V th

3. Assume Vdsat = 200mV and find Vgs using Vgs= Vdsat+Vth

4. From ID /W Vs Vgs of NMOS characteristics find ID /W for calculated Vgs.

5. For the required value of I find W from the ID /W using I/ID /W

Figure 9 : NMOS Chararcterisation - gm/Id

Figure 10 : NMOS Chararcterisation - Id/W


Figure 11 : NMOS Chararcterisation - Vth

6. Using the W create the schematics of the Simple Current mirror (Figure 1) and the
Cascade Current Mirror (Figure 2).

7. Plot the ID Vs Vdc of the circuits.

8. To design a Cascade with 5I current output, the new W for Output MOSFETs is 5W

9. Create the Schematics for the new Cascade Current mirror

10. And Plot the ID Vs Vdc.


Design and Analysis:
Output Graphs:

Figure 12 : Vgs from gm/id graph

Figure 13 : Vth for NMOS

Figure 14 : Id/W graph


Figure 15 : Id Vs Vdc of Simple Current Mirror

Figure 16 : Id Vs Vdc of Cascade Current Mirror

Figure 17 : Id Vs Vdc of Cascade Current Mirror with 5I


Result and Inference:

You might also like