h a % 10. PROBLEMS aon 42, t 4-13] Chapter 4 Problems 149 Encecovac, M. D., and T. LANG, Digital Systems anil Hardware/Firmware Algorithms. ‘New York: John Wiley, 1985. Manck, D., Analysis and Synthesis of Logic Sysiems. Norwood, MA: Artech House, 1986. SuivA, S. G., dntroduction to Logic Design. Glenview, IL: Scott, Foresman, 1988, MCCLUSKEY, E. J., Logic Design Principles. Englewood Cliffs, NI: Prentice-Hall, 1986. Design a combinational circuit with three inputs and one ootput. The output is equal to logic-1 when the binazy value of the inpat is less than 3. The output is logic-0 otherwise Design a combinational circuit with three inputs, x, y, and 2, and three ouputs, A. B. and . When the binary input is 0, 1, 2, or 3, the binary output is one greater than the input. ‘When the binary input is 4, 5, 6, of 7, the binary outpot is one less than the input. A majority function is generated in a combinational circuit when the output is equal to 1 if, the input variables have more 1's than O's. The output is 0 otherwise. Design a 3-inpnt ‘majority function, ‘Design a combinational circuit that adds one to a 4-bit binary number, Ay AaAy Ay. For ex ample, ifthe inpot of the circuit is As AzA; Ao = 1101, the outpat is 1310, The eircuit can bbe designed using four half-adders. ‘A combinational circuit produces the binary sum of two 2-bit numbers, x1x9 and yi. The ‘outputs are C, 5,, and So. Provide a trath table of the combinational circuit, Design the circuit of Problem 4-5 using two full-adders. Design a combinational circuit that multiplies two 2-bit numbers, ado and bb, to pro~ duce a 4-bit product, csezeice. Use AND gates and half-adders. ‘Show that a full-subtractor can be constructed with two half-subtractors and an OR gate. Desiga a combinational circuit with three inputs and six outputs. ‘The ouput binary aum- ber should be the square of the input binary umber. Design 4 combinational circuit with four inputs that represent a decimal digit in BCD and four outputs that produce the 9's complement of the input digit. The six unused combina- tions can be treated as don’t-care conditions. . Design a combinational cireuit with four inputs and four outputs. The output generates the 2's complement of the input binary number. Design a combinational circuit that detects an ercor in the representation of a decimal digit in BCD. The output of the circuit must be equal to logic-1 when the inputs contain any ‘one of the six unused bit combinations in the BCD code. Design a code converter that converts a decimal digit ftom the 8 4-2 —1 code to BCD (see Table 1-2.)150 Chapter 4 Combinational Logie [a-1a Design a combinational circuit that converts a decimal digit from the 2 4.2 1 cade to the 84 —2 ~1 code (see Table 1-2.) 415 Design a combinational circuit that converts a binary number of four bits to a decimal number in BCD. Note that the BCD number is the same as the binary musaber as long as the input is less than or equal to 9. The binary number from 1010 to 1111 converts into. BCD numbers from 1 0000 to 1 0101. 16 A BCD-to-seven-segmeat decoder is a combinational circuit that converts a decimal digit : ‘in BCD (o an appropriate code for the selection of segments in a display indicator used for displaying the decimal digit in a familiar form. The seven outputs of the decoder (a, by ¢, 4, e, f. 2) select the corresponding segments in the display, as showa io Fig. P4-16(a). ‘The womeric. designation chosen to represent the decimal digit is shown in Fig. P4-16(b). Design the BCD-to-seven-segment decoder using a minimum number of NAND gates. ‘The six invalid combinations should result in a blank display. dibko = - rm ri _ roid dak: ul 7 my (a) Segment designation (b) Numerical detignation for display Ficume Pa-16 4-17 Analyze the two-output combinational circuit shown in Fig. P4-17, Find the Boolean functions forthe two culpots asa function ofthe theee inputs and explain the circuit oper- ation. 4-18 Derive the truth table of the circuit shown in Fig. P4-17. 4 B FIGURE P4-17Chapter S Problem: 199 5-8 Derive the two-level Boolean expression for the output carry Cs shown in the look-ahead carry generator of Fig. 5-5. 5-9 How many unused input combinations are there in a BCD adder? «6-40 Desiga a combinational circuit that genersted the 9°s complement of a BCD digit. $11 Construct a 4-digit BCD adder-subtractor using four BCD adders, as shown in Fig. $-6, os and four 9°s complement circuits fom Problem 5-10, Use block diagrams for each compo: nent, showing only inputs and outputs. 5-12 tis necessary to design a decimal adder for two digits represented in the excess-3 code. ~ Show that the correction after adding the two digits with a 4-bit binary adder is as fol- + ews: (a) The ouput carry is equal to the carry ftom the binary adder. (©) Ifthe output carry = 1, then add 0011. (©) Wthe ouput carry = 0, then add 1101 Construct the decimal adder with two 4-bit adders and an inverter. 5-13 Design a combinational circuit that compares two 4-bit numbers A and B to check if taey are equal. The citcuit hes one output x, sothatx = 1ifA = Band x = Oif A is not equal woB. 5-14° Design a BCD-to-decimal decoder using the unused combinations of the BCD code as don’ -care conditions. 5-05 A combinational circuit is defined by the following three Boolean functions. Design the Circuit with a decoder and external gates. Fest tar Rawr try Bo x'y's + ay 5-16 A combinational circuit is specified by the following three Boolean functions. Implement the circuit with a 3.x 8 decoder constructed with NAND gates (similar to Fig, 5-10) and three external NAND ot AND gates. Use a block diagram for the decoder. Minimize the ‘urnber of inpats in the external gates. F(A, B, C) = 202, 4, 7} FAA, B,C) = 3(0, 3) FIA, B,C) = 3, 2, 34,7) 5-17 Draw the logic diagram of a 2-to-d line decoder with only NOR gates. Incinde an enable input, [ET Construct a 5 x 32 decoder with four 3 x & decodere with enable and one 2X 4 de- coder. Use block diagrams similar to Fig. 5-12. 5-19 Rearrange the truth (able for the circuit of Fig. 5-10 and verify that it can fonction as a derauitiplexer. 5-20 Design a 4-input priority encoder with inputs as in Table 5-4, but wich input Dp having the ‘highest priority and input Ds the lowest priarizy.200 Chapter S MS! and PLD Components Specify the truth table of an octal-to-binary priority encoder: Provide an ourput V to indi- fate that at least one of the inputs is 1. The inpot with the highest subscript number has the highest priority. What will be the value of the four outputs if inputs D; and Ds are | and the other inpers are all 0's? -22] Draw the logic diag:am of a dual 4-t0-L-line multipleser with common selection inputs ‘and a common enable input. 5-23] Construct a 16 X 1 caukiplexer with two 8 x 1 and one 2 % 1 multiplexers. Use block diagraras for the three smultiplexers, 5-24] implement the following Boolean functioa with an & X ¥ multiplener. F(A, B,C, D) = 20, 3, 5.6, 8,9, 14, 15) 5-25) Implement a full-adder with two 4 1 multiplexers. Implement the Boolean function of Example 5-2 with an 8 x 1 multiplexer, but with in- pots A, B, and C connected to selectiog inputs s,s, and so respectively. 5-27) An 8 X 1 multiplexer has inputs A, B, and C connected to the selection inputs s,s), and fu respectively. The data inputs, Jo through b, are as follows: f, = hk = fy = 0; ihe 1.= 1; fo = In = D; and f= D’, Determine the Boolean function that the multi- plexer implements. Implement the following Boolean function with a4 X 1 multiplexer and external gates. ‘Connect inputs A and B to the selection lines. ‘The input requirements tor the four data fines will be a fuactiou of variables Cand D. These values are obtained by expressing F as ‘a fonction of C and D for exch of the Zour cases when AB = 00, O1, 10, and 11. These functions may have to be implemented with external gates. F(A, B,C, D) = BU, 3,4, 1, 12, 13, 14, 15) 5-29 Given a 32 x 8 ROM chip with an enable input, show the extemal connections necessary to construct a 128 X 8 ROM with four chips and a decoder. 5.30 A ROM chip of 4096 X 8 bits has two enable inputs and operates from a S-valt power supply. How many pins are needed for the integrated-circuit package? Draw a block dia- ‘gram and label all inpur and output terminals in the ROM. 5-31 Specify the size of s ROM (number of words and numbe: of bits per word) that will ac~ commodate the truth table for the following combinational circuit compouents: (a) A binary multiplier that multiplies two 4-bit aumbers. (b) A 4-bit adder-subuactor; see Fig. 5-20). fo) A quadruple 2-t0-I-line multipiexers with common select and enable inputs; see 5-17. {ay A BCD-to-seven-segment decoder with an enable input; see Problem 4-16. 5-32 Tabulate the truth table for an 8 x 4 ROM thal implements the following four Boolcun functions! Als y= BU, 2,4, 6) Bis, ¥. 2) = 20, 1, 6,7) Ch, y, 2) = 30, 6) D(x, yt) = EU, 2.3.5.7)