AND9083/D

MOSFET Gate-Charge
Origin and its Applications
Introduction
Engineers often estimate switching time based on total
drive resistances and gate charge or capacitance. Since www.onsemi.com
capacitance is non-linear, gate charge is an easier parameter
for estimating switching behavior. However, the MOSFET APPLICATION NOTE
switching time estimated from datasheet parameters does not
normally match what the oscilloscope shows. This is due to
differences between the parameters taken from the datasheet
and the application conditions. For example, in Figure 1 the 32 V
gate charge of NTD5805N was characterized at two
different conditions and results varied greatly. If datasheet
values are characterized at conditions different from the +
user, the differences will introduce error in the estimation. 0 à 10 V
ID VDS
This article will explain how to better estimate gate charge −
from datasheets and their applications. For simplicity in this
article, power MOSFET NTD5805N’s datasheet [1] is used +
VGS
with circuit conditions of 32 V and 30 A. −

10
VGS, GATE−TO−SOURCE VOLTAGE (V)

9
8 ID = 30 A, VDS = 5 V
30 A
7
6
5 ID = 5 A, VDS = 30 V
4
Figure 2. Inductive Switching
3
2
QSW
1 10 35
VGS, GATE−TO−SOURCE VOLTAGE (V)

VDS, DRAIN−SOURCE VOLTAGE (V)

0 9 ID
0 5 10 15 20 25 30 35 VDS 30
8

ID, DRAIN CURRENT (A),

QG, TOTAL GATE CHARGE (nC) QG
7 25
Figure 1. NTD5805N Gate-to-Source Voltage vs.
Total Charge 6
20
5 VGP
Inductive Switching 4 15
In switch-mode power supplies, MOSFETs switch 3 10
inductive loads. Figure 2 shows a basic buck circuit with high VTH
2
side MOSFET turn on transition. Before the high side A B C 5
1
MOSFET is turned on, inductor current is flowing through the
0 0
low side MOSFET’s body diode (VBD). The turn-on transition 0 10 20 30
is broken down into three regions (Figure 3). These regions QG, TOTAL GATE CHARGE (nC)
will be individually explained. Figure 4 shows the transition
through these regions in terms of output characteristics. Gate Figure 3. Gate-to-Source Voltage
charge can be derived from the non-linear capacitance and Switching vs. Total Charge
curves, which are fully characterized at a range of VDS
(VGS = 0 V) and VGS (VDS = 0 V) as shown in Figure 5.

© Semiconductor Components Industries, LLC, 2016 1 Publication Order Number:

February, 2016 − Rev. 2 AND9083/D
 AND9083/D

VGS = 5.5 V − 10 V
100 3000
90 VGS = 5.2 V
2500
80
ID, DRAIN CURRENT (A)

5V

C, CAPACITANCE (pF)
70 Ciss
2000
60 C
4.5 V
50 1500
40 C B VGP 4.2 V 1000 A
30
4V Coss
20
500
A
10 B
3.5 V Crss
0 0
0 1 2 3 30 40 10 5 0 5 10 15 20 25 30 35 40
VDS, DRAIN−TO−SOURCE VOLTAGE (V) VGS VDS
GATE−TO−SOURCE OR DRAIN−TO−SOURCE VOLTAGE (V)
Figure 4. On-Region Characteristics for Different
Gate-to-Source Voltages Figure 5. Capacitance Variation

Region A: MOSFET QGS Region C: MOSFET Remaining Total Gate Charge

This is the region where gate-to-source voltage (VGS) This is the region where the MOSFET enters into ohmic
rises from 0 V to its plateau voltage (VGP). When the gate mode operation as seen in the ID−VDS curve (Figure 4). VGS
rises from 0 V to its threshold voltage (VTH), the MOSFET rises from VGP to driver supply voltage (VGDR). Both ID and
is still off with no drain current (ID) flow and drain-to-source VDS remain relatively constant. ID is still clamped by the
voltage (VDS) remains clamped. Once gate voltage reaches inductor current. As VGS increases, the channel
VTH, the MOSFET starts conducting and ID rises. Its VDS is (VDS = I * RDS(ON)) continue to be more enhanced and VDS
still clamped to VDD + VBD until all inductor current is dropped slightly. The charge needed is shown as region C in
being supplied by the MOSFET. In this region, gate current Figure 5 and can be calculated by Equation 3.
is used to charge the input capacitance (Ciss) with its VDS
being clamped. Since voltage across gate-to-drain changes QC ^ ŕ VV GDR
GP
Ciss(V GS) @ dV (eq. 3)
from VDD to VDD – VGP, charge is stored from the input
capacitance curve at that range. It can be approximated by
Equation 1. Getting the Gate Charge for Different Conditions
It was explained above how different sections of gate
Q GS ^ ŕ V DD
V DD * V GP Ciss(V DS) @ dV (eq. 1) charge are formed. Circuit conditions determine gate charge
boundaries between regions A, B and C (Figure 6). The
range is set by VDD and VGDR. VGP can be found from
Region B: MOSFET QGD ID−VDS curves at inductor current (ID) and supply voltage
This is the region where VGS is held at VGP and remains (VDD). With these three voltages found, gate charge equals
flat. ID clamps to inductor current and VDS clamping effect to area under those capacitance regions. An example is
is gone, MOSFET’s VDS starts to drop. It can be seen from shown in Table 1 employing methodology described the
ID−VDS curve (Figure 4) that VGS remains relatively same circuit conditions as characterization data in Figure 1
constant at fixed ID with varying VDS. This is the origin of using only simple estimations. Total gate charge (QGTOT) is
the flat plateau seen on the gate charge curve. During this the total amount charge stored by the MOSFET on its gate
region, the gate current is used to charge the reverse transfer up to the driver voltage. Switching gate charge (QSW) is the
capacitance (Crss). VDS is decreasing from VDD + VBD to amount charge needed to complete ID and VDS transitions.
ID * RDS(ON). Thus the voltage across Crss (gate-to-drain
capacitance) changes from {(VDD + VBD) − VGP} to
{(ID * RDS(ON)) − VGP}. The polarity of voltage is reversed.
Charge (Equation 2) needed for this transition is shown as
the area under region B capacitance curve of Figure 5.

Q GD ^ ŕ V0 DD * V GP
Crss(V DS) @ dV )
(eq. 2)

)ŕ
V GP
Crss(V GS) @ dV
0

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 AND9083/D

GATE−TO−SOURCE OR DRAIN−TO−SOURCE VOLTAGE (V)

VGS VDS
3000

2500

C, CAPACITANCE (pF)
C
2000

1500
A

1000

500
B
0
VGDR VGP(ID) VDD − VGP(ID) VDD

Figure 6. Circuit Parameters Effects

Table 1. ESTIMATION OF GATE CHARGE BASED ON METHOD DESCRIBED

Parameters VDD = 30 V, ID = 5 A VDD = 5 V, ID = 30 A Refer to
VGP 3.6 V 4.2 V ID – VDS Curve
Region A − Charge 3.6 V * 1.7 nF ≈ 6.1 nC 4.2 V * 1.9 nF ≈ 8.0 nC
Region B − Charge (30 V – 3.6 V) * 0.2 nF + (5 V – 4.2 V) * 0.4 nF +
3.6 V * 1.1 nF ≈ 9.2 nC 3.6 V * 1.1 nF ≈ 4.9 nC Capacitance Curve

Region C − Charge (10 V – 3.6 V) * 2.7 nF ≈ 18 nC (10 V – 4.2 V) * 2.7 nF ≈ 15.95 nC

QGTOT 33 nC 29 nC Sum A, B & C
VTH 2.7 V 2.7 V Datasheet Value
QSW (3.6 V – 2.7 V) / 3.6 V * 6.1 nF + (4.2 V – 2.7 V) / 4.2 V * 8.0 nF + QA(after VTH) + QB
9.2 nC ≈ 11 nC 4.9 nC ≈ 7.8 nC

Resistive Switching 32 V
LED and heating coil are examples of resistive switching.
The main difference between inductive and resistive 32 / 30 W
switching is that there is no clamping of drain current
involved. Before reaching its threshold voltage, the FET is
off. When the MOSFET starts to turn-on in the saturation +
region, VDS is dependent on resistive load and voltage ID VDS
0 à 10 V
supply. Once the FET is in ohmic mode, the MOSFET and −
the load become a simple resistor divider. There is no flat +
plateau region as both VDS and ID are changing resulting in VGS
−
increasing VGS (Figure 9 region E). Fortunately, QSW and
QGTOT are unchanged from inductive switching.
Figure 7. Resistive Switching

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 AND9083/D

QSW
10
VGS, GATE−TO−SOURCE VOLTAGE (V) 35 100

VDS, DRAIN−SOURCE VOLTAGE (V)

9 ID 90
VDS 30
8 80

ID, DRAIN CURRENT (A),

ID, DRAIN CURRENT (A)

7 25 70
6 60
20
5 50
4 15 40
F
3 10 30
VTH E
2 20
E F 5
1 10
D D
0 0 0
0 10 20 30 0 10 20 30 40
QG, TOTAL GATE CHARGE (nC) VDS, DRAIN−TO−SOURCE VOLTAGE (V)
Figure 8. Gate-to-Source Voltage and Switching Figure 9. On-Region Characteristics for Different
vs. Total Charge (Resistive Switching) Gate-to-Source Voltages

Gate Charge Applications

One important aspect of MOSFET applications is the charge (QSW) is the amount of current the gate driver needed
power losses. There are several power loss components. to supply to complete the switching transitions of drain
Conduction loss is power dissipated in the resistive element voltage and current. Gate charge loss (PQG) is power
(RDSON) of the channel. Switching loss (PSW) is power dissipated due to charging and discharging of the gate.
dissipated in switching current and voltage. Switching gate
P QG + Q GTOT@VGDR @ V GDR @ F SW (eq. 4)

Q SW + Q GS(afterVth) ) Q GD (eq. 5)

T SW(ON) + Q SWń ǒ V GDR * V GP

R DR ) R G
Ǔ
, T SW(OFF) + Q SWń
V GP
R DR ) R G
ǒ Ǔ (eq. 6)

P SW(inductive) + 0.5 @ V DD @ I D @ ǒT SW(ON) ) T SW(OFF)Ǔ @ F SW (eq. 7)

P SW(resistive) + 0.25 @ V DD @ I D @ ǒT SW(ON) ) T SW(OFF)Ǔ @ F SW (eq. 8)

Derivations above do not apply to zero voltage switching inductive switching or short-circuit performance can also be
applications. For example in synchronous rectification, evaluated.
MOSFET has a negative diode voltage drop across VDS 40
(body diode conduction) before it is turned on. They can still
35 QGTOT@10 VGS
be derived from the capacitances (VGS side) and ID−VDS
curve using the same idea. 30
GATE CHARGE (nC)

Conclusion 25 ID = 1 A
With different circuit conditions, it has been shown how ID = 50 A
datasheet gate charge parameters changes. Only simple 20
mathematics is needed in getting the right gate charge. 15
The origins of gate charge are analytically explained. QSW
Through understanding of MOSFET gate charge, more 10
accurate estimations can be made in designing for different 5
circuit conditions (Figure 10). Trade offs are evaluated in
0
selecting gate drive schemes. A lower gate drive voltage 0 10 20 30 40
would save some energy but must be balanced between VDS, DRAIN−TO−SOURCE VOLTAGE (V)
higher on-resistance. Using methods described by D. Lee in Figure 10. NTD5805N Gate Charge at Various
[2], extreme operating conditions like repetitive unclamped Conditions

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 AND9083/D

APPENDIX A: ESTIMATION WITHOUT CAPACITANCE-vs-VGS CURVE

3000

2500

C, CAPACITANCE (pF)
Ciss
2000

1500

1000
Coss
500
Crss
0
10 5 0 5 10 15 20 25 30 35 40
Vgs Vds

GATE−TO−SOURCE OR DRAIN−TO−SOURCE VOLTAGE (V)

Figure 11. NTD5805N Capacitance Curves

Since most of the MOSFETs datasheet are without information. The missing Capacitance-vs-VGS curves will
Capacitance-vs-VGS curve (shaded part of the Figure 11), concern region B and region C.
estimation will have to be made based on the available

Figure 12. Circuit Parameters Effects

For region B, we can assume VGP(ID) are relative constant For region C, we can estimate the gate charge after
in modern trench MOSFET devices. Due to the high trench VGP(ID) due to its constant capacitance.
density (high transconductance), a large change in drain
current, ID, only resulted in small increase in gate plateau
voltage, VGP(ID).

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 AND9083/D

For example using 40 V NTMFS5C442NL,

180
220 10 V to 4.5 V 4.0 V
VDS = 3 V
200 160
3.8 V
180
ID, DRAIN CURRENT (A)

ID, DRAIN CURRENT (A)

140
160 3.6 V 120
140
3.4 V 100
120
100 3.2 V 80
TJ = 25°C
80 60
3.0 V
60
2.8 V 40
40
20 TJ = 125°C
20
TJ = −55°C
0 0
0 0.5 1.0 1.5 2.0 2.5 3.0 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0
VDS, DRAIN−TO−SOURCE VOLTAGE (V) VGS, GATE−TO−SOURCE VOLTAGE (V)

Figure A. On-Region Characteristics Figure B. Transfer Characteristics

Figure 13. NTMFS5C442NL Datasheet Curves

From Figure A and B of NTMFS5C442NL, we can see for every 15 A increase or decrease in drain current. We can
that when Gate-to-Source voltage, VGS, changed from 3.0 V conclude that VGP for modern trench MOSFET devices are
to 3.2 V the drain current, ID, increase by 30 A. Therefore, relative constant due to high transconductance.
it implied gate plateau VGP change by approximately 0.1 V

Table 2. NTMFS5C442NL DATASHEET PARAMETERS

Parameter Symbol Test Condition Min Typ Max Unit
Total Gate Charge QG(TOT) VGS = 4.5 V, VDS = 32 V, ID = 50 A − 23 −
Total Gate Charge QG(TOT) VGS = 10 V, VDS = 32 V, ID = 50 A − 50 −
Threshold Gate Charge QG(TH) − 5.0 − nC
Gate-to-Source Charge QGS − 9.8 −
VGS = 4.5 V, VDS = 32 V, ID = 50 A
Gate-to-Drain Charge QGD − 6.7 −
Plateau Voltage VGP − 3.1 − V

Figure 14. NTMFS5C442NL Capacitance Curves with Datasheet Test Conditions

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 AND9083/D

Region A = QGS = 9.8 nC (estimated from curve = 3.1 V * 3100 pF = 9.6 nC)
Region B = QGD = 6.7 nC
Region C = QGTOT – QGS – QGD = 33.5 nC

Calculate for Different Test Conditions

For example at VGS = 6 V, VDS = 20 V, ID = 20 A:

Figure 15. NTMFS5C442NL Capacitance Curves with New Test Conditions

Region A = 3.1 V * 3100 pF = 9.6 nC

Region B = 6.7 nC – (12 V * 100 pF) = 5.5 nC
Region C = 33.5 nC / (10 V – 3.1 V) * (6 V – 3.1 V) = 14.1 nC

Figure 16. Graphic Representation of Change in Above NTMFS5C442NL Estimation

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 AND9083/D

Figure 17. Gate Charge Comparison between Test Conditions

The change in gate change can be seen in Figure 16 with

new test condition in shaded regions.

REFERENCES

[1] ON Semiconductor, “Power MOSFET 40 V [3] ON Semiconductor, “Power MOSFET 40 V

NTD5805N Datasheet”, NTMFS5C442NL Datasheet”,
http://www.onsemi.com/pub_link/Collateral/ http://www.onsemi.com/pub_link/Collateral/
NTD5805N−D.PDF NTMFS5C442NL-D.PDF
[2] ON Semiconductor, “MOSFET Transient Junction
Temperature Under Repetitive UIS/Short-Circuit
Conditions”,
http://www.onsemi.com/pub_link/Collateral/
AND9042−D.PDF

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