Digital Circuits

• Combinational Circuits
• Sequential Circuits
3-to-8-line Decoder

157
 Decoder with enable input

Some decoders are constructed

with NAND gates, it becomes
more economical to generate the
decoder minterms in their
complemented form.
As indicated by the truth table ,
only one output can be equal to
0 at any given time, all other
outputs are equal to 1.

158
Demultiplexer
A B
A decoder with an
enable input is
referred to as a
decoder/demultiplex
er. D0

Demultiplexer D1
The truth table of E
demultiplexer is the D2
same with decoder. D3

159
DEMULTIPLEXER
Cont.
3-to-8 decoder with enable implement the 4-to-16
decoder

162
Implementation of a Full Adder with a Decoder
From table 4-4, we obtain the functions for the combinational circuit in sum of minterms:
S(x, y, z) = ∑(1, 2, 4, 7)
C(x, y, z) = ∑(3, 5, 6, 7)

163
ENCODERS
Cont.
MAGNITUDE COMPARATOR
Cont.
2-Bit magnitude comparator
Cont.
Code Converters
Cont.
Sequential Circuits
SEQUENTIAL LOGIC CIRCUITS
Cont.
Cont.
Cont.
LATCHES
Cont.
Cont.
Cont.
SR Flip flop
JK Flip-Flop

Cont.
JK FF Truth Table:
Q (t+1)
J (Input) K (Input) Q (PS)
(NS)
0 0 0 0
0 1 0 0
1 0 0 1
1 1 0 1
0 0 1 1
0 1 1 0
1 0 1 1
1 1 1 0
Cont. 3. D Flip-Flop
D flip-flop is a better alternative that is very popular with digital
electronics. They are commonly used for counters, shift registers,
and input synchronization.
In the D flip-flops, the output can only be changed at the clock
edge, and if the input changes at other times, the output will be
unaffected.
Truth Table:

Q (t+1)
Clock D (Input) Q (PS)
(NS)
↓»0 0 0 1
↑»1 0 0 1
↓»0 1 0 1
↑»1 1 1 0
 Cont.
4. T Flip-Flop
A T flip-flop is like a JK flip-flop. These are single-
input versions of JK flip-flops. This modified form
of the JK is obtained by connecting inputs J and
K together. It has only one input along with the
Truth Table :
clock input.
T Q (PS) Q (t+1) (NS)
These flip-flops are called T flip-flops because of
0 0 0 their ability to complement their state i.e.
1 0 1 Toggle, hence they are named Toggle flip-flops.
0 1 1
1 1 0
Cont.
Need of Master-Slave FF
Cont.
The benefit of using a master-slave flip-flop is
that it is a very reliable and secure way to
store and transfer data. This is due to the fact
that the master and the slave are completely
isolated from each other. This makes it almost
impossible for any interference from the
outside to affect the output in any way.
In addition, the master and the slave are
separated by a clock signal, which ensures
that the data is only transferred when the
clock is active.
MASTER SLAVE FLIPFLOP
Cont.
Master Slave flip flop are the cascaded combination of two flip-flops among which the first is
designated as master flip-flop while the next is called slave flip-flop (Figure 1).
Here the master flip-flop is triggered by the external clock pulse train while the slave is activated
at its inversion i.e. if the master is positive edge-triggered, then the slave is negative-edge
triggered and vice-versa.
This means that the data enters into the flip-flop at leading/trailing edge of the clock pulse while
it is obtained at the output pins during trailing/leading edge of the clock pulse.
Hence a master-slave flip-flop completes its operation only after the appearance of one full
clock pulse for which they are also known as pulse-triggered flip-flops.
Internal structure of a master-slave JK flip-flop
in terms of NAND gates and an inverter
From figure it is also evident that the
slave is driven by the outputs of the
master (M1 and M2), which is in
accordance with its name master-
slave flip-flop. Further the master is
active during the positive edge of the
clock due to which M1 and M2 change
their states; depending on the values
of J and K. However at this instant the
outputs of the overall system (master-
slave JK flip-flop) remains unchanged
as the slave will be inactive due to
positive-edge of the clock pulse.
Similar to this, the slave decides on its
outputs Q and Q̅ depending on its
inputs M1 and M2, during the negative
edge of the clock during which the
master will be inactive.
Truth Table
The truth table corresponding to the working
of the flip-flop shown in Figure 2 is given by
Table I. Here it is seen that the outputs at the
master-part of the flip-flop (data enclosed in
red boxes) appear during the positive-edge of
the clock (red arrow). However at this instant
the slave-outputs remain latched or
unchanged. The same data is transferred to
the output pins of the master-slave flip-flop
(data enclosed in blue boxes) by the slave
during the negative edge of the clock pulse
(blue arrow).
Timing Diagram
The same principle is further
emphasized in the timing
diagram of master-slave flip-flop
shown by Figure 3. Here the
green arrows are used to
indicate that the slave-output is
nothing but the master-output
delayed by half-a-clock cycle.
Moreover it is to be noted that
the working of any other type of
master-slave flip-flop is
analogous to that of the master
slave JK flip-flop explained here.
Conversion of Flip-Flops
Flip-flops, namely:
• SR flip-flop,
• D flip-flop,
• JK flip-flop &
• T flip-flop.
We can convert one flip-flop into the remaining three flip-flops by including some additional
logic.
So, there will be total of twelve flip-flop conversions.
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Flip-flop conversion steps
SR Flip-Flop to other Flip-Flop
Conversions
Cont.
Cont.
Cont.
D flip-flop to T flip-flop conversion
Cont.
Cont.
Shift Registers
• We know that one flip-flop can store one-bit of information.
• To store multiple bits of information, we require multiple flip-flops.
• The group of flip-flops, which are used to hold store the binary data is known as register.
• If the register is capable of shifting bits either towards right hand side or towards left hand
side is known as shift register.
• An ‘N’ bit shift register contains ‘N’ flip-flops. Following are the four types of shift registers
based on applying inputs and accessing of outputs.

https://www.tutorialspoint.com/digital_circuits/digital_circuits_shift_registers.htm
Serial In − Serial Out SISO
Shift Register In this shift register,
we can send the bits
serially from the input
of left most D flip-
flop. Hence, this input
is also called as serial
input. For every
positive edge
triggering of clock
signal, the data shifts
from one stage to the
next. So, we can
receive the bits
serially from the
output of right most
D flip-flop. Hence,
this output is also
called as serial
output.
Cont.
Serial In - Parallel Out SIPO
Shift Register
Parallel In − Serial Out PISO
Shift Register
Parallel In -
Parallel Out
PIPO
Shift
Register
Example
Counters
• A special type of sequential circuit
used to count the pulse is known
as a counter, or a collection of flip
flops where the clock signal is
applied is known as counters.
• The counter is one of the widest
applications of the flip flop.
• Based on the clock pulse, the
output of the counter contains a
predefined state.
• The number of the pulse can be
counted using the output of the
counter.
Asynchronous or ripple counters
Cont.
Operation
Condition 1: When both the flip flops are in reset condition.
Operation: The outputs of both flip flops, i.e., QA QB, will be 0.

Condition 2: When the first negative clock edge passes.

Operation: The first flip flop will toggle, and the output of this flip flop will
change from 0 to 1. The output of this flip flop will be taken by the clock input
of the next flip flop. This output will be taken as a positive edge clock by the
second flip flop. This input will not change the second flip flop's output state
because it is the negative edge triggered flip flop.
So, QA = 1 and QB = 0

Condition 3: When the second negative clock edge is applied.

Operation: So, QA = 0 and QB = 1.

Condition 4: When the third negative clock edge is applied.

Operation:
So, QA = 1 and QB = 1

Condition 5: When the fourth negative clock edge is applied.

Operation: The first flip flop will toggle again, and the output of this flip flop
will change from 1 to 0. This output will be taken as a negative edge clock
by the second flip flop. This input will change the output state of the second
flip flop.
So, QA = 0 and QB = 0
Cont.
Synchronous counters
In the Asynchronous counter, the present counter's
output passes to the input of the next counter. So, the
counters are connected like a chain. The drawback of
this system is that it creates the counting delay, and
the propagation delay also occurs during the counting
stage. The synchronous counter is designed to remove
this drawback
In the synchronous counter, the same clock pulse is
passed to the clock input of all the flip flops. The clock
signals produced by all the flip flops are the same as
each other. Below is the diagram of a 2-bit synchronous
counter in which the inputs of the first flip flop, i.e., FF-
A, are set to 1. So, the first flip flop will work as a toggle
flip-flop. The output of the first flip flop is passed to
both the inputs of the next JK flip flop.
Operation

Initially let both

1 the FFs be in the QBQA = 00 initially.
reset state
As soon as the first negative clock edge is applied, FF-A will toggle
and QA will change from 0 to 1.
After 1st negative
2 But at the instant of application of negative clock edge, QA , JB = KB =
clock edge
0. Hence FF-B will not change its state. So QB will remain 0.
QBQA = 01 after the first clock pulse.
On the arrival of second negative clock edge, FF-A toggles again and
QA changes from 1 to 0.
After 2nd negative
3 But at this instant QA was 1. So JB = KB= 1 and FF-B will toggle. Hence
clock edge
QB changes from 0 to 1.
QBQA = 10 after the second clock pulse.
On application of the third falling clock edge, FF-A will toggle from 0
After 3rd negative
4 to 1 but there is no change of state for FF-B.
clock edge
QBQA = 11 after the third clock pulse.
On application of the next clock pulse, QA will change from 1 to 0 as
After 4th negative
5 QB will also change from 1 to 0.
clock edge
QBQA = 00 after the fourth clock pulse.
Classification of counters
Cont.
Ring Counter

A ring counter is a special type of application of the Serial IN Serial OUT Shift register.
The only difference between the shift register and the ring counter is that the last flip
flop outcome is taken as the output in the shift register. But in the ring counter, this
outcome is passed to the first flip flop as an input.
All of the remaining things in the ring counter are the same as the shift register.
No. of states in Ring counter = No. of flip-flop used
4-bit ring
counter

In this diagram, we can see that the clock pulse (CLK) is applied to all the flip-flops simultaneously.
Therefore, it is a Synchronous Counter. Also, here we use Overriding input (ORI) for each flip-flop.
Preset (PR) and Clear (CLR) are used as ORI. When PR is 0, then the output is 1. And when CLR is 0,
then the output is 0. Both PR and CLR are active low signal that always works in value 0.

These two values are always fixed.

They are independent of the value of
input D and the Clock pulse (CLK)
 Here, ORI is connected to Preset (PR) in FF-0 and it is connected to Clear (CLR) in FF-
Working 1, FF-2, and FF-3. Thus, output Q = 1 is generated at FF-0, and the rest of the flip-flop
generates output Q = 0. This output Q = 1 at FF-0 is known as Pre-set 1 which is used
to form the ring in the Ring Counter.
Types of Ring Counter
Types of Ring Counter
Johnson Counter
The Johnson counter is similar to the Ring counter. The only difference between the
Johnson counter and the ring counter is that the outcome of the last flip flop is passed to
the first flip flop as an input. But in Johnson counter, the inverted outcome Q' of the last
flip flop is passed as an input.
The remaining work of the Johnson counter is the same as a ring counter. The Johnson
counter is also referred to as the Creeping counter.
In Johnson counter:
•No. of states in Johnson counter = No. of flip-flop used
•Number of used states=2n
•Number of unused states=2n - 2*n
Cont.
Truth Table

CP Q1 Q2 Q3 Q4
0 0 0 0 0
1 1 0 0 0
2 1 1 0 0
3 1 1 1 0
4 1 1 1 1
5 0 1 1 1
6 0 0 1 1
7 0 0 0 1

Number of used states=2n = 8

Design of Asynchronous Counter (Decade Counter)
Design a BCD ripple counter using JK flip flops.
Cont. Step 3: Draw the truth table for BCD ripple counter.

Step 1: Find the number of flip-flops

BCD is the 4-bit number and there are
9 valid states in a 4-bit BCD. Hence 4
flip-flops should be used in the design.
The valid states are 0000, 0001, 0010,
… 1001.
Step 2: Choose the type of flip-flop.
Let us design the BCD ripple /
asynchronous counter with JK flip-
flops.
Cont.
Step 4: Use Kmap to find the reset logic function.
Cont.
Design of Synchronous Counter
Cont.
Example
J K Q Q+
0 0 0 0
0 1 0 0
1 0 0 1
1 1 0 1
0 0 1 1
0 1 1 0
1 0 1 1
1 1 1 0
Cont.
Remaining Topics of Unit-1
Finite State Machine (FSM)
• A Finite State Machine, or FSM, is a computation model that can be used to simulate
sequential logic, or, in other words, to represent and control execution flow.
• Finite State Machines can be used to model problems in many fields, including
mathematics, artificial intelligence, games or linguistics.
• A Finite State Machine is a model of computation based on a hypothetical machine
made of one or more states.
• Only one single state of this machine can be active at the same time. It means the
machine has to transition from one state to another in to perform different actions.
• A Finite State Machine is any device storing the state of something at a given time.
The state will change based on inputs, providing the resulting output for the
implemented changes.
• Finite State Machines come from a branch of Computer Science called “automata
theory”. The family of data structure belonging to this domain also includes the
Turing Machine.
Cont.
FSM important points:
• We have a fixed set of states that the machine can be in
• The machine can only be in one state at a time
• A sequence of inputs is sent to the machine
• Every state has a set of transitions and every transition is associated with an input and
pointing to a state
Real world example
Traffic Light
• States: Red, Yellow, Green
• Transitions: After a given time, Red will change to Green, Green to Yellow, and Yellow to Red
Coin-operated turnstile
• States: locked, unlocked
• Transitions: pointing a coin in the slot will unlock the turnstile, pushing the arm of the unlocked
turnstile will let the costumer pass and lock the turnstile again
According to
input variables
there are two
types of Circuits
Realization of
state table from
verbal
description,
state table,
transition
matrix
Cont.
Example
Cont.
Cont.
Cont.
Example 2
Cont.
Cont.
Cont.
Cont.
Cont.
Cont.
Cont.
Cont.
Cont.
Cont.
Cont.