Combinational Logic circuits

RANDOM SEQUENCE GENERATION

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Introduction:
In this module, we try to understand “Combinational logic circuit” and logic circuit
simplification with the help of Exercise titled “Random sequence generation using Logic
gates”

But before going into that aspect, let us have a brief idea on fundamentals required to do
this exercise.

1. Basic Gates
2. Boolean Algebra fundamentals
3. Sum of products, Products of sum expression
4. Simplification of logic circuits (Algebraic, K- Map method)

BASIC GATES:

NAND and NOR gates are called Universal gates, because with that gates we can able to
produce all other gates.

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BOOLEAN ALGEBRA:
Boolean Algebra is used to analyze and simplify digital circuits. It uses only binary
numbers that is 0 and 1 .

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Sum of products form (SOP):

The method of logic circuit simplification and design that we will study require the logic
expression to be in Sum of product form. Some examples of this form are

Products of sum form (POS):

Another general form for expression is sometimes used in logic circuit simplification
called Products of sum form

The method of circuit simplification and design that we will be using are based on Sum of
products form.

Simplifying logic circuits:

Once the expression for a logic circuit has been obtained, we may be able to reduce it to a
simpler form containing fewer terms or fewer variables in one or more terms. The new
expression can then be used to implement a circuit that is equivalent to the original
circuit but that contains fewer gates and connections.

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Advantages of simplification:

1. Smaller and Cheaper than the original circuit

2. Reliability of circuit will improve because they are fewer interconnections by
reducing potential circuit faults.
3. Reducing gates increases the operation speed of circuits.

We have two methods for simplifying logic circuits

1. Algebraic method.
2. Karnaugh Map method.

Algebraic methods:
In Algebraic methods, we will use Boolean Algebra laws, let us see this example

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Example for designing logic circuit:

Design a logic circuit that has three inputs A, B and C and whose output will be High only
when majority of inputs are high.

Step -1 : Set up the Truth table

Step -2 : Write the AND term for each case where the output is 1.

Step -3 : Write the Sum of products expression for the output

Step -4 : Simplify the output expression

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Step -5 : Implement the Circuit for the final expression

Since the expression is in SOP form, the circuit consists of a group of AND gates, working
into a single OR gate

Karnaugh Maps:
Karnaugh Map (K- Map) is a graphical tool used to simplify a logic equation or to convert
a truth table to its corresponding logic circuit in a simple orderly process. This map can
find practical applications up to four variables.

The K map is almost like a truth table, is a means of showing relationship between logic
inputs and desired output. The truth table gives the output X for each combination of
input values, the K- map gives the same information in a different format. The truth table,
K-Map for two variable, three variable, four variables are as shown below.

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• A =0 , B =0 condition in truth table corresponds to 𝐴̅𝐵̅ square in K- map, because

the truth table shows X =1 for this case , 1 is placed in the AB square in K-map.
Similarly A=1 , B=1 condition in the truth table corresponds to AB square of the K-
map, because X=1 for this case, 1 is placed in the AB square. All other squares are
filled with 0. Similar procedure followed for three variable and four variable
• K- map squares are labeled so that horizontal , vertical adjacent square differ only
in one variable
• Once K map has been filled with 0 and 1 , the sum of products expression for the
output X can be obtained by OR ing together those square that contain 1 .

Looping :

The expression for out put X can be simplified by properly combining those squares in the
K map that contain 1 . The process of combining these 1 is called Looping.

Looping a group of two:

Looping a pair of adjacent 1 in K map, eliminates a variable that appears in complimented

and uncomplemented form

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Looping a group of four (quad):

Looping a quad of adjacent 1 eliminates the two variables that appear in both
complimented and uncomplimented form

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Looping a group of Eight (Octet) :

Looping of an octet of adjacent 1 eliminates the three variables that appear in both
complimented and uncomplimented form.

When we generalized,

When a variable appears both in complemented and uncomplemented form with in a loop
, that variable is eliminated from the expression. Variables that are the same for all squares
of the loop must appear in the final expression.

Steps for K- map method for simplifying Boolean expression:

1. Construct a K- Map and place 1 in those squares corresponding to 1 in the truth

table. Place 0 in other squares.
2. Examine the map for adjacent 1 and loop those 1 that are not adjacent to any other
1 . these are called isolated 1
3. Next , look for those 1 , that are adjacent to only one other 1 , loop any pair
containing such as 1
4. Loop any octet even if it contains some 1 that have already been looped

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5. Loop any quad that contains one or more 1

6. Form the OR sum of all the terms generated by each loop

Examples :

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Don’t care conditions:

Some logic circuits can be designed so that they are certain input conditions, for which
there is no specified output level, because these input conditions will never occur. In other
words there will be certain combinations of input levels where we “don’t care” weather the
output is 1 or 0.

A circuit designer is free to make the output of any don’t care condition either 0 or 1 to
produce simplest output expression. Decision is always a not easy one.

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Now we will move towards Exercise. (Random number sequence generation)

Step 1 : Construct truth table for a given random number sequence

Step 2 : Construct Four K maps and minimize Boolean expressions with respect to
NAND gates

Step 3 : Draw Logic circuit diagram for four expressions

Step 4 : By seeing Data sheet of IC , draw pin diagram clearly

Step 5 : Take provided kit and realize the Random number sequence by giving proper
connections.

Step 6 : Document results

Step 7 : By showing output to concerned person.

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IC Diagram:

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Multiplexers:
Now we will move towards Exercise. (Random number sequence generation)

Step 1 : Construct truth table for a given random number sequence

Step 2 : Realize the output with 4x1 MUX (Based on selection lines

Step 3 : Draw Logic circuit diagram for four expressions

Step 4 : Try with different combination of selection lines select the optimized. By seeing
Data sheet of IC , draw pin diagram clearly

Step 5 : Take provided kit and realize the Random number sequence by giving proper
connections.

Step 6 : Document results

Exercise-1:

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Selection lines

Multiplexer Inputs

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For Implementation purpose please go through the Video File.

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