SW Versions

LE910 Family
LE910-EUG
17.00.5x3
LE910-NAG
LE910-NVG
LE920 Family
LE920-EUG
LE920-NAG

Note: the features described by the present document are provided by the products equipped
with the software versions equal or higher than the versions shown in the table.
 SPECIFICATIONS SUBJECT TO CHANGE WITHOUT NOTICE

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Copyright © Telit Communications S.p.A. 2014

fig. 1: Example of Digital Voice Interface Use.................................................................................................. 10
fig. 2: Telit Module/Codec Connections ............................................................................................................ 17
fig. 3: I2S bus configurations.............................................................................................................................. 21
fig. 4: Schematic for Reference Design ............................................................................................................. 22

Tab. 1: DVI Signals ........................................................................................................................................... 11

The present document provides the reader with a guideline concerning the setting and use of
the Digital Voice Interface developed on the Telit’s modules families shown in the
Applicability Table.

This Application Note covers the configurations of the Digital Voice Interface, e.g.: the
selections of the voice sampling frequency, the bit number of the voice sample, the audio
formats, etc. In addition, the document shows some configurations of a popular Audio Codec
connected to the Module. These activities are accomplished via I2S and I2C buses; the
hardware characteristics of the two buses are beyond the scope of the document.

The document is intended for those users that need to develop applications dealing with signal
voice in digital format.

For general contact, technical support, to report documentation errors and to order manuals,
contact Telit Technical Support Center (TTSC) at:

[email protected]
[email protected]
[email protected]
[email protected]

Alternatively, use:
http://www.telit.com/en/products/technical-support-center/contact.php
For detailed information about where you can buy the Telit Modules or for recommendations
on accessories and components visit:
http://www.telit.com
To register for product news and announcements or for product questions contact Telit
Technical Support Center (TTSC).
Our aim is to make this guide as helpful as possible. Keep us informed of your comments and
suggestions for improvements.
Telit appreciates feedback from the users of our information.
This document contains the following chapters:

Chapter 1: “Introduction” provides a scope for this document, target audience, contact and
support information, and text conventions.

Chapter 2: “Overview” provides an overview of the document.

Chapter 3: “Module’s DVI (PCM)” describes the DVI port

Chapter 4: “Protocol description”

Chapter 5: “Parameters and timing characteristics”

Chapter 6: “Custom AT commands”

Chapter 7: “External codec” provides an example of interfacing with an external audio codec.

Danger – This information MUST be followed or catastrophic equipment failure or bodily

injury may occur.

Caution or Warning – Alerts the user to important points about integrating the module, if
these points are not followed, the module and end user equipment may fail or malfunction.

Tip or Information – Provides advice and suggestions that may be useful when
integrating the module.

All dates are in ISO 8601 format, i.e. YYYY-MM-DD.

[1] LE910 Hardware User Guide, 1vv0301089
[2] MAX9867 Ultra-Low Power Stereo Audio Codec, MAXIM
[3] LE910 AT Commands Reference Guide, 80421ST10585A
[4] LE920 Hardware User Guide, 1vv0301026
[5] LE920 AT Commands Reference Guide, 80407ST10116A

Revision Date Changes

0 2014-03-31 First issue
1 2014-08-08 Updated supported modes
Updated supported modes
2 2014-08-22
Added note on CODEC example applicability
Add LE920 support
3 2014-11-09
Updated DVI command setting

DTE Data Terminal Equipment

DVI Digital Voice Interface
GPIO General Purpose Input/Output
I2C Inter-Integrated Circuit
I2S Inter-IC Sound
MSB Most Significant Bit
Before dealing with the configuration and technical aspects of the Telit’ Digital Voice
Interface (DVI) it is useful to illustrate briefly where and how this interface can be used, refer
to fig. 1

The voice coming from the downlink, in digital format, is captured by the dedicated software
running on the Telit’s module and directed to the Digital Voice Interface. The Audio Codec
decodes the voice and sends it to the speaker. The other way round the voice captured by the
microphone is coded by the Audio Codec and directed through the Digital Voice Interface to
the module that collects the received voice, in digital format, and sends it on the uplink.
The DVI uses the PCM interface as part of the audio front end.

Uplink

Digital Voice Interface

Downlink

Telit
Audio Codec
Module

fig. 1: Example of Digital Voice Interface Use

Although analog communication is ideal for human communication, analog transmission is
neither robust nor efficient at recovering from line noise.
As example in the early telephony network, when analog transmission was passed through
amplifiers to boost the signal, not only was the voice boosted but the line noise was amplified,
as well. This line noise resulted in an often-unusable connection.
It is much easier for digital samples, which are comprised of 1 and 0 bits, in order to be
separated from line noise. Therefore, when analog signals are regenerated as digital samples,
a clean sound is maintained.
PCM converts analog sounds into digital form by sampling the analog sounds 8000 times per
second and converting each sample into a numeric code. If you sample an analog signal at
twice the rate of the highest frequency of interest, you can accurately reconstruct that signal
back into its analog form (Nyquist theorem). Because most speech content is below 4000Hz, a
sampling rate of 8000 times per second (8 KHz that means 125 µSec between samples) is
required.

The physical DVI interface provided by the Telit’s modules is based on the I2S Bus. An
overview of the standard I2S Bus is described in chapter 4.1. Tab. 1 summarizes the DVI
signals and a short description for each one of them: refer to documents [1] and [4] to have
information on electrical characteristics and signals pin-out in accordance with the used
module.

Tab. 1: DVI Signals

The LE910 is supporting only the MASTER Mode.

The figures below show the configuration of the DVI interface relating to the Word
Alignment and Clock signals. When the module is Master the Clock and Word Alignment
signals (also called Word Alignment Output WAO) are generated by the module itself.
 The command AT#DVICFG is usable to configure the DVI interface.
Its syntax is the following:

#DVICFG – DVI CONFIGURATION

AT#DVICFG=[ Set command sets the DVI configuration
<clock>[,<decoder
pad>[,<decoder Parameter:
format>[, <clock>: Clock speed for master mode
<encoder 0 : normal mode(factory default)
pad>[,<encoder 1 : high speed mode
format>]]]]]
<decoder pad>: PCM padding enable in decoder path
0 : disable
1 : enable(factory default)

<decoder format>: PCM format in decoder path

0 : u-Law
1 : A-Law
2 : linear(factory default)

<encoder pad>: PCM padding enable in encoder path

0 : disable
1 : enable(factory default)

<encoder format>: PCM format in encoder path

0 : u-Law
1 : A-Law
2 : linear(factory default)

Note:
 #DVICFG parameters are saved in the extended profile .
 LE910 supports only the first parameter <clock>
Normal mode (factory default) = 128KHz with sample rate 8k.
High speed mode = 2048KHz with sample rate 16k.
 LE920 supports only the first parameter <clock>
Normal mode (factory default) = 2048KHz with sample rate 8k.
High speed mode = 4096KHz with sample rate 16k.
 Another parameters (<decoder pad>,<decoder format>,<encoder
pad>,<encoder format>)have no effect and are included only for backward
compatibility.
AT#DVICFG=? Test command returns the supported range of values of parameter <clock>,
<decoder pad>,<decoder format>,<encoder pad>,<encoder format>.
 The AT#DVI command enables/disables the DVI interface.
Its syntax is the following:

AT#DVI=<mode> Set command enables/disables the Digital Voiceband Interface.

[,<dviport>,
<clockmode>] Parameters:
<mode> - enables/disables the DVI.
0 – DVI disabled; (factory default)
1 – DVI enabled;

<dviport>
2 - DVI port 2 (factory default)

<clockmode>
0 - DVI slave (mode not supported)
1 - DVI master (factory default)

Note:
#DVI parameters are saved in the extended profile
LE910/LE920 support “DVI master” mode only.

The <dviport> and <clockmode> parameters have no effect and are included only
for backward compatibility with the Telit
On Active/MT/MO Voice Call return Error.
AT#DVI? Read command reports last setting, in the format:

#DVI: <mode>,<dviport>,<clockmode>
AT#DVI=? Test command reports the range of supported values for parameters
<mode>,<dviport> and <clockmode>
Example AT#DVI=1,2,1
OK

DVI activated for audio. DVI is configured as master providing on DVI Port #2
The LE910 modules have the following possible configurations:

Normal mode (factory default)

 Master Mode
 8KHz
 16 bits
 128KHz clock

High Speed mode

 Master Mode
 16KHz
 16 bits
 2.048MHz clock

The LE920 modules have the following possible configurations:

Normal mode (factory default)

 Master Mode
 8KHz
 16 bits
 2.048MHz clock

High Speed mode

 Master Mode
 16KHz
 16 bits
 4.096MHz clock
Parameter Description Min Typical Max Units
t(sync) PCM_SYNC cycle time - 125 - us
t(syncha) PCM_SYNC asserted time - 488 - ns

t(syncd) PCM_SYNC de-asserted time - 124.5 - us

t(clk) PCM_CLOCK cycle time - 488 - ns

t(clkh) PCM_CLOCK high time - 244 - ns

t(clkl) PCM_CLOCK low time - 244 - ns

t(sync_offset) PCM_SYNC offset time to PCM_CLOCK falling - 122 - ns

t(sudin) PCM_RX setup time to PCM_CLOCK falling 60 - - ns

t(hdin) PCM_RX hold time after PCM_CLOCK falling 60 - - ns

t(pdout) Delay from PCM_CLOCK rising to PCM_TX valid - - 60 ns

Delay from PCM_CLOCK falling to PCM_TX

t(zdout) - - 60 ns
HIGH-Z

t(sync)

PCM_SYNC

t(synca) t(syncd)

Figure 5. Primary PCM_SYNC timing (Short sync, 2048kHz clock)

 t(clk)

PCM_CLOCK

t(clkh) t(clkl)

t(susync)

t(hsync)

PCM_SYNC

t(sudin) t(hdin)

PCM_RX MSB LSB

Figure 6. External codec to LE910 timing

t(clk)

PCM_CLOCK

t(clkh) t(clkl)

t(susync)

t(hsync)

PCM_SYNC

t(pdout) t(pdout) t(zdout)

PCM_TX MSB LSB

Figure 7. LE910 to External codec timing

 The next chapters show how to configure an external codec connected to the Module.
All the following setting examples are performed using the hardware configuration shown in

fig. 2.

I2C bus is used to configure the MAX9867 Codec1 [2].

The DVI bus provides the voice connection between the two devices.

fig. 2: Telit Module/Codec Connections

NOTE: The CODEC Example is applicable only to the High Speed mode
 Master Mode
 16KHz
 16 bits
 2.048MHz clock

1
The following examples use the MAX9867 Codec, see chapter 4.2 for a schematic reference design. In general, the user
can use any codec compliant with the technical requirements of the Telit’s modules.
The module has the role of master. In this case, the WAO and CLK signals are generated by
the module. The WAO signal defines the frame of the audio channel.

The following part is showing the commands necessary to set the DVI and the codec

Configure the DVI

DVI bus
AT#DVICFG=1,1,2,1,2
OK
1 High Speed Mode
1 decoder pad enabled
2 decoder format Linear
1 encoder pad enabled
2 encoder format Linear

Set the Module in Master Mode

DVI bus
AT#DVI=1,2,1
OK
1 enable DVI interface
2 use DVI port 2 (mandatory)
1 set the module as Master (factory setting)

Configure the codec in Slave , PCM, Burst (I2S) Mode

I2C bus
AT#I2CWR=X,Y,30,4,19
>0010900004000000300000000B0B3414C00000

OK
X GPIO number used as SDA, refer to [3]
Y GPIO number used as SCL, refer to [3]
30 Device address on I2C, refer to [2]
4 Register address from which start the writing, refer to [2]
19 number of bytes to write
>00101000…..refer to [2]

AT#I2CWR=X,Y,30,17,1
>8A
OK
X GPIO number used as SDA, refer to [3]
Y GPIO number used as SCL, refer to [3]
30 Device address on I2C, refer to [2]
17 Register address where write data, refer to [2]
1 number of bytes to write
>8A, refer to [2]
 The CODEC configuration is described in the following table (refer to the MAX9867
datasheet for the details):
Register Value Value
Register Name Description
address (Hex) (Bin)
0x04 Interrupt Enable 0 0 Disabled

MCLK is between 10MHz and 20MHz (12.288MHz in our example);

Frequency: Normal mode
0x05 System Clock 10 10000 The frequency of LRCLK is set by the NI divider bits.
Due to the fact the COD is Slave, it expects an LRCLK as specified by the
divide ratio

0x06 Audio Clock High 20

NI=0x2000 --> 16KHz
0x07 Audio Clock Low 0 0

MAS=0 : The MAX9867 operates in slave mode with LRCLK and BCLK
configured as inputs.
WCI ignored because TDM=1
BCI=0 : SDIN is latched into the part on the rising edge of BCLK. SDOUT
transitions after the rising edge of BCLK as determined by SDODLY*.
DLY ignored because TDM=1
HIZOFF=0 : SDOUT goes to a high-impedance state after all data bits have
0x08 Interface mode 1a 4 100 been transferred out of the MAX9867, allowing SDOUT to be shared by other
devices.
TDM=1 : LRCLK is a framing pulse that transitions polarity to indicate the
start of a frame of audio data consisting of multiple channels. When
operating in TDM mode, the left channel is output immediately following the
frame sync pulse. If rightchannel data is being transmitted, the 2nd channel
of data immediately follows the 1st channel data.

LVOLFIX=0 :
0x09 Interface mode 1b 0 0 DMONO=0 : Stereo data input on SDIN is processed separately.
BSEL=0 : No effect becasue in Slave Mode

MODE=0 : 0 = IIR Voice Filters

AVFLT = 0x3 : Filter Eliptical, Sample Rate 8KHz, HighPass Corner Freq
0x0A Codec Filters 33 110011 256Hz, 217Hz Notch active.
DVFLT= 0x3 : Filter Eliptical, Sample Rate 8KHz, HighPass Corner Freq
256Hz, 217Hz Notch Active.

DSTS=0 : 00 = No sidetone is selected.

0x0B DAC Gain/Sidetone 0 0
DVST=0 : Disabled

DACM=0 : NO Mute
0x0C DAC Level 0 0 DACG=0 : 0dB
DACA=0 : 0dB Gain

AVL=0x3 : 0dB Gain

0x0D ADC Level 33 110011
AVR=0x3 : 0dB Gain

LILM=0 : Line input is connected to the headphone amplifiers.

0x0E Left Line Input Level 0C 1100
LIRM=0 : Line input is connected to the headphone amplifiers.

LIGL = 0xC : 0dB Gain

0x0F Right Line Input Level 0C 1100
LIGR = 0xC : 0dB Gain
 VOLLM=0 : Audio playback is unmuted.
0x10 Left Volume Control 9 1001
VOLL=0x9 : 0dB Gain

VOLRM=0 : Audio playback is unmuted.

0x11 Rigth Volume Control 9 1001
VOLR= 0x9 : 0dB Gain

PALEN=0x01 : PreAmplifier Gain=0dB

0x12 Left Mic Gain 24 100100
PGAML=0x4 : Gain =+16dB

PALEN=0x01 : PreAmplifier Gain=0dB

0x13 Rigth Mic Gain 24 100100
PGAML=0x4 : Gain =+16dB

MXNL= 01 = Left analog microphone

MXNR= 00 = No Input selected
AUXCAP=0 : Update AUX with the voltage at JACKSNS/AUX.
0x14 ADC Input 40 1000000
AUXGAIN=0 : Normal operation
AUXCAL=0 : Normal operation
AUXEN=0 : Use JACKSNS/AUX for jack detection.

MICCLK=0 : PCLK/8
0x15 Microphone 0 0 DIGMICL=0 and DIGMICR=0 : Left ADC input= ADC input mixer, Right ADC
Input=ADC input mixer.

DSLEW=0 : Digital volume changes are slewed over 10ms.

VSEN*=1 : Volume changes occur in one step.
ZDEN*=1 : Line-input volume changes occur immediately.
0x16 Mode 60 1100000 JDETEN=0 : Enables pullups on LOUTP and JACKSNS/AUX to detect jack
insertion. LSNS and JKSNS are valid. LOUTP detection is only valid in
differential and capacitorless output modes.
HPMODE=0 : Stereo differential (clickless)

SHDN*=1 : Places the device in low-power shutdown mode.

LNLEN=0 : Left-Line Input disabled
LNREN=0 : Rigth-Line Input disabled
DALEN=1 : Enables the left DAC and automatically enables the left and right
0x17 System Shutdown 8A 10001010
headphone amplifiers.
DAREN=0 : Right DAC disabled
ADLEN=1 : Left ADC Enabled
ADREN=0 : Right ADC disabled
This chapter provides a short description of the standard I2S bus. This standard suitably modified is used by
the DVI interface implemented on the Telit’s modules.

The standard I2S is an electrical serial bus designed for connecting digital audio devices. This popular serial
bus has been developed by Philips® in 1986 as a 3-wire bus for interfacing to audio chips such as codecs. It is
a simple data interface, without any form of address or device selection.

Refer to fig. 3: the I2S design handles audio data separately from clock signals. On an I2S bus, there is only
one bus master and one transmitter.

In high-quality audio applications involving a Codec, the Codec is typically the master so that it has precise
control over the I2S bus clock.

An I2S bus design consists of the following serial bus lines:

 SD: Serial Data

 WS: Word Select
 Serial Clock: SCK

The I2S bus carries two channels (left and right) 8 bit long, which are typically used to carry stereo audio data
streams. The data alternates between left and right channels, as controlled by the word select signal driven by
the bus master.

clock SCK

word select WS

data SD

clock SCK

word select WS

data SD

fig. 3: I2S bus configurations

A schematic example of an interface between the Telit’s modules and the MAX9867 CODEC could be the
following:

fig. 4: Schematic for Reference Design