•4)2YUNDl\I HY62256A Series

32K x 8~bit CMOS SRAM

DESCRIPTION

The HY62256A is a high-speed, low power and 32,768 x 8-bits CMOS static RAM fabricated using Hyundai's high
performance twin tub CMOS process technology. This high rełiability process coupled with innovative circuit
design techniques, yields maximum access time of 55ns. The HY62256A has a data retention mocie that
guarantees data to rernain valid at a minimum power supply voltage of 2 .0 volt. Using CMOS technology, supply
voltages from 2.0 to 5.5 volt have little effect on supply current in data retention mode. Reducing the suppty voltage
to minimize current drain is unnecessary with the HY62256A Series.

FEATURES PIN CONNECTION

At4 1 A14
• High speed -55170/851100ns (max.) A12 2 A12
• Low power consumption A7 3 A7
/ł6 4 M
- Operating : 150mW (typ.) /ł6 s 145
A4
- Standby (CMOS) : 5µw (typ.) M e 1'J
1(J 7 A2
• Single 5V:t;10% poWer supply A2 8 At
A1 9 /łlJ
• Battery backup (ULL-part) NJ 10 I01
- 2.0V (mln.) data retention I01 11 Kl2
• Fully static operatłon a 12 ~
~ 13
- No clock or refresh requlred \ISS 14
• TTL compatible inputs and outputs Pm'
• Tri-state output ~ ~ o
l
ł
ł,.,"
1

~
t
• Standard pin conflguratlon
- 28 pin 800 mil PDIP
- 28 pin 330 mil SOP
- 28 pin 8x13.4 mm TSOP-1
*

~~-:::=-:=""~~~-
'!SCfY
Kl ~
o

TSOP-ł~
o I
PIN DESCRIPTION BLOCK DIAGRAM

NJ vet:,
vss
Pin Name Pin Functlon
MEMORY
OECOOER
CS Chip Select AMAY
512x512
WE Write Enable
A14
OE Output Enabłe
AO-A14 Address lnputs
<>:--
1/01-1/08 Data tnput/Output
K>1
...
Vcc Power(+5V)
l/08
.
o-:-
K)OATA

Vss Ground

CONTROL
LOGIC

-
Thla doci.ment is a general product descripllon and is subject to change without notice. Hyundai Electronics does not assume any
i.ponsiblllty for use of clrcultll cleseribed. No Datent llcences are lmplied.
1DC01-11-MAY95
4675088 0006053 31T „ 35
4YU•DAI ' HY62256A Series

ABSOLUTE MAXIMUM RATINGSl1l

SYMBOL PARAMETER RATING UNIT

VCC VIN. VOUT Power Sunntv ln-·.tin•.;...„ Volłane -0.5 to 7.0 V
TA o .; .
... r; ,.tuut Oto 70 ·c·
TBIAS TemDentture Under Bias -10to 125 ·c
TSTG StoraaeT ture „. -65to 150 ·c
PD Power Oilł.lł.iftAtion
. .
1.0 w
IOUT Data~ Current 50 mA
TSOLDER LeadS .... .T ,-ture & Time 260•10 ·c •sec
Note: . . .. . . .·
1. Stresses greeter than those liated under ABSOLUTE MAXIMUM RATINGS may cause permanent damage
to the device. This il atreas rating on!y and·functional operation of the devi~ ·at these Or any other condi-
tions above those indlcated in theoperational ofthls apecification ia not implied. Exposure to absolute
maximum rating conditiona for extended period may affect reliability.

RECOMMENDED OC OPERATING CONDłTIONS

(TA= o·c to 10°c)

SYMBOL PARAMETER MIN. TYP. MAX. UNIT
Vcc Power SuDDlv Voltaae 4.5 5.0 5.5 V
VIH lnout Hiah Voltaae 2.2 - Vcc+0.5 V
VIL lnDUt Low Voltaae -0.511> - 0.8 V
Note: *
1. Vll = -3.0V for pulse width less than 50na

TRUTHTABLE

MODE 110 OPERATION CS W!' 'DE

Standbv Hiah-Z H X X
Outnut Disabled Hlah-Z L H H
Read Data Out L H L
Write ·O.ta in L L X
Note:
1.H=VIH, L=VIL, X=Don't Cere

36 „ 4675088 0006054 256 „ 1DCOM1-MAY95

etaYUIDl\I HY62256A Series

DC CHARACTERISTICS

(TA: 0°C to 70°C, Vcc: SV± 10%, unless otherwise specified.)

ILO Output Leakage CUrrent Vss s VOOT s Vcc, -1 1 µA

lee Operating Power Supply B:Vll 30 50 mA

ICC1 Average Operating ~VIL 40 70 mA

ISB TTL Standby Current CS•VtH V..-V1H or VIL 0.4 2 mA

ISB1 CMOS Standby Current B <?: Vcc-0.2V

(CMOS lnputs)
VrH <!: Vcc-0.2V or
v-.so.2V LL 1 25 µA

4
Note:
1. Typical values are at Vcc=5.0V, TA:25°C

~~~~~~~~~

1DC01-11-MAY9I
„ 4675088 0006055 192 „
~~~~~~~~~

37
efGYUIDAI HY62256A Seri•s

AC CHARACTERISTICS

(TA=O"C to ro•c, Vcc=5V :t10%, unless otherwise note<t)

•55 -70 . -85 ·10
# SYMBOL PARAMETER UNIT
•N. MAX. MIN. MAX. MIN. MAX. MIN. MAX.

READCYCLE
1 tRC Read Cvcle Time 55 -,,
70 ~ '.
. 85 - ' 100 - ns
2 tAA Address Access Time - 55 . 70 . 85 - 100 ns
3 tAcs ChiD Select Access Time - 55 - 70 - 85 - 100 ns
4 toe Qutnut Enable to Outout Valid - 30 - 35 - 45 - 50 ns
5 tcLZ ChiD Select to Low -z Outnut 5 - 5 - 5 - 5 - ns
6 tOLZ Outmrt Enable to Low-Z Outnut 5 - 5 - 5 - 5 - ns
7 teHZ Chio Disable to Hiah -Z Outout o 20 o 30 o 30 o 35 na
8 toHZ Qutnuł Disable to Hiah -z Outnut o 20 o 30 o 30 o 35 ns
9 tOH Outout Hold from Address Chanae 5 - 5 - 5 - 5 - ns
WRITECYCLE
10 twe Write Cvcle Time 55 - 70 . 85 - 100 - ns
11 tcw Chio Select to End of Write 50 - 65 - 75 - 80 - na
12 tAW Address Valid to End of Write 50 - 65 - 75 - 80 - ns
13 tAS Address Set-uo Time o -
.
o - o - o - na
14 twP Write Pluse Wiclth 40 50 - 60 - 70 - ns
15 twR Write Recoverv Time
*
o - o - o - o - na
16 twHz Write to Hiah·Z Outout o 20 o 30 o 30 o '35 na
17 tow Data to Write Time OverlaD 25 - 35 . 40 - 40 - ns
18 łDH Data Hold from Write Time o - o - o - o - ns
19 tow Outout ActiVe from End of Write 5 - 5 - 5 - 5 . ns

---~~~~~~~
„ 4675088 0006056 029 „ 1DC01-11-MAYH
~YUIDAI HY62256A Serles

A.C TEST CONDITIONS

{TA=0°C to 70°C, Vcc=5V :t: 10%, unless otherwise specified.)

PARAMETER I SPEED VALUE

lnout Pulse Level 0.8Vto 2.4V
lnnut Rise and Fall Time 5na
lnout and Outnut Timina Reference levels 1.5V

Outputload
I 70/851100na CL=100nF + 1TTL Load
I 55ns CL= SOoF + 1TTL Load

A.C TEST LOADS

TTL

*
NOTE:
1. lncluding jig and scope capacitance.

CAPACITANCE

{TA„25°C, r- 1MHz)
SYMBOL PARAMETER CONDITION MAX. UNIT
CIN lnout Caoacitance VIH=OV 6 DF
C110 lnout/OutDut Caoacitance V11o=OV 8 DF
Note:
1. This parameter is sampled and not 100% tested.

~~~~~~~~~

1DC01-11-MAY95
„ 4b75088 0006057 Tb5 „ 31
-GGYU•DAI HY62256A Series

TIMING DIAGRAM

READ CYCLE 1

Note (READ CYCLE):

1. tcHZ and toHZ are defined as the time at which the outputs achieve the open circuit conditions and are not
referenced to output voltage levels.
2. At any given temperature and voltage condition, łcHZ max. is less than tcLZ min. both for a given device and
from device to device.
3. WE is high for read cycle. *

READ CYCLE 2

FIC

No~READ CYCLE):
1. WE is high for read cycle.
2. Device is continuously selected CS=VIL
3. OE=V1L.

..,..,......----- • 4675088 0006058 9T1 • 1DC01-11-MAY95

~YUNDl\I HY62256A Series

WRITE CYCLE I (OE Clocked )

J//JJaf ~w YXll/fl!/llJ//!////
I :,..__- - - - - - -- --·-·---1
I ! ON I

" §111!$/dz;;x 1;;111!ljJ/l!Jlli//J/JT//

1 I i
~ T'\ I i j
~ .
I I

m~M~&_.__~~~~f.~~-~~~-
i
IWA

ON j Dł
:,._--------.I.------

tOHZ

*
WRITE CYCLE 2 (OE Low Fiixcd)

--~ i----- --------------~-----------------==l ~----

~w
------- ··- -+-
' IWR ~

//!//jl//li!)/ZA!- - - - --------·-··-·li!////(Jl///J///Jfll!JJI
'CN

~~"'-'-!ts4''...__-_-_-_-_~
_·tNP==----_·-·-_------- ---'-/.
'ON . . - - : ___ Qi_ _ _;

DalaVelid

I ON
"---
------- ·

-DC--_- -M-AY-- - - -
1 01 11 95
4675088 0006059 838 - -----
41
efaYUIDl\I HY62256A Series

Note (WRITE CYCLE):

1. A write occurs dllri~he overłap of a low CS and a low WE. A write begins at the latest transition among
CS going low, and WE going low: A write ends at the earlist transition among CS going high WE going
high. fwp is measured from the ~ning of write to the end of write.
2. tcw is measured from the later of CS going low to end of write.
3. I.As is measL1red from the address va lid to the beginning of write.
4. twR is rneasured from the end of write to the address change. twR applied in case a write ends as CS, or
W!.iloing high.
5. lf OE and WE are in the read mode duńng this period, the 110 pins are in the output low-Z state, inputs of
o~site phase of the output must not be applied because bus contention can occur.
6. lf C~ goes low simultaneously with WE going low or after WE going low, the outputs remain in high imped-
ance state.
7. DouT is the same phase of lastest written data in this write cycle.
8. DouT is the read data of the new address.

42 „ 4675088 0006060 55T „ 10C01-11-MAY95

~YUIDl\I HY62256A Series

DATA RETENTION CHARACTERISTICS

(TA:0°C to 70°C)
SYMBOL PARAMETER TEST CONDITION POWER MIN. TYP. MAX UNIT
VDR VCC for Data Retention CS<!:: vcc-0.2V, VSSSVIN:5 Vcc 2.0 - - V
ICCDR Data Retention Current vcc=3.0V, L - 1 50 uA
CS ~ Vcc-0.2V
LL
- 1 1sc2> µA
Vss :5 V1N ~ Vcc
łCDR Chip Disable to See Data Retention Timing Diagram o - - ns
Data Retention Time
łR Orieratina Recoverv Time tRd31 - - ns
Notes :
1. Typical values are at the condition of TA=25°C.
2. 3µA max. at TA=0°C to 40°C
3. tRc is read cycle time.

DATA RETENTION TIMING DIAGRAM

DATA~MOOE

vcc - - - - - - .

4!N - - - - - - - - - - -

22'1 - - - - -
VOR --- --

\ISS ----- -- -- - - - - -- - -- -- - - - --------- - - -- -----

1DC01-11-MAY95
„ 4675088 0006061 496 „ 43
-taYUIDl\I HY62256A Series

PACKAGE INFORMATION

600 mil 28 pin D•al In-line Package(P)

o o
o.eoo esc ----i
(15.Kł .I
o. II

0.&30(13.482) I
I

-l!S.R:il

*
330mil 28 pin SmaD Oadine Packa&e (J)

lNT: INCH(mn) -M-

~~~~~-· „ 4675088 0006062 322 „ ~~~~~~~-

1DC01-11-MAY95
~YUllDAI HY62256A Series

28 pin Plastic: Tbio Small Out Line Pac:bge(Tl)

., '----~~----li
~
r - D.:4e!l{11.l!) Ij
'
o.4«X11.7) I
I• 0.53!K13.$

:. o.318(8.11
I,__ _ 0.311(7.ei
·I · ~~
,...:O::,:
_ _ _ _ _!_--ł-o.~ .087)

Jj (....____ _ _ _) (\_ ~ g:~.ast

-1 1 • 0.027(0.7)
0.012!0.~
TD.IQ!(0.2,)
0.004(0.1) r-
--1 O.O'ł21Q.fi6 BSC1 ,-

*
28 pin Tbill Small Oat Line Package(RI)

0.()40(1 .018)

0.291 .51

0.4!!!!tl1.9)
11·
I
0.4«X11 .7)
0.631W13.8)
I
0.62((13.2)

Jj (---------1)(\_
T O.(l)!!f).2)
•o.o:mo.n
--11 0.012tQ.31 0.004(0.1)

------------~------„
1DC01-11-MAY95
4b75088 000b0b3 2b9 „
~YUIDAI HY6264A-1 Series

ORDERING INFORMATION

PART NO. SPEED POWER PACKAGE

HY62256AP 55170/85/1 oo PDIP

HY62256ALP 55170/85/1 oo L-part PDIP

HY62256ALLP 55170/8511 oo LL-part PDIP

HY62256AJ 55/70/85/1 oo SOP

HY62256ALJ 55/70/85/1 oo L-Part SOP

HY62256ALLJ 55170/85/1 oo LL-Part SOP

HY62256AT1 55/70/85/1 oo TSOP-1 Standard

HY62256ALT1 55170/85/1 oo L-Part TSOP-1 Standard

HY62256ALLT1 55/70/85/1 oo LL-Part TSOP-1 Standard

HY62256AR1 55/70/85/1 oo TSOP-1 Reversed

HY62256ALR1 55/70/85/1 oo L-Part TSOP-1 Reversed

HY62256ALLR1 55170/85/1 oo LL-Part TSOP-1 Reversed

-------
46
„ 4675088 0006064 1T5 „ 10C01-11-MAY95