Unit 4_Part 1

Basic Knowledge
A program must be brought (from disk) into memory and
placed within a process for it to be run
A program can be written in machine language, assembly
language, or high-level language.
Main memory and registers are the only storage entities that a
CPU can access directly
The CPU fetches instructions from main memory according to
the value of the program counter.
Typical instruction execution cycle – fetch instruction from
memory, decode the instruction, operand fetch, possible
storage of result in memory.

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 Basic Knowledge (Cont.)
Memory unit only sees a stream of one of the following:
address + read requests (e.g., load memory location
20010 into register number 8)
address + data and write requests (e.g., store content
of register 6 into memory location 1090)
Memory unit does not know how these addresses were
generated
Register access can be done in one CPU clock (or less)

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 Basic Knowledge (Cont.)

Completing a memory access may take many cycles of

the CPU clock. In such a case the processor needs to
stall since it does not have the data required to complete
the instruction it is executing.
Cache sits between main memory and CPU registers to
deal with the “stall” issue.
Protection of memory is required to ensure correct
operation:
User process cannot access OS memory
One user process cannot access the memory of
another user process.

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Bare Machine & Resident Monitor

Basic Bare Machine

The simplest variety of organization of main memory is Bare Machine
wherever the complete memory is given to the designer, there's no
partition within the memory.
Memory organization mistreatment in Bare machine has the
subsequent options
No Protection.
No Overhead.
Simplest variety of memory management.
User have complete control and operating system has none.
This is used by hardware diagnostics, by the system boot code, real
time/dedicated system, maximum flexibility to user and minimum
hardware cost.
No operating system service. It means OS manage nothing instead of
its entire address space is given to the program and all the managing
left to it.

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Bare Machine & Resident Monitor

Resident Monitor
In resident monitor the memory is partitioned off,
divided into 2 partitions. one among the partition is
occupied by the computer program or the software
package and therefore the second partition contains
the user knowledge or the user program.

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 Memory Protection
A base register (holding the smallest legal physical address of
a program in memory) and a limit register (specifies the size
of the program) define the boundary of a program in memory.
CPU must check that every memory access generated in user
mode is between the base and base + limit for that user

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Hardware Address Protection

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 Address Binding
A program residing on the disk needs to be brought into memory
in order to execute. Such a program is usually stored as a binary
executable file and is kept in an input queue.
In general, we do not know a priori where the program is going to
reside in memory. Therefore, it is convenient to assume that the
first physical address of a program always starts at location 0000.
Without some hardware or software support, program must be
loaded into address 0000
It is impractical to have first physical address of user process to
always start at location 0000.
Most (all) computer systems provide hardware and/or software
support for memory management,

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 Address Binding (Cont.)
In general, addresses are represented in different ways at
different stages of a program’s life
Addresses in the source program are generally symbolic
 i.e., variable “count”
A compiler typically binds these symbolic addresses to
relocatable addresses
 i.e., “14 bytes from beginning of this module”
Linker and loader will bind relocatable addresses to
absolute addresses
 i.e., 74014
Each binding maps one address space to another
address space

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Address Binding (Cont.)

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 Binding of Instructions and Data to Memory

Address binding of instructions and data to memory

addresses can happen at three different points in time:

Compile time: If memory location known a priori, absolute code

can be generated; must recompile code if starting location
changes
Load time: If memory location is not known at compile time and
no hardware support is available, relocatable code must be
generated
Execution time: Binding delayed until run time if the process can
be moved during its execution from one memory segment to
another
Need hardware support for address maps (e.g., base and limit
registers)

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Multistep Processing of a User Program

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Logical vs. Physical Address Space
The concept of a logical address space that is bound to a separate
physical address space is central to proper memory management
Logical address – generated by the CPU.
Physical address – address seen by the memory unit
Logical and physical addresses are:
The same in compile-time and load-time address-binding schemes;
They differ in execution-time address-binding scheme. In that case
the logical address is referred to as virtual address.
We use Logical address and virtual address interchangeably
Logical address space is the set of all logical addresses generated by
a program
Physical address space is the set of all physical addresses
corresponding to a given logical address space.

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Memory-Management Unit (MMU)

Hardware device that at run time maps virtual addresses to

physical address

The user program deals with logical addresses; it never sees

the real physical addresses
Execution-time binding occurs when reference is made to
location in memory
Logical address bound to physical addresses

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Dynamic relocation using a relocation register

To start, consider simple scheme where the value in the base

register is added to every address generated by a user process
at the time it is sent to memory
Base register now called relocation register
MS-DOS on Intel 80x86 used 4 relocation registers

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 Dynamic Loading
Until now we assumed that the entire program and data
has to be in main memory to execute
Dynamic loading allows a routine (module) to be loaded
into memory only when it is called (used)
Results in better memory-space utilization; unused routine
is never loaded
All routines kept on disk in relocatable load format
Useful when large amounts of code are needed to handle
infrequently occurring cases (e.g., exception handling)
No special support from the operating system is required
It is the responsibility of the users to design their
programs to take advantage of such a method
OS can help by providing libraries to implement
dynamic loading

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 Dynamic Linking
Dynamically linked libraries – system libraries that are linked
to user programs when the programs are run.
Similar to dynamic loading. But, linking rather than loading
is postponed until execution time
Small piece of code, stub, used to locate the appropriate
memory-resident library routine
Stub replaces itself with the address of the routine, and
executes the routine
Operating system checks if routine is in processes’ memory
address
If not in address space, add to address space
Dynamic linking is particularly useful for libraries
System also known as shared libraries

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 Overlays

Keep in memory only those instructions and data

that are needed at any given time.
Needed when process is larger than amount of
memory allocated to it.
Implemented by user, no special support needed
from operating system, programming design of
overlay structure is complex

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Overlays for a Two-Pass Assembler

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 Swapping

A process can be swapped temporarily out of memory to a backing store,

and then brought back into memory for continued execution

Backing store – fast disk large enough to accommodate copies of all

memory images for all users; must provide direct access to these memory
images

Roll out, roll in – swapping variant used for priority-based scheduling

algorithms; lower-priority process is swapped out so higher-priority process
can be loaded and executed

Major part of swap time is transfer time; total transfer time is directly
proportional to the amount of memory swapped

Modified versions of swapping are found on many systems (i.e., UNIX,

Linux, and Windows)
System maintains a ready queue of ready-to-run processes which have
memory images on disk

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Schematic View of Swapping

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 Contiguous Allocation
Main memory must support both OS and user processes
Limited resource -- must allocate efficiently
Contiguous allocation is one early method
Main memory is usually divided into two partitions:
Resident operating system, usually held in low memory
with interrupt vector
User processes are held in high memory
Each process contained in single contiguous section of
memory

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 Contiguous Allocation (Cont.)
Relocation registers used to protect user processes from each
other, and from changing operating-system code and data
Base register contains value of smallest physical address
Limit register contains range of logical addresses – each
logical address must be less than the limit register
MMU maps logical address dynamically
Can then allow actions such as kernel code being
transient – comes and goes as needed. Thus, kernel can
change size dynamically.

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Hardware Support for Relocation and Limit Registers

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 Memory Management Techniques

Although the following simple/basic memory management

techniques are not used in modern OSs, they lay the ground for a
later proper discussion of virtual memory:

Fixed/Static Partitioning
Variable/Dynamic Partitioning
Simple/Basic Paging
Simple/Basic Segmentation

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Fixed Partitioning Multiprogramming

Partition main memory

into a set of non-
overlapping memory
regions called
partitions.
Fixed partitions can be
of equal or unequal
sizes.
Leftover space in
partition, after program
assignment, is called
internal fragmentation.

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 Placement Algorithm with Partitions

Equal-size partitions:
If there is an available partition, a process can be
loaded into that partition –
because all partitions are of equal size, it does
not matter which partition is used.
If all partitions are occupied by blocked processes,
choose one process to swap out to make room for
the new process.

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Placement Algorithm with Partitions
Unequal-size partitions, use of
multiple queues:
assign each process to the
smallest partition within
which it will fit.
a queue exists for each
partition size.
tries to minimize internal
fragmentation.
problem: some queues
might be empty while some
might be loaded.

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 Placement Algorithm with Partitions

Unequal-size
partitions, use of a
single queue:
when its time to load a process
into memory, the smallest
available partition that will hold
the process is selected.
increases the level of
multiprogramming at the
expense of internal
fragmentation.

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 Dynamics of Fixed Partitioning

Any process whose size is less than or equal to a

partition size can be loaded into the partition.
If all partitions are occupied, the OS can swap a process
out of a partition.
A program may be too large to fit in a partition. The
programmer must design the program with overlays.

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 Comments on Fixed Partitioning

Main memory use is inefficient. Any program, no matter

how small, occupies an entire partition. This can cause
internal fragmentation.
Unequal-size partitions lessens these problems but they
still remain ...
Equal-size partitions was used in early IBM’s OS/MFT
(Multiprogramming with a Fixed number of Tasks).

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Multiple-partition allocation(Variable)
Multiprogramming
Variable-partition -- sized to a given process’ needs.
Hole – block of available memory; holes of various size are
scattered throughout memory
When a process arrives, it is allocated memory from a hole large
enough to accommodate it
Process exiting frees its partition, adjacent free partitions
combined
Operating system maintains information about:
a) allocated partitions b) free partitions (holes)

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Dynamic Storage-Allocation Problem

How to satisfy a request of size n from a list of free holes?

First-fit: Allocate the first hole that is big enough

Best-fit: Allocate the smallest hole that is big enough;

must search entire list, unless the list is ordered by size.
 Produces the smallest leftover hole

Worst-fit: Allocate the largest hole; must also search

entire list, unless the list is ordered by size
 Produces the largest leftover hole
Next-fit: Next fit is a modified version of first fit. It begins
as first fit to find a free partition. When called next time it
starts searching from where it left off, not from the
beginning.
First-fit and best-fit are better than worst-fit in terms of speed
and storage utilization

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 Dynamic Memory Management
Operating system needs to keep track of dynamically allocated
regions and of the remaining free space.
The number and size of free and occupied regions varies over time
Processes may need to expand the memory regions allocated to
them
There are two main software approaches to keeping track of a linear
memory space:-
fixed sized bitmaps
dynamic linked lists.

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Dynamic Storage-Allocation Problem

Question 1
Consider the following heap (figure) in which blank regions are
not in use and hatched region are in use.

The sequence of requests for blocks of sizes 300,25,125, 50 can

be satisfied if we use
a) either first fit or best fit policy (any one)
b) first fit but not best fit policy
c) best fit but not first fit policy
d) None of the above

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 Dynamic Storage-Allocation Problem

In first fit, block request will be satisfied from the first free block that fits it.
So, request for 300 will be satisfied by 350 size block reducing the free size to
50.
Request for 25, satisfied by 150 size block, reducing it to 125.
Request for 125 satisfied by 125 size block.
And request for 50 satisfied by the 50 size block.
So, all requests can be satisfied.
In best fit strategy, a block request is satisfied by the smallest block in that can fit it.
So, request for 300 will be satisfied by 350 size block reducing the free size to
50.
Request for 25, satisfied by 50 size block as its the smallest size that fits 25,
reducing it to 25.
Request for 125, satisfied by 150 size block, reducing it to 25.
Now, request for 50 cannot be satisfied as the two 25 size blocks are not
contiguous.
So, answer (b).

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 Dynamic Storage-Allocation Problem

Question 2

A 1000 Kbyte memory is managed using variable partitions but no

compaction. It currently has two partitions of sizes 200 Kbyte and 260
Kbyte respectively. The smallest allocation request in Kbyte that could
be denied is for
a) 151
b) 181
c) 231
d) 541

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 Dynamic Storage-Allocation Problem
Since the total size of the memory is 1000KB, lets assume that the
partitioning for the current allocation is done in such a way that it will leave
minimum free space.

Partitioning the 1000kB as below will allow gaps of 180KB each and hence
a request of 181kB will not be met.

[180Kb−200kb−180kb−260kb−180kb].
The reasoning is more of an intuition rather than any formula.
So Answer is (B).

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 Fragmentation
As processes are loaded and removed from memory,
the free memory space is broken into little pieces. It
happens after sometimes that processes cannot be
allocated to memory blocks considering their small size
and memory blocks remains unused. This problem is
known as Fragmentation. Fragmentation is of two
types.
S.N. Fragmentation & Description
1 External fragmentation
Total memory space is enough to satisfy a request or to
reside a process in it, but it is not contiguous, so it cannot
be used.
2 Internal fragmentation
Memory block assigned to process is bigger. Some portion
of memory is left unused, as it cannot be used by another
process.

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 Fragmentation (Cont.)
The following diagram shows how fragmentation can cause waste of
memory and a compaction technique can be used to create more free
memory out of fragmented memory −

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 Fragmentation (Cont.)
External fragmentation can be reduced by compaction or
shuffle memory contents to place all free memory together
in one large block. To make compaction feasible,
relocation should be dynamic.
The internal fragmentation can be reduced by effectively
assigning the smallest partition but large enough for the
process.

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 Non-contiguous Allocation
Partition the a program into a number of small units, each
of which can reside in a different part of the memory.
Need hardware support.
Various methods to do the partitions:
Segmentation.
Paging
paged segmentation.

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 Segmentation
Memory-management scheme that supports user’s view of memory
A program is a collection of segments -- a logical unit such as:
main program
procedure
function
method
object
local variables, global variables
common block
stack
symbol table
arrays
Each segment can reside in different parts of memory. Way to
circumvent the contiguous allocation requirement.

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User’s View of a Program

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Two Dimensional Addresses

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Logical and Physical Memory

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 Segmentation Architecture

Logical address consists of a two tuple:

<segment-number, offset>
Need to map a two-dimensional logical addresses to a one-
dimensional physical address. Done via Segment table:
base – contains the starting physical address where the
segments reside in memory
limit – specifies the length of the segment
Segment table is kept in memory
Segment-table base register (STBR) points to the
segment table’s location in memory
Segment-table length register (STLR) indicates number
of segments used by a program;
segment number s is legal if s < STLR

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Segmentation Hardware

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Example of Segmentation

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 Paging
Physical address space of a process
can be non-contiguous.
Process is divided into fixed-size blocks,
each of which may reside in a different
part of physical memory.
Divide physical memory into fixed-sized
blocks called frames
Divide logical memory into blocks of
same size as frames called pages
Backing store, where the program is
permanently residing, is also split into
storage units (called blocks), which are
the same size as the frame and pages.
Physical memory allocated whenever
the latter is available
Avoids external fragmentation
Still have Internal fragmentation

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 Paging (Cont.)
Keep track of all free frames
To run a program of size N pages, need to find N free frames
and load program from backing store.
Set up a page table to translate logical to physical addresses
Page table is kept in memory.
Page-table base register (PTBR) points to the page table
Page-table length register (PTLR) indicates size of the
page table
Still have Internal fragmentation.

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 Address Translation Scheme
Assume the logical address space is 2m. (How is m bit
determined?)
Assume page size is 2n
Address generated by CPU is divided into:
Page number (p) – used as an index into a page table
which contains base address of each page in physical
memory. Size of p is “m – n”
Page offset (d) – combined with base address to define
the physical memory address that is sent to the memory
unit. Size of d is “n”.

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Paging Hardware

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Paging Model of Logical and Physical Memory

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 Paging Example
Assume m = 4 and n = 2 and 32-byte memory and 4-byte pages

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 Storage Units
4 bit = 1 Nibble
8 bit = 1 Byte
10
1024 byte = 1 KB = 2
1024 KB = 1 MB = 2 20
30
1024 MB = 1 GB = 2
40
1024 GB = 1 TB = 2

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Logical to physical address mapping
The technique of transforming logical address to physical
address with the help of page table is known as paging .
Paging is implemented on Hardware level, not in software level
Logical Address Space(LAS) will be divided into equal size of
pages

Page size is equal to frame size.

Physical Address Space (PAS) will be divided into equal

frames.

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 Problems on Paging
Question 1:

Consider a system which has logical address is 29 bits and

physical address is 23 bits. Page size = 4 kb, Memory is byte
addressable. The calculate

A) Number of frames

B) Number of pages

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Problems on Paging

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 Problems on Paging
Question 2

Consider a system which has logical address space is 128MB

and physical address is 24 bits. The physical address is divided
into 8 k frames.. Calculate

A) Size of a page

B) Number of pages

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Problems on Paging

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 Problems on Paging
Question 3
Consider a system which has logical address space is 256 MB
and physical address of 27 bits, physical address space is
divided in to 4 KB frame. Calculate the number of pages in LAS

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 Problems on Paging
Question 3
Consider a system which has logical address space is 256 MB,
Physical address is 27 bit and physical address space is divided
in to 4 KB frame. Calculate the number of pages in LAS

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 Internal Fragmentation
Calculating internal fragmentation
Page size = 2,048 bytes
Process size = 72,766 bytes
35 pages + 1,086 bytes
Internal fragmentation of 2,048 - 1,086 = 962 bytes
Worst case fragmentation = 1 frame – 1 byte
On average fragmentation = 1 / 2 frame size
So small frame sizes desirable?
But each page table entry takes memory to track
Page sizes growing over time
 Solaris supports two page sizes – 8 KB and 4 MB
By implementation process can only access its own memory

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Allocating Frames to a New Process

Before allocation After allocation

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 TLB -- Associative Memory
The hardware implementation of page table can be done by using
dedicated registers. But the usage of register for the page table is
satisfactory only if page table is small. If page table contain large
number of entries then we can use translation look-aside buffers
(TLBs), a special, small, fast look up hardware cache.
The TLB is associative and high speed memory – parallel search.
Page # Frame #

Each entry in TLB consists of two parts: a tag and a value.

When this memory is used, then an item is compared with all tags
simultaneously. If the item is found, then corresponding value is
returned.
Address translation (p, d)
If p is in associative register, get frame # out
Otherwise get frame # from page table in memory
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 TLB issues
TLB is typically small (64 to 1,024 entries)
On a TLB miss, the value of the (missed page-table and
frame-number), is loaded into the TLB for faster access
next time that address is used.
What if there is no free TLB entry? Replacement
policies must be considered
Some entries can be wired down for permanent fast
access
Some TLBs store address-space identifiers (ASIDs) in
each TLB entry – uniquely identifies each process to
provide address-space protection for that process
Otherwise need to flush TLB at every context switch

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Paging Hardware With TLB

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 Effective Access Time
Associative Lookup = (Epsilon) time unit
Can be < 10% of memory access time
Hit ratio =  (Alpha)
Hit ratio – percentage of times that a page number is found in
the associative registers(ratio related to number of associative
registers)
Miss ratio = 1-  (Alpha)
Effective Access Time (EAT)
TLB_hit_time := TLB_search_time + memory_access_time
TLB_miss_time := TLB_search_time + memory_access_time +
memory_access_time

EAT = hit_ratio * (TLB_hit_time) + (1- hit_ratio) * (TLB_miss_time)

EAT = (1 + )  + (2 + )(1 – )
=2+–
(This formula is valid only when there is single level paging and there are no
page faults)

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 Effective Access Time
Consider  = 20ns for TLB search and 100ns for memory access

if  = 80%:

 EAT = 0.80 x (100+20) + 0.20 x (200+20)

= (96+44) ns

=140 ns

Consider more realistic hit ratio of  = 99%

 EAT = 0.99 x (100+20) + 0.01 x (200+20)

– = (118.8 + 2.2) ns

– = 121 ns

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 Problems on Paging Hardware With TLB

Problem 1:
TLB lookup takes 5 nano sec.
Memory access time is 100 nano sec.
Hit ratio (probability to find page number in TLB) is 
▪ Suppose  = 80% (for example, TLB size = 16)
▪ Suppose  = 98% (for example, TLB size = 64)

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 Problems on Paging Hardware With TLB

Problem 1:
TLB lookup takes 5 nano sec.
Memory access time is 100 nano sec.
Hit ratio (probability to find page number in TLB) is 

Effective Access Time = (5+100)*  +( 5+100+100)*(1- )

Suppose  = 80% (for example, TLB size = 16)

EAT = 105*.8 + 205*.2 = 125 nano sec.

Suppose  = 98% (for example, TLB size = 64)

EAT = 105*.98 + 205*.02 = 107 nano sec.

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 Problems on Paging Hardware With TLB

Problem 2:
A paging scheme uses a Translation Look-aside Buffer (TLB). A TLB-
access takes 10 ns and a main memory access takes 50 ns. What is
the effective access time(in ns) if the TLB hit ratio is 90% and there is
no page-fault?
(A) 54
(B) 60
(C) 65
(D) 75

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 Problems on Paging Hardware With TLB

Problem 2:
A paging scheme uses a Translation Look-aside Buffer (TLB). A TLB-
access takes 10 ns and a main memory access takes 50 ns. What is
the effective access time(in ns) if the TLB hit ratio is 90% and there is
no page-fault?
(A) 54
(B) 60
(C) 65
(D) 75
Answer: (C)

Effective access time = hit ratio * time during hit + miss ratio * time
during miss
TLB time = 10ns, Memory time = 50ns, Hit Ratio= 90%
E.A.T. = (0.90)*(60)+0.10*110 =65

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 Problems on Paging Hardware With TLB
Problem 3:

Consider a paging hardware with a TLB. Assume that the

entire page table and all the pages are in the physical
memory. It takes 10 milliseconds to search the TLB and 80
milliseconds to access the physical memory. If the TLB hit
ratio is 0.6, the effective memory access time (in
milliseconds) is _________.

(A) 120
(B) 122
(C) 124
(D) 118

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 Problems on Paging Hardware With TLB
Problem 3:
First Calculate TLB hit time and TLB miss time
TLB_hit_time := TLB_search_time + memory_access_time

TLB_miss_time := TLB_search_time +
memory_access_time +
memory_access_time
As both page table and page are in physical memory
EAT = hit_ratio * (TLB_hit_time) + (1- hit_ratio) * (TLB_miss_time)
= 0.6*(10+80) + (1-0.6)*(10+2*80)
= 0.6 * (90) + 0.4 * (170)
= 122

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 Memory Protection
Memory protection implemented by associating protection bits
with each frame to indicate if “read-only “ or “read-write” access
is allowed
Can also add more bits to indicate “execute-only” and so on
Valid-invalid bit attached to each entry in the page table:
“valid” indicates that the associated page is in the process’
logical address space, and is thus is a legal page
“invalid” indicates that the page is not in the process’ logical
address space
Or use page-table length register (PTLR)
Any violations result in a trap to the kernel

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Valid (v) or Invalid (i) Bit In A Page Table

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 Page Table Entries

▪ Page table has page table entries where each page table entry
stores a frame number and optional status (like protection) bits.
Many of status bits used in the virtual memory system. The
most important thing in PTE is frame Number.
Page table entry has the following information –

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 Page Table Entries
1.Frame Number – It gives the frame number in which the current page you
are looking for is present. The number of bits required depends on the
number of frames.
Number of bits for frame = Size of physical memory/frame size
2.Present/Absent bit – Present or absent bit says whether a particular page
you are looking for is present or absent. In case if it is not present, that is
called Page Fault. It is set to 0 if the corresponding page is not in memory.
Used to control page fault by the operating system to support virtual
memory. Sometimes this bit is also known as valid/invalid bits.

3.Protection bit – Protection bit says that what kind of protection you want
on that page. So, these bit for the protection of the page frame (read, write
etc).

4.Referenced bit – Referenced bit will say whether this page has been
referred in the last clock cycle or not. It is set to 1 by hardware when the
page is accessed.

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 Page Table Entries

5. Caching enabled/disabled – Some times their is a need of

fresh data (i.e. input by the user) for execution .Let us say the
user is typing some information from the keyboard and your program
should run according to the input given by the user. In that case, the
information will come into the main memory. Therefore main
memory contains the latest information which is typed by the user.
Now if you try to put that page in the cache, that cache will show the
old information. So whenever user input is required, no need to go
for caching or many levels of the memory. The information present in
the closest level to the CPU and the information present in the
closest level to the user might be different. Hence their is a need of
information consistency, which means whatever information user has
given, CPU should be able to see it as first as possible. That is the
reason we want to disable caching. So, this bit enables or
disable caching of the page.

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 Page Table Entries

6. Modified bit – A modified bit is a flag (i.e 0 or 1) that

indicates whether an attribute needs to be updated. Such
situations usually occur when a bit in memory cache or virtual
memory page that has been changed by a processor but has not
been updated in the storage. Sometimes this modified bit is also
called as the Dirty bit.

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 Shared Pages
Shared code
One copy of read-only (reentrant) code shared among
processes (i.e., text editors, compilers, window systems)
Similar to multiple threads sharing the same process space
Also useful for inte-rprocess communication if sharing of
read-write pages is allowed
Private code and data
Each process keeps a separate copy of the code and data
The pages for the private code and data can appear
anywhere in the logical address space

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Shared Pages Example

85
 Structure of the Page Table
Memory structures for paging can get huge using straight-
forward methods
Consider a 32-bit logical address space
Page size of 4 KB (212)
Page table would have 1 million entries (232 / 212)
If each entry is 4 bytes -> Page table is of size 4 MB
 That amount of memory used to cost a lot.
 Do not want to allocate that contiguously in main
memory
What about a 64-bit logical address space?

86
Page Table for Large address space

Hierarchical Paging or Multilevel Pagging

Hashed Page Tables

Inverted Page Tables

87
Hierarchical (Multilevel) Page Tables
The need for multilevel paging arises when-
The size of page table is greater than the frame size.
As a result, the page table can not be stored in a single frame
in main memory.
Break up the logical address space into multiple page tables
A simple technique is a Multilevel page table as given below (two
level )

88
 Multilevel(Two) Paging Example
A logical address (on 32-bit machine with 12 bit page size) is divided
into:
a page number consisting of 20 bits
a page offset consisting of 12 bits

Since the page table is paged, the page number is further divided into:
a 10-bit page number
a 12-bit page offset

Thus, a logical address is as follows:

where p1 is an index into the outer page table, and p2 is the

displacement within the page of the inner page table Known as
forward-mapped page table

89
Multilevel Paging Working Principle
In multilevel paging,
The page table having size greater than the frame size is divided
into several parts.
The size of each part is same as frame size except possibly the last
part.
The pages of page table are then stored in different frames of the
main memory.
To keep track of the frames storing the pages of the divided page
table, another page table is maintained.
As a result, the hierarchy of page tables get generated.
Multilevel paging is done till the level is reached where the entire
page table can be stored in a single frame.

90
Address-Translation Scheme

91
 Problems on Multilevel Paging
Problem No. 1 (GATE Question)
Consider a system using multilevel paging scheme.
Logical Address Space = 4 GB
Physical Address Space = 256 MB
Frame size = 4 KB
Page Table entry =2B
Calculate how many levels of page table will be required?

92
 Problems on Multilevel Paging
Step-1 Number of Bits in Physical Address-
Size of main memory = Physical Address Space
= 256 MB
= 228 B
Thus, Number of bits in physical address = 28 bits

Step-2 Number of Frames in Main Memory-

Number of frames in main memory = Size of main memory / Frame size
= 256 MB / 4 KB
= 216 frames
Thus, Number of bits in frame number = 16 bits

93
 Problems on Multilevel Paging
Step-3 Number of Bits in Page Offset-
As Page size = 4 KB = 212 B
Or
Number of bits in page offset
= Number of bits in physical address – Number of bits in frame number
= 44 bits – 32 bits
= 12 bits
Thus, Number of bits in page offset = 12 bits
So, Physical address Space looks like-

94
 Problems on Multilevel Paging
Step -4 Number of Pages in a Process-
Number of pages the process is divided = Process size / Page size
= 4 GB / 4 KB
= 220 pages
Note:
A process consists of number of Pages, all the pages are available in
Logical address Space. So process size =Size of the Logical address
Space
Frame size =Page size, Hence Frame Size is also 4KB

95
 Problems on Multilevel Paging
Step -5 Calculate Inner Page Table Size-
Inner page table keeps track of the frames storing the pages of
process.
Inner Page table size
= Number of entries in inner page table x Page table entry size
= 220 x 2B
= 220 = 2 MB

96
 Problems on Multilevel Paging
Step -5 Calculate Inner Page Table Size-
Inner page table keeps track of the frames storing the pages of
process.
Inner Page table size
= Number of entries in inner page table x Page table entry size
= 220 x 2B
= 220 = 2 MB
Now, the observation is -
The size of inner page table is greater than the frame size
(i.e. 2 MB>4 KB)
Thus, inner page table can not be fitted in a single frame.
So, inner page table has to be divided into pages. And the
references of inner page table pages are stored in Outer Page table

97
 Problems on Multilevel Paging
Step- 6 Number of Pages of Inner Page Table-
Number of pages the inner page table is divided
= Inner page table size / Page size
= 2 MB / 4 KB
= 29 pages
Now, these 29 pages of inner page table are stored in different frames of
the main memory.
Step–7 Number of Page Table Entries in One Page of Inner Page
Table-
Number of page table entries in one page of inner page table
= Page size / Page table entry size
= 4 KB / 2B
= 210

98
 Problems on Multilevel Paging
Step – 8 Number of Bits Required to Search an Entry in One Page of
Inner Page Table-
One page of inner page table contains 210 entries.
Thus, Number of bits required to search a particular entry in one page of
inner page table = 10 bits
Step -9 Outer Page Table Size-
Outer page table is required to keep track of the frames storing the
pages of inner page table.
Outer Page table size
= Number of entries in outer page table x Page table entry size
= 29 x 2B
= 210 =1 KB

99
 Problems on Multilevel Paging
Now, the observation is -
The size of outer page table is same as frame size (4 KB).
Thus, outer page table can be stored in a single frame.
So, for given system, we will have two levels of page table.
Page Table Base Register (PTBR) will store the base address of the
outer page table.
Step – 10 Number of Bits Required to Search an Entry in Outer Page
Table-
Outer page table contains 211 entries. (20 bits-9 bits=11 bits)
Thus, Number of bits required to search a particular entry in outer page
table = 11 bits

100
 Problems on Multilevel Paging
The paging system will look like as shown below-

101
 Problems on Multilevel Paging
Problem No. 2 (GATE Question)
Consider a system using paging scheme where-
Logical Address Space = 4 GB
Physical Address Space = 16 TB
Page size = 4 KB

Calculate, how many levels of page table will be required.

102
 Problems on Multilevel Paging
Step-1 Number of Bits in Physical Address-
Size of main memory = Physical Address Space
= 16 TB
= 244 B
Thus, Number of bits in physical address = 44 bits

Step-2 Number of Frames in Main Memory-

Number of frames in main memory = Size of main memory / Frame size
= 16 TB / 4 KB
= 232 frames
Thus, Number of bits in frame number = 32 bits

103
 Problems on Multilevel Paging
Step-3 Number of Bits in Page Offset-
As Page size = 4 KB = 212 B
Or
Number of bits in page offset
= Number of bits in physical address – Number of bits in frame number
= 44 bits – 32 bits
= 12 bits
Thus, Number of bits in page offset = 12 bits
So, Physical address looks like-

104
 Problems on Multilevel Paging
Step -4 Number of Pages of Process-
Number of pages the process is divided = Process size / Page size
= 4 GB / 4 KB
= 220 pages
Step -5 Inner Page Table Size-
Inner page table keeps track of the frames storing the pages of
process.
Inner Page table size
= Number of entries in inner page table x Page table entry size
= Number of pages the process is divided x Number of bits in frame
number
= 220 x 32 bits
= 220 x 4 bytes
= 4 MB

105
 Problems on Multilevel Paging
Now, the observation is -
The size of inner page table is greater than the frame size (4 KB).
Thus, inner page table can not be stored in a single frame.
So, inner page table has to be divided into pages.

106
 Problems on Multilevel Paging
Step- 6 Number of Pages of Inner Page Table-
Number of pages the inner page table is divided
= Inner page table size / Page size
= 4 MB / 4 KB
= 210 pages
Now, these 210 pages of inner page table are stored in different frames of
the main memory.
Step–7 Number of Page Table Entries in One Page of Inner Page Table-
Number of page table entries in one page of inner page table
= Page size / Page table entry size
= Page size / Number of bits in frame number
= 4 KB / 32 bits
= 4 KB / 4 B
= 210

107
 Problems on Multilevel Paging
Step – 8 Number of Bits Required to Search an Entry in One Page of
Inner Page Table-
One page of inner page table contains 210 entries.
Thus, Number of bits required to search a particular entry in one page of
inner page table = 10 bits
Step -9 Outer Page Table Size-
Outer page table is required to keep track of the frames storing the
pages of inner page table.
Outer Page table size
= Number of entries in outer page table x Page table entry size
= Number of pages the inner page table is divided x Number of bits in
frame number
= 210 x 32 bits
= 210 x 4 bytes
= 4 KB

108
 Problems on Multilevel Paging
Now, the observation is -
The size of outer page table is same as frame size (4 KB).
Thus, outer page table can be stored in a single frame.
So, for given system, we will have two levels of page table.
Page Table Base Register (PTBR) will store the base address of the
outer page table.
Step – 10 Number of Bits Required to Search an Entry in Outer Page
Table-
Outer page table contains 210 entries.
Thus, Number of bits required to search a particular entry in outer page
table = 10 bits

109
 Problems on Multilevel Paging
The paging system will look like as shown below-

110
 64-bit Logical Address Space
Even two-level paging scheme not sufficient
If page size is 4 KB (212)
Then page table has 252 entries
If two level scheme, inner page tables could
be 210 4-byte entries
Address would look like

Outer page table has 242 entries or 244 bytes

111
64-bit Logical Address Space (Cont.)
One solution is to divide the outer page table. Various
ways of doing so. Example – three-level page table

Even with 2nd outer page table, the outer-outer table

is still 234 bytes in size.
And possibly 4 memory access to get to one physical
memory location.
The next step would be four-level. But ….

112
64-bit Logical Address Space (Cont.)
Several schemes for dealing with very large logical
address space

Hashed Page Table.

Clustered Page Tables
Inverted Page Table

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 Hashed Page Table
Common in address spaces > 32 bits
The virtual page number is hashed into a page table
This page table contains a chain of elements hashing
to the same location
Each element contains:
1. The virtual page number
2. The value of the mapped page frame
3. A pointer to the next element
Virtual page numbers are compared in this chain searching
for a match
If a match is found, the corresponding physical frame
is extracted

114
Hashed Page Table

115
Hashed Page Table

116
 Clustered Page Tables
Variation for 64-bit addresses is clustered page tables

Similar to hashed but each entry refers to several pages

(such as 16) rather than 1
Especially useful for sparse address spaces (where memory
references are non-contiguous and scattered)

117
 Inverted Page Table

Rather than each process having a page table and keeping

track of all possible logical pages, track all the physical
pages
Use inverted page-table, which has one entry for
each real page of memory
An entry the inverted-page table consists of the virtual
address of the page stored in that real memory location,
with information about the process that owns that page.
What is maximum size of the inverted page-table?

118
Inverted Page Table Architecture

119
 Inverted Page Table (Cont.)

Decreases memory needed to store each individual page

table, but increases time needed to search the inverted
page table when a page reference occurs
Use hash table to limit the search to one — or at most a
few — page-table entries
TLB can accelerate access
But how to implement shared memory?
One mapping of a virtual address to the shared
physical address

120
Segmented-paging-vs-Paged-segmentation

https://www.baeldung.com/cs/segmented-paging-vs-paged-segmentation

121
 Oracle SPARC Solaris
Consider modern, 64-bit operating system example with
tightly integrated HW
Goals are efficiency, low overhead
Based on hashing, but more complex
Two hash tables
One kernel and one for all user processes
Each maps memory addresses from virtual to physical
memory
Each entry represents a contiguous area of mapped
virtual memory,
 More efficient than having a separate hash-table entry
for each page
Each entry has base address and span (indicating the
number of pages the entry represents)

122
 Oracle SPARC Solaris (Cont.)
TLB holds translation table entries (TTEs) for fast hardware lookups
A cache of TTEs reside in a translation storage buffer (TSB)
 Includes an entry per recently accessed page
Virtual address reference causes TLB search
If miss, hardware walks the in-memory TSB looking for the TTE
corresponding to the address
 If match found, the CPU copies the TSB entry into the TLB
and translation completes
 If no match found, kernel interrupted to search the hash table
– The kernel then creates a TTE from the appropriate hash
table and stores it in the TSB, Interrupt handler returns
control to the MMU, which completes the address
translation.

123
Example: The Intel 32 and 64-bit Architectures

Dominant industry chips

Pentium CPUs are 32-bit and called IA-32
architecture
Current Intel CPUs are 64-bit and called IA-64
architecture
Many variations in the chips, cover the main ideas
here

124
 Example: The Intel IA-32 Architecture

Supports both segmentation and segmentation with paging

Each segment can be 4 GB
Up to 16 K segments per process
Divided into two partitions
 First partition of up to 8 K segments are private to
process (kept in local descriptor table (LDT))
 Second partition of up to 8K segments shared among all
processes (kept in global descriptor table (GDT))

125
 Example: The Intel IA-32 Architecture (Cont.)

CPU generates logical address

Selector given to segmentation unit
 Which produces linear addresses

Linear address given to paging unit

 Which generates physical address in main memory
 Paging units form equivalent of MMU
 Pages sizes can be 4 KB or 4 MB

126
Logical to Physical Address Translation in IA-32

127
Intel IA-32 Segmentation

128
Intel IA-32 Paging Architecture

129
 Intel IA-32 Page Address Extensions
32-bit address limits led Intel to create page address extension (PAE),
allowing 32-bit apps access to more than 4GB of memory space
Paging went to a 3-level scheme
Top two bits refer to a page directory pointer table
Page-directory and page-table entries moved to 64-bits in size
Net effect is increasing address space to 36 bits – 64GB of physical
memory

130
 Intel x86-64
Current generation Intel x86 architecture
64 bits is ginormous (> 16 exabytes)
In practice only implement 48 bit addressing
Page sizes of 4 KB, 2 MB, 1 GB
Four levels of paging hierarchy
Can also use PAE so virtual addresses are 48 bits and physical
addresses are 52 bits

131
 Example: ARM Architecture
Dominant mobile platform chip
(Apple iOS and Google Android
32 bits
devices for example)
outer page inner page offset
Modern, energy efficient, 32-bit
CPU
4 KB and 16 KB pages
4-KB
1 MB and 16 MB pages (termed or
16-KB
sections) page

One-level paging for sections, two-

level for smaller pages
Two levels of TLBs 1-MB
or
Outer level has two micro 16-MB
section
TLBs (one data, one
instruction)
Inner is single main TLB
First inner is checked, on
miss outers are checked,
and on miss page table
walk performed by CPU

132
 Swapping
A process can be swapped temporarily out of memory to a
backing store and then brought back into memory for
continued execution
Total physical memory space of all processes can
exceed the real physical memory of the system.
Backing store – fast disk large enough to accommodate
copies of all memory images for all processes; must provide
direct access to these memory images
System maintains a ready queue of ready-to-run processes
which are either in memory or have memory images on disk.
Major part of swap time is transfer time; total transfer time is
directly proportional to the amount of memory swapped

133
Schematic View of Swapping

134
 Swapping (Cont.)
Does the swapped out process need to swap back in to
same physical addresses?
Depends on address binding method
 Plus must consider pending I/O to / from process
memory space
Modified versions of swapping are found on many systems
(i.e., UNIX, Linux, and Windows). A common variation:
Swapping is normally disabled
Swapping is started if the amount of free memory
(unused memory available for the operating system or
processes to use) falls below a given threshold.
Swapping is disabled again once memory demand
reduced below the threshold
Another variation. Swapping portions of processes--rather
than entire processes--to decrease swap time.
Typically, these modified forms of swapping work in
conjunction with virtual memory (covered soon).

135
Context Switch Time including Swapping

If next processes to be located a CPU (say A) is not in

memory and there is not enough physical memory to
accommodate A, then we need to swap out one of the
processes in memory (say B) and swap in process A.
Context switch time can then be very high
100MB process swapping to hard disk with transfer rate of
50MB/sec
Swap out time of 2000 ms
Plus swap in of same sized process
Total context switch swapping component time of 4000ms
(4 seconds)
Can reduce context switch time by knowing how much memory
is really being used. System calls to inform OS of memory use:
request_memory() and release_memory()

136
Context Switch Time and Swapping (Cont.)

Other constraints as well on swapping

Pending I/O – can’t swap out as I/O would occur to wrong
process
Or always transfer I/O to kernel space, then to I/O device
 Known as double buffering, adds overhead
Standard swapping not used in modern operating systems
But modified version common
 Swap only when free memory extremely low

137
Swapping on Mobile Systems
Not typically supported. Mobil systems use Flash memory:
Limited number of write cycles
Poor throughput between flash memory and CPU on mobile
platform
Mobile systems use other methods to free memory if low
iOS asks apps to voluntarily relinquish allocated memory
 Read-only data thrown out and reloaded from flash if
needed
 Failure to free can result in termination
Android terminates apps if low free memory, but first writes
application state to flash for fast restart
Both operating systems support paging.

138