ADITYA ENGINEERING COLLEGE (A)

VLSI Design
Unit-II
Basic Electrical Properties of MOS and Bi-CMOS Circuits

P. Bujjibabu
Assistant Professor
Department of Electronics and Communication Engineering
Aditya Engineering College (A)
Email: [email protected]
 Aditya Engineering College (A)
Vision and Mission of the Department
Vision:
To become a center of excellence in the field of Electronics and
Communication Engineering with technological capability, professional
commitment and social responsibility.
Mission:
Ml: Provide quality education, well-equipped laboratory facilities and industry collaboration.

M2: Promote cutting edge technologies to serve the needs of the society and industry through
innovative research.

M3: Inculcate professional ethics and personality development skills.

5/15/2023 VLSI Design Unit II P. Bujjibabu, Associate Professor, ECE 2

 Aditya Engineering College (A)
Vision and Mission of the Institute
Vision:
• To emerge as a premier institute for quality technical education and
innovation
Mission:
• M1: Provide learner centric technical education towards academic excellence
• M2: Train on technology through collaborations
• M3: Promote innovative research & development
• M4: Involve industry institute interaction for societal needs

5/15/2023 VLSI Design Unit II P. Bujjibabu, Associate Professor, ECE 3

 Aditya Engineering College (A)

Course objectives
COB 1: To enable the students learn various fabrication steps of IC and MOS, Bi CMOS processes
COB 2: To enable the students learn basic electrical properties of Transistors in analysis of all circuits.
COB 3: To make the students study MOS technology-specific stick and layout rules
COB 4: To make students to familiar with different architectural issues of Subsystem design process
COB 5: To enable the students to highlight the architecture design issues in the context of IC design

Course outcomes
At the end of the Course, Student will be able to:

CO 1: Outline the fundamental concepts related to MOS and Bi-CMOS Circuits fabrication.
CO 2: Describe the electrical properties of MOS & BiCMOS circuits.
CO 3: Make use of design rules for stick and layout diagrams.
CO 4: Construct alternative forms of loads towards effective performance by subsystems.
CO 5: Interpret FPGA and ASIC design approaches for semi custom design.
P. Bujjibabu, Associate Professor, ECE 4
5/15/2023
VLSI Design Unit II
 Aditya Engineering College (A)
UNIT-II
Basic Electrical Properties of Circuits:
• Ids versus Vds Relationships It is required to go
with
• Aspects of MOS transistor: Vt, Gm, Gd, Figure of Merit,
Text Book 1. &
• Pass Transistor concept , Sung Mo Kang
• NMOS Inverter, alternative forms of pull ups
• Pull-up to Pull-down Ratio for NMOS Inverter driven by another NMOS inverter,
• Pull-up to Pull-down Ratio for NMOS Inverter driven by another NMOS inverter
through one or more Pass Transistors.
• The CMOS Inverter, and Bi-CMOS Inverter,
• Transistor switches,
• Schematics using NMOS, PMOS, and CMOS technologies:
Inverter
NAND gate
NOR gate
5/15/2023 VLSI Design Unit II P. Bujjibabu, Associate Professor, ECE 5
 metal Aditya Polysilicon
Engineering College (A)
Oxide
MOS diagrams N+ N+
P substrate
• nMOS enhancement mode
Vgs > Vth
p-,n-
lightly doped

Vds> (Vgs-Vth)

p,n
e-,e- holes Ids> 0 moderately
doped

P+,n+
heavily
dopde

P-Substrate
Electrons
5/15/2023 VLSI Design Unit II P. Bujjibabu, Associate Professor, ECE 6
 Summary of normal conduction characteristics: Aditya Engineering College (A)
 Cut-off : accumulation, Ids is essentially zero.
 Non-saturated : weak inversion, Ids dependent on both Vgs and Vds .
 Saturated : strong inversion, Ids is ideally independent of V ds.

Region NMOS
VDS < VDS(sat) W 1 2
I D  k (VGS  VTN )VDS  VDS 
'
n
Non-saturation/ L 2 
Triode V
RDSon  DS
ID
VDS > VDS(sat)
Saturation/ kn' W 
ID   [VGS  VTN ]
2
Pinch-off 2 L

Transition between triode

VDS(sat) = VGS - VTN
and pinch-off

Enhancement Mode VTN > 0 V, ID ≥ 0 mA, ID = IS, IG = 0 mA

5/15/2023 7
VLSI Design Unit II
 1. Ids vs Vds derivation Aditya Engineering College (A)

• A voltage on the gate, Vgs, induces a charge in the channel between source and drain
which may then caused electron to move from source to drain under the influence of
electric field created by drain voltage Vds.
• Since the charge induced is dependent on the gate -to-source voltage Vgs, then the Ids is
dependent on both Vgs and Vds.
• Consider the structure, as shown in figure below, in which electron will flow from source -
to- drain

5/15/2023 VLSI Design Unit II 8

 Aditya Engineering College (A)

charge induced in a channel (Qc )

• The drain to source current Ids is I ds  I -sd 
Electron transit time( sd )
Length of the channel (L)
• Where  sd 
Electron velocity (v)
• But velocity of moving particle is v   n Eds with an effective field developed
between drain and the source , Vds
Eds 
L
and hence electron velocity Vds
v  n
L L L2
• There fore  sd  which is then given by  sd 
n
Vds  nVds
L
where n  650 cm / v s and  p  240 cm / v s

5/15/2023 VLSI Design Unit II 9

 The Non-Saturation region: Aditya Engineering College (A)

• The total induced charge (Qc) in the channel is then given by Qc  Q0WL
• Where Qo is the charge per unit area which is given by Q0  E g  ins 0 and
• Eg is average electric field in the gate to channel and is given by

 g
V 
Vds 


 gs
V  Vt  
Vds 
 
     
VG 2 2
Eg 
D D D
 insis the relative permittivity of the insulation
 0 is the absolute permittivity
Vg is the effective gate voltage = Vgs-Vt
Vds/2 is the average voltage at drain terminal
Vt is the threshold voltage
W is the width of the MOS transistor
L is the length of the MOS transistor
VG is the gate voltage under Vds
D is the thickness of the gate oxide layer
10
5/15/2023 VLSI Design Unit II
• The total induced charge (Qc) in the channel is then given by Aditya Engineering College (A)



 V gs  Vt 
Vds 
 
  ins 0WL. 
2 
Qc
D
• Thus the drain - to - source current is given by

 V

 V gs  Vt  ds 
 ins 0WL. 
2 
Qc D
I ds  
 sd L2
or
 nVds


 V gs  Vt  
Vds 

I ds   ins 0WL.  2  1
. nVds 2 or
D L
 ins 0
I ds 
1 

WL. n . 2  V gs  Vt  
Vds 
.Vds or
D L  2 

I ds  1 
 C g . n . 2  V gs  Vt Vds 
.Vds C 
 A
5/15/2023
LII 
VLSI Design Unit 2  D 11
 • In other words the same current is also given by Aditya Engineering College (A)

 I ds  C0  n .
W 

 V gs  Vt 
L 

Vds 
2 
.Vds or

 I ds  K .
W 
 V
 
 V gs  Vt  ds .Vds
L  2 
The Saturation region:
• Saturation begins when
Vds  Vgs  Vt
W  V 2 
 I ds  K.  Vds 2  ds . or
L  2 
 
 2Vds 2  Vds 2 
W
 I ds 
 K. . or
 L 2 
 
W 
2   2 
 2V 2
 V   K. W V
 ds 
 I ds  K. ds ds
L 
 2 
 L 
 2 


 I ds  .
 Vds 2 
 

 .
Vgs  Vt 2
5/15/2023 VLSI Design  12
 2 Unit II 2
 Aditya Engineering College (A)

V-I characteristics of nMOS

The parameters that effect the magnitude of Ids are:
 The distance between source and drain (channel length).
 The channel width.  ins 0
 The threshold voltage. I ds 
1 

WL. n . 2  V gs  Vt 
Vds 
.Vds 
D L  2 
 The thickness of the gate oxide layer.
 The dielectric constant of the gate insulator.
 The carrier (electron or hole) mobility.
5/15/2023 VLSI Design Unit II 13
 Aspects of MOS Transistor: Threshold voltage:Aditya
VtEngineering College (A)

https://ecee.colorado.edu/~bart/book/book/chapter7/ch7_4.htm
• The MOSFET conducts no current between its source and drain terminals unless
VGS is greater than VT0.
• Increasing the gate-to-source voltage above and beyond VT0 will not affect the
surface potential and the depletion region depth.
• The gate to source voltage, for which the concentration of electrons under the gate
is equal to the concentration of holes in the p-sub far from the gate called the
THRESHOLD VOLTAGE (Vt = Vgs) and is given by
Lot more to
2 s qN A (2F  VSB )
VT  VFB  2F know about the
Cox Vt. If you wish,
go through the
link
Flat band
voltage From equations, threshold voltage may be varied by changing:
 The doping concentration (N A ).
 The oxide capacitance (C ox ).
 Surface state charge (Q fc ).
5/15/2023 VLSI Design Unit II 14
 Aspects of MOS Transistor: Transconductance,
Adityagm
Engineering College (A)

• In most MOSFET applications, an input signal is the gate voltage VG and the output is the
drain current Id.
• The ability of MOSFET to amplify the signal is given by the output current /input voltage
ratio, the Transconductance,

• Transconductance (gm) is a measure of how much drain current changes wrt the gate
voltage.
• For amplifier applications, the MOSFET is usually operating in the saturation region.
For a long-channel MOSFET:

g m   n Cox VGS  VTH 

W
L
For a short-channel MOSFET: Key factors influencing
g m  vsatWC ox the MOS Performance

5/15/2023 VLSI Design Unit II 16

 Aspects of MOS Transistor: Output Conductance
Adityagds
Engineering College (A)

• The output conductance of a MOS device is defined as the ratio between the
change in output current to the change in output voltage.
I ds
g ds 
Vds Vgs  Constant

• The output conductance in non saturation is given by

g ds   n Cox
W
L

Vgs  Vt  Vds 
• and decreases with increase in Vds (gds is 0 for saturation region).

Aspects of MOS Transistor: figure of merit wo

• Figure of merit is used obtain the frequency response characteristics of a MOS
device in presence of AC source at gate.
• rs & rd are ignored and all drops are zero
g
 C
n ox
W
Vgs  Vt  3 V  V 
• The figure of merit is given by w0  m  L 
n gs t
Cg 2
C0WL 2 L2
3
5/15/2023 VLSI Design Unit II 17
 MOSFET Pass Characteristics Aditya Engineering College (A)

5/15/2023 VLSI Design Unit II 18

 Aditya Engineering College (A)

Switch logic and gate logic

• Switch logic is based on the pass transistor (PTL)or on the transmission gate logic(TGL).
• This approach is fast for small arrays and takes no static current from the supply rails.
• Hence power dissipation is small since current flows on switching only.
• Switch (or pass transistor) logic is similar to logic arrays based on relay contacts
• The designer can implement logics with expected features.

5/15/2023 VLSI Design Unit II 19

 Aditya Engineering College (A)
Switch logic and gate logic
• Switch logic is based on the pass transistor (PTL)or on the transmission gate logic(TGL).
• This approach is fast for small arrays and takes no static current from the supply rails.
• Hence power dissipation is small since current flows on switching only.
• Switch (or pass transistor) logic is similar to logic arrays based on relay contacts
• The designer can implement logics with expected features.

AND
5/15/2023 gate in PTL VLSI Design Unit II 20
 Aditya Engineering College (A)
Switch logic and gate logic

Ex Or gate in PT Logic

5/15/2023 VLSI Design Unit II 21

 Name the logic? Aditya Engineering College (A)
Inverter

RTL Inverter logic DTL Inverter logic TTL Inverter logic nMOS Inverter logic with R as load

nMOS Inverter logic with

nMOS Inverter logic with
depletion nMOS as load CMOS Inverter logic Bi-CMOS Inverter logic
enhancement nMOS as load
5/15/2023 VLSI Design Unit II Source: https://www.falstad.com/circuit/ 22
 nMOS inverter Aditya Engineering College (A)
Vdd Vdd
Both the Vdd
Transistor & PU n/w
Resistor are Rd PU n/w PU n/w
taking much
of silicon area Vout Vout Vout
Vin
Vin Vin
PD n/w PD n/w PD n/w

Vss Vss Vss

Resistor as PU Depletion nMOS as PU Enhancement nMOS as PU
Vout
Vout Vtpu
Vdd
Vdd
Even Resistor is
taking much of
Vtpd
silicon area Vtpd
0.5Vdd
Vin 0.5Vdd
5/15/2023 VLSI Design Unit II Vin 23
 cMOS inverter Aditya Engineering College (A)
Vdd
Vout Vout

PU n/w Vdd Vdd

Vin Vout
Vinv Vinv

PD n/w
Vin Vin
Vss 0.5Vdd 0.5Vdd

 When Vin =0, then pMOS transistor(PU) is ON and nMOS transistor is off Vdd( logic 1)
 When Vin =1, then T3 is ON(T4 OFF) implies T1 ON (T2 OFF) and hence Vout= 0( logic 0)
 Good with large driving capability.
5/15/2023 VLSI Design Unit II 24
 CMOS Inverter: DC Analysis Aditya Engineering College (A)

• Analyze DC Characteristics of CMOS Gates

by studying an Inverter

• DC Analysis
– DC value of a signal in static conditions

• DC Analysis of CMOS Inverter

– Vin, input voltage
– Vout, output voltage
– single power supply, VDD
– Ground reference
– find Vout = f(Vin)

• Voltage Transfer Characteristic (VTC)

– plot of Vout as a function of Vin
– vary Vin from 0 to VDD
– find Vout at each value of Vin

5/15/2023 VLSI Design Unit II 25

 Inverter Voltage Transfer Characteristics Aditya Engineering College (A)

• Output High Voltage, VOH

– maximum output voltage
• occurs when input is low (Vin = 0V)
• pMOS is ON, nMOS is OFF
• pMOS pulls Vout to VDD
– VOH = VDD
• Output Low Voltage, VOL
– minimum output voltage
• occurs when input is high (Vin = VDD)
• pMOS is OFF, nMOS is ON
• nMOS pulls Vout to Ground
– VOL = 0 V
• Logic Swing
– Max swing of output signal
• VL = VOH - VOL
• VL = VDD

5/15/2023 VLSI Design Unit II 26

 Inverter Voltage Transfer Characteristics Aditya Engineering College (A)

• Gate Voltage, f(Vin) •Drain Voltage, f(Vout)

– VGSn=Vin, VSGp=VDD-Vin –VDSn=Vout, VSDp=VDD-Vout
+
• Transition Region (between VOH and VOL) VSGp
– Vin low -
• Vin < Vtn + VGSn
– Mn in Cutoff, OFF -
– Mp in Triode, Vout pulled to VDD
• Vin > Vtn < ~Vout
– Mn in Saturation, strong current
– Mp in Triode, VSG & current reducing
– Vout decreases via current through Mn
– Vin = Vout (mid point) ≈ ½ VDD
– Mn and Mp both in Saturation
– maximum current at Vin = Vout Vin < VIL
– Vin high input logic LOW
• Vin > ~Vout, Vin < VDD - |Vtp|
– Mn in Triode, Mp in Saturation
Vin > VIH
• Vin > VDD - |Vtp|
input logic HIGH
– Mn in Triode, Mp in Cutoff

5/15/2023 VLSI Design Unit II 27

 Aditya Engineering College (A)

Beta Ratios
Region C is the most important region. A small change in the input voltage, V in , results in a
LARGE change in the output voltage, V out .
This behavior describes an amplifier, the input is amplified at the output. The amplification is
termed transistor gain, which is given by beta.
Both the n and p-channel transistors have a beta.
Varying
5/15/2023
their ratio will change the characteristics of the output curve.
VLSI Design Unit II
28
 Aditya Engineering College (A)

5/15/2023 VLSI Design Unit II 29

 Bi-cMOS inverter Aditya Engineering College (A)

Vdd

T4 T2
0 ON ON

Vin= Vout

T3
T1 Vss

 When Vin =0, then T4 is ON(T3 OFF) implies T2 ON (T1 OFF) and hence Vout= Vdd(
logic 1)
 When Vin =1, then T3 is ON(T4 OFF) implies T1 ON (T2 OFF) and hence Vout= 0( logic
0)
 Good with large driving capability.
5/15/2023 30
VLSI Design Unit II
 Case-I Pull up to pull down ratio Aditya Engineering College (A)

• The transfer characteristics and Vinv can be shifted by varying the Zpu/Zpd
• As shown in figure, an inverter is driven by another similar inverter
• Consider the depletion mode transistor as pull up,for which Vgs=0 under all
conditions and meeting the requirement Vin=Vout= Vinv
VDD

Ids1
Vin1 Vin2 Vout2 Vgs=0
Vout1

Fig: Inverter driven by another inverter Ids2

Vgs= Vinv

5/15/2023 VLSI Design Unit II 31

 Pull up to pull down ratio Aditya Engineering College (A)

• Let us consider at Vg=Vin=Vinv=0.5VDD, both the transistors in an inverter are

in saturation with a drain current of; 2
 
V
W  gs
 Vt  VDD
I ds K
L 2

• In depletion mode tr(PUN), the drain current can be re written as Vgs=0

Ids1
2
 
W pu 
V td 
I ds  K
L pu 2
• and the current in the enhancement mode tr(PDN), is Ids2
Vgs= Vinv
2
 
W pd V
 inv
Vt 
I ds  K
L pd 2

5/15/2023 VLSI Design Unit II 32

 Pull up to pull down ratio Aditya Engineering College (A)

• In saturation, current in both the transistors are equal and hence

2 2

Vinv Vt 
 
 Vtd 

W pd   
W pu  
L pd 2 L pu 2

L pu L pd
1
Vinv  Vt  
2 1
 Vtd  ; Since, Z pu 
2
and Z pd 
Z pd Z pu W pu W pd

Z pu Z pu
Vinv  Vt 
2
  Vtd  
2
  Vtd  / Vinv  Vt 
2 2

Z pd Z pd
here;Vinv  0.5V
Vt  0.2V Z pu 4
 
Vtd  0.6V Z pd 1
• This is pull up to pull down ratio of inverter driven by another inverter
5/15/2023 VLSI Design Unit II 33
 Aditya Engineering College (A)
Pull up to pull down ratio of ….. through one or more PTs Case-II

• Let us consider the arrangement shown in fig. input to inverter 2 is from output of
inverter 1, but through the series of nMOS transistors called Pass Transistors
VDD
(VDD-Vt1)-Vt2
Vgs=0 Ids1
0 VDD VDD-Vt1 VDD or VDD-Vtp
VDD

Vout2
Vin2 Ids2
Vgs= VDD
Vin1 ~1
Vout1 1 <VDD VDD
0
VDD Vgs=0 Ids1
0V Vtp

Fig: Inverter driven by another inverter through one or more Pass Transistors Ids2
Vgs= VDD-Vtp

5/15/2023 VLSI Design Unit II 34

 Aditya Engineering College (A)

• We are now concerned that connection of pass transistors in series will degrade the logic 1 level
into inverter 2 so that the output will not be a proper logic 0 level.
• So as given in fig. input to inverter 2 is reduced by threshold voltage of series of nMOS pass
transistors.
• For this reduced voltage at input to inverter 2, we must get out the same as would be the output
of inverter 1.
VDD
VDD T1 T1
Vgs=0 Ids1 Depletion I2
Vgs=0 Depletion I1
Ids1 mode
mode

Ids2 Enhancement
Ids2 Vgs= VDD-Vtp R
Vgs= VDD Enhancement R mode
Vout2=I2R2
mode Vout1=I1R1 2
1 T2
T2
Vin=VDD Vin=VDD-Vtp

Fig: Inverter 1 with Vgs=Vin= VDD Fig: Inverter 2 with Vgs=Vin= VDD-Vtp

5/15/2023 VLSI Design Unit II 35

 Pull up to pull down ration Derivation Aditya Engineering College (A)

• If the input is at VDD, then the pd transistor T2 is conducting but with a low voltage across it
,and is said to be linear mode or resistive mode represented by R1 shown in fig.
• But, Pu transistor T1 is in saturation and is said to be constant current source.
• For the Pd transistor,
W pd 1  Vds1 
• W pd 1  Vds1  ; here Vgs=Vdd  I ds  K (VDD  Vt )  Vds1
I ds  K (Vgs  Vt )  2  Vds1 L pd 1  2 
L pd 1  
  here Vds1 very small and hence neglected
Vds1 1 L pd 1  1 
 R1     Vds1 1  1 
I ds K W pd 1  (V  
Vds1  R1   Z pd 1      (1)
 (VDD  Vt ) 
 V )  I ds K
 
DD t
2

• For the Pu transistor,

W pu1  (Vgs  Vt ) 2  W pu1  (0  Vtd ) 2 
• I ds  K   ; here Vgs=0  I ds K  
L pu1  2  L pu1  2 

5/15/2023 VLSI Design Unit II 36
 1  ( Vtd ) 2  Aditya Engineering College (A)
• And hence, I1  I ds  K      (2)
Z pu1 
 2 

1  ( Vtd ) 2  1  1 
Now Vout1  I1R1 K   X Z pd 1  
Z pu1  2  K VDD  Vt 
Z pd 1  ( Vtd ) 2   1 
 Vout1        (A)
Z pu1  2  VDD  Vt 
Now consider inverter 2 with input (VDD  Vtp )
Vds 2 1  1 
 R2   Z pd 2      (3)
I ds K  (VDD  Vtp  Vt ) 
 
1  (Vtd ) 2 
and I 2  I ds  K      (4)
Z pu 2  2 

Now Vout2  I 2 R2 1  (Vtd ) 2  1  1 

K   X Z pd 2  
Z pu 2  2  K  DD
V  V tp  Vt 

Z pd 2  (Vtd ) 2   1 
 Vout 2        (B)
Z pu 2  2  VDD  Vtp  Vt 
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 Aditya Engineering College (A)

• If inverter 2 is to have the same output voltage under these conditions as inverter 1,then
Vout1= Vout2.
Z pd 1  (Vtd ) 2   1  Z pd 2  (Vtd ) 2   1 
• ie… I1R1=I2R2      
Z pu1  2  VDD  Vt  Z pu 2  2  VDD  Vtp  Vt 
• Modifying the above equation, will give; Z pu 2 Z pu1  (VDD  Vt ) 
  
Z pd 2 Z pd 1 VDD  Vtp  Vt 

Z pu 2
 2 
4 8 at Vt  0.2VDD and Vtp  0.3VDD
• Which leads Z pd 2 1 1
Z pu 4

• For an inverter driven by another inverter is with Z pd and inverter driven by
1
another inverter through one or more Pass Transistor logic with Z pu 8 is

desirable to have proper logic at o/p with expected amount of shift Z pd 1

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 Aditya Engineering College (A)
Switch logic and gate logic
• Switch logic is based on the pass transistor (PTL)or on the transmission gate logic(TGL).
• This approach is fast for small arrays and takes no static current from the supply rails.
• Hence power dissipation is small since current flows on switching only.
• Switch (or pass transistor) logic is similar to logic arrays based on relay contacts
• The designer can implement logics with expected features.

AND
5/15/2023 gate in PTL VLSI Design Unit II 39
 Aditya Engineering College (A)
Switch logic and gate logic

Ex Or gate in PT Logic

5/15/2023 VLSI Design Unit II 40

 Aditya Engineering College (A)
CMOS inverter
Vdd

Vin Vout

Vss

Vdd Vin

Vout

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Vss VLSI Design Unit III P. Bujjibabu, Associate Professor, ECE
 Series/Parallel Equivalent Circuits Aditya Engineering College (A)

• Scale both W and L

– no effective change in W/L
– increases gate capacitance
 = Cox (W/L)
inputs must be at same value/voltage
• Series Transistors
– increases effective L
effective
  ½

• Parallel Transistors
– increases effective W

effective
  2

5/15/2023 VLSI Design Unit II 42

 Note: Aditya Engineering College (A)

Consider above cited books for reference only and you may get more
information from some other books and websites
Collect notes from your subject Teacher, if interested.

Useful Web links:

http://emicroelectronics.free.fr/onlineCourses/VLSI/toc.html
http://ece-research.unm.edu/jimp/vlsi/slides/c1_itrs.pdf
http://rti.etf.bg.ac.rs/rti/ri5rvl/tutorial/TUTORIAL/HTML/HOMEPG.HTM
https://www.tutorialspoint.com/vlsi_design/vlsi_design_useful_resources.htm
https://www.southampton.ac.uk/~bim/notes/cad/
http://www.uta.edu/ronc/4345sp02/lectures/
http://www.ece.utep.edu/courses/web5392/Lab_7.html
http://www.ece.utep.edu/courses/web5392/Notes.html
http://www.ittc.ku.edu/~jstiles/312/handouts/
https://www.mepits.com/tutorial/384/vlsi/steps-for-ic-manufacturing

5/15/2023 VLSI Design Unit II 43

P. Bujjibabu, Associate Professor, ECE