Chapter-6

Onboard communication Protocols

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INDEX
❑ Inter - Integrated Circuit (I2C ❑ SPI Topology
❑ I2C Introduction ❑ SPI Data Transmission
❑ What is I2C ❑ Clock Polarity and Phase
❑ I2C Features ❑ SPI Configuration
❑ Responsibility ❑ Advantages and drawbacks
❑ I2C Addressing ❑ SPI Devices & Applications
❑ I2C Operation ❑ Low Pin Count LPC
❑ START and STOP Conditions ❑ LPC Introduction
❑ I2C Full Data Transfer ❑ Goals of the LPC Interface
❑ I2C Read and Write Operations ❑ Applications
❑ I2C Read and Write Operations ❑ LPC bus limitations
❑ Multi-master I2C Systems
❑ Bus Recovery ❑ Enhanced Serial Peripheral Interface (eSPI)
❑ I2C Devices & Applications ❑ eSPI Introduction
❑ Requirements
❑ Serial Peripheral Interface ❑ eSPI Topology
SPI ❑ eSPI Configuration
❑ SPI Introduction

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 I2C Introduction
▪ When multiple devices Connecting to a microcontroller, the address and data lines
of each device were conventionally connected individually.
▪ This would take up precious pins on the microcontroller, result is lot of traces on
the PCB, and require more components to connect everything together.
▪ This made these systems expensive to produce and susceptible to interference and
noise.
To solve this problem
• Philips developed Inter-IC bus, or I2C, in
the 1980s.
• I2C is a low-bandwidth, short distance
protocol for on board communications.
All devices are connected through two
wires: serial data (SDA) and serial clock
(SCL). HCL training © copyright @etechprowess.com🌐 etechprowess.com
What is I2C
• The name stands for “Inter - Integrated Circuit Bus”
• It provide half-Duplex Operation
• Originally intended for operation on one
single board / PCB
▪ Synchronous Serial Signal
▪ Two wires carry information between
a number of devices
▪ One wire use for the data (SDA)
▪ One wire used for the clock (SCL)
• Today, a variety of devices are available with I2C Interfaces
▪ Microcontroller, EEPROM, Real-Timer, interface chips,
LCD driver, A/D converter
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 2
IC Features
I2C has many important features worth mentioning
• No strict baud rate requirements like for instance with RS232, the master generates a bus clock, it supports
multiple data speeds:
• standard (100 kbps)
• fast (400 kbps)
• high speed (3.4 Mbps) communications.
• I2C is a true multi-master bus providing arbitration and collision detection to prevent data corruption if
more than one masters simultaneously initiate data transfer.
• Master can operate as transmitter or receiver
• Two-wired bus, a serial data line (SDA) and a serial clock line (SCL).
• data transfers: serial, 8-bit oriented, bi-directional
• The number of ICs that can be connected to the same bus segment is limited only by the maximum bus
capacitive loading of 400 pF
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Responsibility
• Master:
• Initiates a transfer by generating
start and stop conditions
• Generates the clock
• Transmits the slave address
• Determines data transfer direction
• Slave:
• Responds only when addressed
• Timing is controlled by the clock line

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 2
IC Addressing
• The first byte of an I2C transfer contains the slave address and the data direction.
• Each node has a unique 7 (or 10) bit address (Given by manufacturer)
• 7 bit allows 128, I2C addresses (some addresses are reserved for special purposes. Thus,
only 112 addresses are available with the 7 bit address scheme. To get rid of this a special
method for using 10 bit addresses is defined.)
• Addresses starting with 0000 or 1111 have special functions

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 START and STOP Conditions
▪ A transition of the data line while the clock line is high is defined as either a start
or a stop condition.
▪ Both start and stop conditions are generated by the bus master
▪ The bus is considered busy after a start condition, until a stop condition occurs

START: AHIGH to LOW

transition on the SDA line
while SCL is HIGH
STOP: A LOW to HIGH
transition on the SDA line
while SCL is HIGH

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 I2C Operation
I2C has a master/slave protocol. The master initiates the communication. The sequence of events are:

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 I2C Operation
I2C has a master/slave protocol. The master
initiates the communication. The sequence of
events are:
• The Master device issues a start condition.
• The Master device sends the address of the
target slave device and a read/write flag.
• The Slave device with the matching address
responds with an acknowledgement signal.
• Communication proceeds between the
Master and the Slave on the data bus.
• When the communication is complete, the
master issues a stop condition

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I2C Full Data Transfer

eceiver

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I2C Read and Write Operations

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I2C Read and Write Operations

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Arbitration
• Bus arbitration occurs when two or more masters start a transfer at the same
time.
The two MCU's are accessing a slave in write mode at address 1111001

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Bus Recovery
• An I2C bus can be “locked” when:
• A Master and a Slave get out of synchronization.
• A Stop is omitted or missed (possibly due to noise)
• Any device on the bus holds one of the lines low improperly, for any reason
• A shorted bus line
• If SCL can be driven, the Master may send extra clocks until SDA goes high, then
send a Stop.
• If SCL is stuck low, only the device driving it can correct the problem.

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2
IC Devices & Applications
▪ Analog to Digital Converters (A/D, D/A): MMI functions, battery & converters, temperature
monitoring, control systems
▪ Bus Controller: Telecom, consumer electronics, automotive, Hi-Fi systems, PCs, servers
▪ Bus Repeater, Hub & Expander: Telecom, consumer electronics, automotive, Hi-Fi systems, PCs,
servers
▪ Real Time Clock (RTC)/Calendar: Telecom, EDP, consumer electronics, clocks, automotive, Hi-Fi
systems, FAX, PCs,terminals
▪ DIP Switch: Telecom, automotive, servers, battery & converters, control systems
▪ LCD/LED Display Drivers: Telecom, automotive instrument driver clusters, metering systems,
POS terminals, portable items, consumer electronics
There are some specific applications for certain types of I2C devices such as TV or radio tuners, but
in most cases a general purpose I2C device can be used in many different applications because of
its simple construction.
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Serial Peripheral Interface
SPI

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SPI Introduction
• SPI stands for Serial Peripheral Interface, developed by Motorola
SPI is a synchronous protocol that allows a master device to initiate communication
with a slave device.
• It provide Full-Duplex Operation mode using a master-slave architecture with a
single master
• It allows serial communication between two or more devices at a high speed and
is reasonably easy to implement.
• The clock signal controls when data is changed and when it should be read
• Since SPI is synchronous, the clock rate can vary, unlike RS-232 style
communications

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 SPI Topology
The SPI bus specifies four logic signals:
• SCLK: Serial Clock (output from master).
• MOSI: Master Output Slave Input, or
Master Out Slave In (data output from
master).
• MISO: Master Input Slave Output, or
Master In Slave Out (data output from
slave).
• SS/CS: Slave Select

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 SPI Data Transmission
• The master outputs the clock signal:

• The master switches the SS/CS pin to a low

voltage state, which activates the slave:

• The master sends the data one bit at a

time to the slave along the MOSI line. The
slave reads the bits as they are received:

• If a response is needed, the slave returns data

one bit at a time to the master along the
MISO line. The master reads the bits as they
are received: HCL training © copyright @etechprowess.com 🌐 etechprowess.com
 SPI Data Transmission
• Transmissions normally involve two shift registers of some size (eight bits), one in the
master and one in the slave
• They are connected in a virtual ring topology
• Data is usually shifted out with the most significant bit first

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 Clock Polarity and Phase

• To set the clock frequency, the master

must also configure the clock polarity and
phase with respect to the data
• CPOL : Determines the polarity of the
clock
• CPHA : Determines the timing of the
data bits relative to the clock pulses

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 Clock Polarity and Phase
• CPOL: Clock Polarity. This governs the initial logic state of the clock signal.
• CPHA: Clock Phase. This governs the relationship between the data transitions and the
clock transitions.
• The combinations of polarity and phases are often referred to as modes.

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Modes of SPI

Mode 0

Mode 1

Mode 2

Mode 3

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 SPI Configuration
• In the multiple-slave-select
configuration, each slave requires a
unique slave-select line from the
master
• Multiple slaves can be addressed
simultaneously if the master wants to
send the same data to multiple
slaves.

HCL Fig : Multiple

training slave
© copyright configuration
@etechprowess.com 🌐 etechprowess.com
SPI Configuration
• In this configuration, data moves
from one device to the next. The
final slave device can return data
to the master.
• In the daisy-chain configuration,
all slaves share a common slave-
select line.

Fig : Daisy chain configuration

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Advantages and drawbacks
• SPI is a very simple communication protocol.
• It does not have a specific high-level protocol which means that there is almost no overhead.
• Data can be shifted at very high rates in full duplex mode
• Not limited to any maximum clock speed, enabling potentially high speed
• Single master - single slave scenario.
• The exchange itself has no pre-defined protocol. This makes it ideal for data-streaming
applications.
• Data can be transferred at high speed, often into the range of the tens of megahertz.
• The drawback is that there is no acknowledgment, no flow control, and the
master may not even be aware of the slave's presence / or absence.

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SPI Devices & Applications
• Peripheral types can be subdivided into the following categories:
• Converters (ADC and DAC)
• Memories (EEPROM and FLASH)
• Real Time Clocks (RTC)
• Sensors (temperature, pressure)
• Others (signal mixer, potentiometer, LCD controller, UART, CAN controller, USB
controller, amplifier)

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Low Pin Count (LPC)

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 LPC Introduction
• The Low Pin Count(LPC) bus, is used to connect peripherals
around the CPU and to replace the Industry Standard
Architecture (ISA) bus
• It can connect the boot ROM, "legacy" I/O devices,
and Trusted Platform Module(TPM). "Legacy" I/O devices
usually include serial and parallel ports, PS/2 keyboard,
PS/2 mouse, and floppy disk controller.
• Most PC motherboards with an LPC bus have either a Platform
Controller Hub (PCH) or a Southbridge chip, which acts as the
host and controls the LPC bus.

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LPC Specification
The LPC specification defines seven mandatory signals required for bidirectional data
transfer.

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 Goals of the LPC Interface
• Enable a system without an ISA .
• Reduce the cost of traditional bus devices.
• Intended for use by devices down on a motherboard only (i.e. no
connector).
• Meet the data transfer rate of ISA, and exceed those data rates
where appropriate.
• Perform the same cycle types as the ISA: Memory, I/O, DMA, and
Bus Master
• Ability to support a variable number of wait-states.
• Ability to support wake-up and other power state transitions.

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Goals of the LPC Interface

TL611 PRO PCI-E LPC

Motherboard
Diagnostic Test

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 TPM (Trusted Platform Module)
• TPM (Trusted Platform Module) is a computer chip (microcontroller) that can
securely store artifacts used to authenticate the platform (your PC or laptop).
These artifacts can include passwords, certificates, or encryption keys

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 TPM (Trusted Platform Module)
• In Laptop TPM chip is either TSSOP-28 or QFN-32, and they both are tiny
packages. The TSSOP package could be probed with some high-quality probes

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 SPI Bus sniffing
• The screenshot below shows decoded MOSI and MISO byte streams from the
capture

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 Trusted Platform Module
• Trusted Platform Module is a cryptographic coprocessor, which implements a predefined
set of cryptographic operations, secure key storage, and a set of Platform Configuration
Registers (PCRs).
• The two different IC package types are allowed for TPM, which are TSSOP-28 (on the left)
and QFN-32

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 Applications
• Intel designed the LPC bus so that the system BIOS image could be stored in a
single flash memory chip directly connected to the LPC bus.
• Intel also made it possible to put operating system images and software
applications on a single flash memory chip directly connected to the LPC bus, as
an alternative to a Parallel ATA port.
• A CPLD or FPGA can implement an LPC host or peripheral.
• The original Xbox game console has an LPC debug port that can be used to force
the Xbox to boot new code

LPC-Debug Post Card Diagnostic Test kit

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LPC bus limitations
• LPC consists of 7 required pins and 6 optional pins that makes up to a total of 13 pins to
implement.
• Present implementations of the LPC include a fabrication process cost burden as it is
based on 3.3V I/O signalling technology.
• The frequency of the bus clock is fixed at 33 MHz. The fix LPC bandwidth of 133 Mbps is
deemed insufficient to cater for the demands of new devices. Connecting these devices
to high speed interfaces such as PCI Express and USB3 is prohibitive from cost
perspective.
• There exist a significant number of sideband signals used for communication between
chipset and EC, BMC and SIO that amounts to significant pin cost.

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Enhanced Serial Peripheral Interface
(eSPI)

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 eSPI Introduction
• LPC bus limitations led to the
development of eSPI
• The eSPI specification provides a path
for migrating LPC devices over to the
new eSPI interface.
• eSPI reuses the timing and electrical
specification of Serial Peripheral
Interface (SPI) but with different
protocol to meet a set of different
requirements.

Fig : EC/BMC/SIO Communication over eSPI

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Requirements
eSPI is defined to meet the following requirements:
• Low Power
• Pin Count Reduction
• Medium Bandwidth
• LPC Replacement
• Sideband Pins as In-Band Messaging
• Real Time Flash Sharing
• Chipset and Slave Devices SMBus Replacement
• Scalable bandwidth

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eSPI Topology
▪ eSPI bus, there is only one eSPI master and one or more eSPI slaves.
▪ eSPI master dictates the flow of command and data between itself and the eSPI slaves
by controlling the Chip Select# pins for each of the eSPI slaves.
▪ At any one time, the eSPI master must ensure that only one of the Chip Select# pins is
asserted based on source decode.
▪ eSPI master is the only component that is allowed to drive Chip Select# when eSPI
Reset# is de-asserted.

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 eSPI Configuration
Single Master-Single Slave configuration

Fig : Single Master-Single Slave with eSPI Reset# from Slave to Master Fig : Single Master-Single Slave with eSPI Reset# from Master to Slave

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 eSPI Configuration
Multi-drop mode

Single Master-Multiple Slaves with Two eSPI

Reset#

The number of devices that

can be supported over a single eSPI bus
interface is limited by bus loading and signals
trace length.

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