EiceDRIVER™

2EDN753x/2EDN853x/2EDN743x
Dual-channel low-side 5 A gate driver ICs with low ou tput resistance
and excellent timing accuracy

Description
The EiceDRIVER™ 2EDN family is offered in 8-pin DSO, TSSOP and WSON packages as well as in small and versatile 6-pin
SOT23 package. High output current capability together with active output voltage clamping, tight timing specifications,
and optimized start-up and shut-down times, make the 2EDN family the first choice for many fast-switching applications.

Product features Applications

• ±5 A source/sink currents • Switch-mode power-supplies
• 19 ns typ. propagation delay • DC-DC power converters
• +6/-4 ns propagation delay accuracy • Synchronous rectification stages
• 1.8 µs output start-up time • Power factor correction systems
• 500 ns output shut-down time
• Active output voltage clamping
• -12 V input robustness
• 5 A reverse current robustness
• 4 V and 8 V UVLO options
• Package options:
– 8-pin DSO, TSSOP, WSON
– 6-pin SOT23
• Fully qualified for industrial applications according to JEDEC

Available device configurations

8-pin packages 8-pin packages 6-pin packages 6-pin packages

Direct configuration Inverted configuration Direct configuration Inverted configuration

ENA 1 8 ENB ENA 1 8 ENB INA 4 3 OUTA INA 4 3 OUTA

INA 2 7 OUTA INA 2 7 OUTA

INB 5 2 GND INB 5 2 GND
GND 3 6 VDD GND 3 6 VDD

INB 4 5 OUTB INB 4 5 OUTB VDD 6 1 OUTB VDD 6 1 OUTB

Peak output Inputs 8-pin DSO 8-pin TSSOP 8-pin WSON 6-pin SOT23
current 4V UVLO 8V UVLO 4V UVLO 8V UVLO 4V UVLO 4V UVLO
direct 2EDN7534F 2EDN8534F 2EDN7534R 2EDN8534R 2EDN7534G 2EDN7534B
5A
inverting 2EDN7533F 2EDN8533F 2EDN7533R 2EDN8533R – 2EDN7533B
4A direct 2EDN7434F – 2EDN7434R – – –

Datasheet Please read the Important Notice and Warnings at the end of this document Rev.1.0
www.infineon.com 2021-10-29
EiceDRIVER™ 2EDN753x/2EDN853x/2EDN743x
Dual-channel 5 A and 4 A, high-speed, low-side gate driver ICs
Table of Contents

Table of Contents

Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Table of Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
1 Product versions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
1.1 Logic configuration versions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
1.2 Package versions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
2 Pin configuration and description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
2.1 Input configuration for PG-DSO-8 package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
2.2 Input configuration for PG-TSSOP-8 package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
2.3 Input configuration for PG-WSON-8 package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
2.4 Input configuration for PG-SOT23-6 package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
3 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
4 Functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
4.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
4.2 Supply voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
4.3 Undervoltage lockout (UVLO) function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
4.4 Input configurations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
4.5 Driver outputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
4.6 Active output voltage clamping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
5 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
5.1 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
5.2 Thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
5.3 Operating range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
5.4 General electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
6 Timing diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
7 Typical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
8 Application and implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
9 Package outlines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
9.1 Device numbers and markings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
9.2 PG-DSO-8 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
9.3 PG-TSSOP-8 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
9.4 PG-WSON-8 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
9.5 PG-SOT23-6 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
10 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35

Datasheet 2 Rev.1.0
2021-10-29
EiceDRIVER™ 2EDN753x/2EDN853x/2EDN743x
Dual-channel 5 A and 4 A, high-speed, low-side gate driver ICs
Product versions

1 Product versions
The EiceDRIVER™ 2EDN753x/2EDN853x/2EDN743x are available in two different logic configurations (direct and
inverting), two different undervoltage lockout levels (4 V and 8 V) and four package versions.

1.1 Logic configuration versions

The two input logic configurations are identified by the "x" variable in the product code
EiceDRIVER™ 2EDN753x/2EDN853x/2EDN743x:
• x = 3: inverting input logic
• x = 4: non-inverting/direct input logic
Table 1 and Table 2 describe the logic dependence of the output state from undervoltage lockout (UVLO), enable
and input pins for the 8-pin and 6-pin variants respectively. If the enable pin ENA (or ENB) is either driven high or
left open, the associated gate driver output depends on the respective input pin. If the enable pin ENA (or ENB) is
low, the associated OUT pin is low, independent of the input signal. If a UVLO event is triggered, both OUTA and
OUTB are kept in a low state, regardless of the input and enable pins status.
The functional description is in Chapter 3 (Block diagram) and Chapter 4 (Functional description).

Table 1 Logic table for DSO-8, TSSOP-8, WSON-8 pin packages

Inputs Inverting output Direct output
1)
ENA ENB INA INB UVLO OUTA OUTB OUTA OUTB
x x x x active L L L L
L L x x inactive L L L L
H L L x inactive H L L L
H L H x inactive L L H L
L H x L inactive L H L L
L H x H inactive L L L H
H H L L inactive H H L L
H H H L inactive L H H L
H H L H inactive H L L H
H H H H inactive L L H H
1) Inactive UVLO: VDD is above UVLOON voltage threshold and control logic drives the output stage.
Active UVLO: an undervoltage lockout event has been triggered

Table 2 Logic table for SOT23-6 pin package

Inputs Inverting output Direct output
1)
INA INB UVLO OUTA OUTB OUTA OUTB
x x active L L L L
L L inactive H H L L
H L inactive L H H L
L H inactive H L L H
H H inactive L L H H
1) Inactive UVLO: VDD is above UVLOON voltage threshold and control logic drives the output stage.
Active UVLO: an undervoltage lockout event has been triggered

Datasheet 3 Rev.1.0
2021-10-29
EiceDRIVER™ 2EDN753x/2EDN853x/2EDN743x
Dual-channel 5 A and 4 A, high-speed, low-side gate driver ICs
Product versions

1.2 Package versions

The EiceDRIVER™ 2EDN family is available in four different package versions. The package type is identified by the
last character in the product code:
• the standard PG-DSO-8 is designated by “F” (e.g. 2EDN753xF)
• the small leaded PG-TSSOP-8 is designated by “R” (e.g. 2EDN753xR)
• the leadless PG-WSON-8 is designated by “G” (e.g. 2EDN753xG)
• the ultra tiny PG-SOT23-6 is designated by “B” (e.g. 2EDN753xB)
Package drawings are available in Chapter 9 (Package outlines).

Datasheet 4 Rev.1.0
2021-10-29
EiceDRIVER™ 2EDN753x/2EDN853x/2EDN743x
Dual-channel 5 A and 4 A, high-speed, low-side gate driver ICs
Pin configuration and description

2 Pin configuration and description

2.1 Input configuration for PG-DSO-8 package

The pin configuration for all input versions of EiceDRIVER™ 2EDN7534F, 2EDN7434F, 2EDN7533F, 2EDN8534F and
2EDN8533F in the PG-DSO-8 package is shown in Figure 1. Diagrams can be viewed in Chapter 9.2 (PG-DSO-8).

1 ENA ENB 8

2 INA OUTA 7

3 GND VDD 6

4 INB OUTB 5

Figure 1 Pin configuration PG-DSO-8, top view

Table 3 Pin configuration for PG-DSO-8 package

Pin Symbol Description
number
1 ENA Enable input channel A
Logic input. If ENA is high or left open, OUTA is controlled by INA.
ENA low causes OUTA low
2 INA Input signal channel A
Logic input, controlling OUTA (inverting or non-inverting)
3 GND Ground
Gate driver reference ground
4 INB Input signal channel B
Logic input, controlling OUTB (inverting or non-inverting)
5 OUTB Driver output channel B
Low-impedance output with source and sink capability
6 VDD Positive supply voltage
Operating range 4.5 V/8.6 V to 20 V
7 OUTA Driver output channel A
Low-impedance output with source and sink capability
8 ENB Enable input channel B
Logic Input. If ENB is high or left open, OUTB is controlled by INB.
ENB low causes OUTB low

Datasheet 5 Rev.1.0
2021-10-29
EiceDRIVER™ 2EDN753x/2EDN853x/2EDN743x
Dual-channel 5 A and 4 A, high-speed, low-side gate driver ICs
Pin configuration and description

2.2 Input configuration for PG-TSSOP-8 package

The pin configuration for all input versions of EiceDRIVER™ 2EDN7534R, 2EDN7434R, 2EDN7533R, 2EDN8534R and
2EDN8533R in the PG-TSSOP-8 package is shown in Figure 2. Diagrams can be viewed in Chapter 9.3 (PG-
TSSOP-8).

1 ENA ENB 8

2 INA OUTA 7
Exposed
Pad
3 GND VDD 6

4 INB OUTB 5

Figure 2 Pin configuration PG-TSSOP-8, top view

Table 4 Pin configuration for PG-TSSOP-8 package

Pin Symbol Description
Number
1 ENA Enable input channel A
Logic input. If ENA is high or left open, OUTA is controlled by INA.
ENA low causes OUTA low
2 INA Input signal channel A
Logic input, controlling OUTA (non-inverting)
3 GND Ground1)
Gate driver reference ground
4 INB Input signal channel B
Logic input, controlling OUTB (non-inverting)
5 OUTB Driver output channel B
Low-impedance output with source and sink capability
6 VDD Positive supply voltage
Operating range 4.5 V/8.6 V to 20 V
7 OUTA Driver output channel A
Low-impedance output with source and sink capability
8 ENB Enable input channel B
Logic Input. If ENB is high or left open, OUTB is controlled by INB.
ENB low causes OUTB low
1) Exposed pad sink of PG-TSSOP-8 packages has to be connected to GND pin

Datasheet 6 Rev.1.0
2021-10-29
EiceDRIVER™ 2EDN753x/2EDN853x/2EDN743x
Dual-channel 5 A and 4 A, high-speed, low-side gate driver ICs
Pin configuration and description

2.3 Input configuration for PG-WSON-8 package

The pin configuration of EiceDRIVER™ 2EDN7534G in the PG-WSON-8 package is shown in Figure 3. Diagrams can
be viewed in Chapter 9.4 (PG-WSON-8).

ENA 1 8 ENB

INA 2 7 OUTA
Exposed
Pad
GND 3 6 VDD

INB 4 5 OUTB

Figure 3 Pin configuration PG-WSON-8, top view

Table 5 Pin configuration for PG-WSON-8 package

Pin Symbol Description
number
1 ENA Enable input channel A
Logic input. If ENA is high or left open, OUTA is controlled by INA.
ENA low causes OUTA low
2 INA Input signal channel A
Logic input, controlling OUTA (non-inverting)
3 GND Ground1)
Gate driver reference ground
4 INB Input signal channel B
Logic input, controlling OUTB (non-inverting)
5 OUTB Driver output channel B
Low-impedance output with source and sink capability
6 VDD Positive supply voltage
Operating range 4.5 V to 20 V
7 OUTA Driver output channel A
Low-impedance output with source and sink capability
8 ENB Enable input channel B
Logic Input. If ENB is high or left open, OUTB is controlled by INB.
ENB low causes OUTB low
1) Exposed pad of PG-WSON-8 packages has to be connected to GND pin

Datasheet 7 Rev.1.0
2021-10-29
EiceDRIVER™ 2EDN753x/2EDN853x/2EDN743x
Dual-channel 5 A and 4 A, high-speed, low-side gate driver ICs
Pin configuration and description

2.4 Input configuration for PG-SOT23-6 package

The pin configuration of EiceDRIVER™ 2EDN7534B and 2EDN7533B in the PG-SOT23-6 package is shown in
Figure 4. Drawings can be viewed in Chapter 9.5 (PG-SOT23-6).

1 OUTB VDD 6

2 GND INB 5

3 OUTA INA 4

Figure 4 Pin configuration PG-SOT23-6, top view

Table 6 Pin configuration for PG-SOT23-6 package

Pin Symbol Description
number
1 OUTB Driver output channel B
Low-impedance output with source and sink capability
2 GND Ground
Gate driver reference ground
3 OUTA Driver output channel A
Low-impedance output with source and sink capability
4 INA Input signal channel A
Logic input, controlling OUTA (non-inverting)
5 INB Input signal channel B
Logic input, controlling OUTB (non-inverting)
6 VDD Positive supply voltage
Operating range 4.5 V to 20 V

Datasheet 8 Rev.1.0
2021-10-29
EiceDRIVER™ 2EDN753x/2EDN853x/2EDN743x
Dual-channel 5 A and 4 A, high-speed, low-side gate driver ICs
Block diagram

3 Block diagram
Simplified functional block diagrams for the DSO-8, TSSOP-8, WSON-8 package variants are given in Figure 5 and
Figure 6. Block diagrams for the SOT23-6 package variants are shown in Figure 7 and Figure 8. Please refer to
functional description in Chapter 4.

VDD

VDD 6 VDD VDD

VDD
UVLO
400 kΩ

ENA 1

Logic A 7 OUTA
Active
Clamp

INA 2

100 kΩ GND
VDD

GND
400 kΩ VDD

ENB 8

Logic B 5 OUTB
Active
INB 4 Clamp

100 kΩ

GND
GND 3 GND

GND

Figure 5 Simplified block diagram for direct/non-inverting input configuration, 8-pin packages

VDD

VDD 6 VDD VDD

VDD
UVLO
400 kΩ

ENA 1

Logic A 7 OUTA
400 kΩ Active
Clamp

INA 2

GND
VDD

VDD
400 kΩ
ENB 8

400 kΩ
Logic B 5 OUTB
Active
INB 4 Clamp

GND
GND 3

GND

Figure 6 Simplified block diagram for inverting input configuration, 8-pin packages

Datasheet 9 Rev.1.0
2021-10-29
EiceDRIVER™ 2EDN753x/2EDN853x/2EDN743x
Dual-channel 5 A and 4 A, high-speed, low-side gate driver ICs
Block diagram

VDD VDD
VDD
VDD 6
UVLO

Logic A 7 OUTA
Active
INA 2 Clamp

100 kΩ

GND
GND
VDD

Logic B 5 OUTB
Active
INB 4 Clamp

100 kΩ

GND
GND 3 GND

GND

Figure 7 Simplified block diagram for direct/non-inverting input configuration, 6-pin packages

VDD VDD
VDD
VDD 6
UVLO
VDD

400 kΩ Logic A 7 OUTA

Active
INA 2 Clamp

GND

VDD

VDD

400 kΩ Logic B 5 OUTB

Active
INB 4 Clamp

GND
GND 3

GND

Figure 8 Simplified block diagram for inverting input configuration, 6-pin packages

Datasheet 10 Rev.1.0
2021-10-29
EiceDRIVER™ 2EDN753x/2EDN853x/2EDN743x
Dual-channel 5 A and 4 A, high-speed, low-side gate driver ICs
Functional description

4 Functional description

4.1 Introduction
The EiceDRIVER™ 2EDN753x/2EDN853x/2EDN743x is a fast dual-channel driver for low-side switches. Two true
rail-to-rail output stages with very low output impedance and high current capability are chosen to ensure high
flexibility and cover a high variety of applications.
An extended negative voltage range protects input pins against ground shifts. No current flows over the ESD
structure in the IC during a negative input level. All outputs are robust against reverse current. During the
interaction with the power MOSFET, reverse reflected power is handled by the internal output stage.
All inputs are compatible with LV-TTL signal levels. The threshold voltages have a typical hysteresis of 0.9 V, that
is constant over the supply voltage range.
EiceDRIVER™ 2EDN753x/2EDN853x/2EDN743x ensure optimal performance in fast-switching applications
because of the low delays and rise/fall times. The maximum skew between Channel A and Channel B is 2 ns.

4.2 Supply voltage

The maximum operating supply voltage is 20 V. This high voltage is valuable in order to exploit the full current
capability of EiceDRIVER™ 2EDN753x/2EDN853x/2EDN743x when driving low RDSON MOSFETs. The minimum
operating supply voltage is set by the undervoltage lockout function to a typical default values of 4.2 V for the
4 V-UVLO variant and 8 V for the 8 V-UVLO variant.

4.3 Undervoltage lockout (UVLO) function

The undervoltage lockout function ensures that the output can be switched to its high level only if the supply
voltage exceeds the UVLO threshold voltage. This protects power MOSFETs from running into linear mode,
preventing excessive power dissipation if the voltage is not enough to completely turn on the switches.
The UVLO level is set to a typical value of 4.2 V or 8 V (with hysteresis). UVLO of 4.2 V is normally used for logic level
MOSFETs. For standard and high voltage superjunction MOSFETs, a UVLO voltage of typical 8 V is available.

Table 7 UVLO turn-on and turn-off thresholds

Nominal UVLO level UVLO turn-on threshold (typ.) UVLO turn-off threshold (typ.)
4.2 V 4.2 V 3.9 V
8.0 V 8.0 V 7.0 V

4.4 Input configurations

As described in Chapter 1, EiceDRIVER™ 2EDN753x/2EDN853x/2EDN743x are available in two different
configurations with respect to the logic of the input pins.
The enable inputs are internally pulled up to a logic high voltage, i.e. the driver is enabled with these pins left
open. The direct PWM inputs are internally pulled down to a logic low voltage. This prevents a switch-on event
during power up and a not driven input condition. Version with inverted PWM input have an internal pull up
resistor to prevent unwanted switch-on.
All inputs are compatible with LV-TTL levels and provide a hysteresis of 0.9 V typ. This hysteresis is independent
of the supply voltage.
All input pins have a negative extended voltage range. This prevents cross-current over single wires during GND
shifts between signal source (controller) and driver input.

Datasheet 11 Rev.1.0
2021-10-29
EiceDRIVER™ 2EDN753x/2EDN853x/2EDN743x
Dual-channel 5 A and 4 A, high-speed, low-side gate driver ICs
Functional description

4.5 Driver outputs

The two rail-to-rail output stages realized with complementary MOS transistors are able to provide a maximum
sinking/sourcing current of 5 A (4 A output current versions are also available). This driver output stage has a
shoot-through protection and current limiting behavior. After a switching event, current limitation is raised up to
achieve the typical current peak for an excellent fast reaction time of the following power MOS transistor.
The output impedances for the sourcing p-channel MOS have typical values of 0.8 Ω for 2EDN753x and 2EDN853x
and 1.0 Ω for 2EDN743x. The output impedances for the sinking n-channel MOS transistor have
typical values of 0.6 Ω for 2EDN753x and 2EDN853x and 0.8 Ω for 2EDN743x. The use of a p-channel sourcing
transistor is crucial for achieving true rail-to-rail behavior and avoiding a source follower’s voltage drop.
Gate drive outputs are kept actively low in case of floating ENx or INx inputs, or during startup or power down if
the supply voltage is below the UVLO threshold.

4.6 Active output voltage clamping

The undervoltage lockout (UVLO) protection ensures no driver operation when the supply voltage is below the
UVLO threshold. However, this is not sufficient to keep output low when VDD is far below the UVLO threshold. As
a result, fast dv/dt of the switches could trigger undesired Vgs of the driven device, leading to abnormal turn-ons.
The fast active output voltage clamping of EiceDRIVER™ 2EDN753x/2EDN853x/2EDN743x is intended to actively
keep the driver output low when the VDD voltage is between 1.2V and UVLOON threshold, overcoming the
unwanted turn-on issue listed above and ensuring safe off state before device operation.
This structure allows fast reaction and effective clamping of the output pins (OUTx). The exact reaction time
depends on the power supply (VDD) and on the output voltage levels. Undervoltage Lockout together with the
output active clamping ensure that the output is actively held low in case of insufficient supply voltage.

Table 8 Logic table in case of insufficient supply voltages

Inputs Supplies Output
INx VDD OUTx
x 1.2 V < VDD < UVLOVDD,ON L

Datasheet 12 Rev.1.0
2021-10-29
EiceDRIVER™ 2EDN753x/2EDN853x/2EDN743x
Dual-channel 5 A and 4 A, high-speed, low-side gate driver ICs
Electrical characteristics

5 Electrical characteristics
Note: The absolute maximum ratings are listed in Table 9. Stresses beyond these values may cause
permanent damage to the device. Exposure to absolute maximum rating conditions for extended
periods may affect device reliability.

5.1 Absolute maximum ratings

Table 9 Absolute maximum ratings

Parameter Symbol Values Unit Note or Test Condition
Min. Typ. Max.
Positive supply voltage VDD -0.3 – 22 V –
Voltage at pins INA, INB, ENA, VIN -12 – 22 V –
ENB
1)
Voltage at pins OUTA, OUTB VOUT -0.3 – VDD+ 0.3 V
-2 – VDD+ 2 V Repetitive pulse < 200 ns 2)
Reverse current peak at pins ISNKREV -5 – – Apk < 500 ns
OUTA, OUTB ISRCREV – 5
Junction temperature TJ -40 – 150 °C –
Storage temperature TS -55 – 150 °C –
ESD capability VESD – – 0.5 kV Charged Device Model (CDM)
3)

ESD capability VESD – – 2.0 kV Human Body Model (HBM) 4)

1) Voltage spikes resulting from reverse current peaks are allowed
2) Values are verified by characterization on bench
3) According to JESD22-002
4) According to JESD22-A114-B (discharging 100 pF capacitor through 1.5 kΩ resistor)

5.2 Thermal characteristics

Table 10 Thermal characteristics

Parameter Symbol Values Unit Note or Test Condition
Min. Typ. Max.
PG-DSO-8, Tamb = 25°C
1)
Thermal resistance junction- RthJA25 – 111 – K/W
ambient
2)
Thermal resistance junction- RthJC25 – 66 – K/W
case (top)
3)
Thermal resistance junction- RthJB25 – 59 – K/W
board
4)
Characterization parameter ΨthJC25 – 12 – K/W
junction-top
5)
Characterization parameter ΨthJB25 – 57 – K/W
junction-board

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Dual-channel 5 A and 4 A, high-speed, low-side gate driver ICs
Electrical characteristics

Table 10 Thermal characteristics (continued)

Parameter Symbol Values Unit Note or Test Condition
Min. Typ. Max.
PG-TSSOP-8, Tamb = 25°C
1)6)
Thermal resistance junction- RthJA25 – 48 – K/W
ambient
2)
Thermal resistance junction-case RthJP25 – 74 – K/W
(top)
3)6)
Thermal resistance junction- RthJB25 – 22.5 – K/W
board
4)6)
Characterization parameter ΨthJC25 – 3 – K/W
junction-top
5)6)
Characterization parameter ΨthJB25 – 21 – K/W
junction-board
PG-WSON-8, Tamb = 25°C
1)6)
Thermal resistance junction- RthJA25 – 46 – K/W
ambient
2)
Thermal resistance junction-case RthJP25 – 73 – K/W
(top)
3)6)
Thermal resistance junction- RthJB25 – 18 – K/W
board
4)6)
Characterization parameter ΨthJC25 – 2 – K/W
junction-top
5)6)
Characterization parameter ΨthJB25 – 17.5 – K/W
junction-board
PG-SOT23-6, Tamb=25°C
1)
Thermal resistance junction- RthJA25 – 163 – K/W
ambient
2)
Thermal resistance junction-case RthJC25 – 69 – K/W
(top)
3)
Thermal resistance junction- RthJB25 – 36 – K/W
board
4)
Characterization parameter ΨthJC25 – 13 – K/W
junction-case (top)
5)
Characterization parameter ΨthJB25 – 36 – K/W
junction-board
1) The junction-to-ambient thermal resistance under natural convection is obtained in a simulation on a JEDEC-standard,
high-K board, as specified in JESD51-7, in an environment described in JESD51-2a
2) The junction-to-case (top) thermal resistance is obtained by simulating a cold plate test on the package top. No specific
JEDEC standard test exists, but a close description can be found in the ANSI SEMI standard G30-88
3) The junction-to-board thermal resistance is obtained by simulating in an environment with a ring cold plate fixture to
control the PCB temperature, as described in JESD51-8
4) The characterization parameter junction-top, estimates the junction temperature of a device in a real system and is
extracted from the simulation data for obtaining Rth, using a procedure described in JESD51-2a (sections 6 and 7)
5) The characterization parameter junction-board, estimates the junction temperature of a device in a real system and is
extracted from the simulation data for obtaining Rth, using a procedure described in JESD51-2a (sections 6 and 7)
6) Characterization done on a JEDEC 2s2p PCB with thermal via array connected to the first inner copper layer under the
exposed pad

Datasheet 14 Rev.1.0
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Dual-channel 5 A and 4 A, high-speed, low-side gate driver ICs
Electrical characteristics

5.3 Operating range

Table 11 Operating range

Parameter Symbol Values Unit Note or Test Condition
Min. Typ. Max.
Supply voltage VDD 4.5 – 20 V Min. defined by UVLO
Logic input voltage VIN -10 – 20 V –
1)
Junction temperature TJ -40 – 150 °C
1) Continuous operation above 125°C may reduce life time

5.4 General electrical characteristics

Unless otherwise noted, min./max. values of characteristics are the lower and upper limits respectively. They are
valid within the full operating range. The supply voltage is VDD = 12 V. Typical values are given at TJ = 25°C.

Table 12 Power supply

Parameter Symbol Values Unit Note or Test Condition
Min. Typ. Max.
VDD quiescent current IVDDQU1 0.5 0.9 1.2 mA OUT = high, VDD = 12 V
VDD quiescent current IVDDQU2 0.3 0.5 0.7 mA OUT = low, VDD = 12 V

Table 13 Undervoltage lockout for logic level MOSFET

Parameter Symbol Values Unit Note or Test Condition
Min. Typ. Max.
Undervoltage Lockout (UVLO) UVLOON – 4.2 4.5 V –
turn on threshold
Undervoltage Lockout (UVLO) UVLOOFF 3.6 3.9 – V –
turn off threshold
UVLO threshold hysteresis UVLOHYS 0.25 0.3 0.35 V –

Table 14 Undervoltage lockout for standard and superjunction MOSFET version

Parameter Symbol Values Unit Note or Test Condition
Min. Typ. Max.
Undervoltage Lockout (UVLO) UVLOON – 8.0 8.6 V –
turn on threshold
Undervoltage Lockout (UVLO) UVLOOFF 6.5 7.0 – V –
turn off threshold
UVLO threshold hysteresis UVLOHYS 0.8 1.0 1.2 V –

Datasheet 15 Rev.1.0
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Dual-channel 5 A and 4 A, high-speed, low-side gate driver ICs
Electrical characteristics

Table 15 Logic inputs INA, INB, ENA, ENB

Parameter Symbol Values Unit Note or Test Condition
Min. Typ. Max.
Input voltage threshold for VINH 1.9 2.1 2.3 V –
transition LH
Input voltage threshold for VINL 1.0 1.2 1.4 V –
transition HL
1)
Input pull up resistor RINH – 400 – kΩ
2)
Input pull down resistor RINL – 100 – kΩ
1) Inputs with initial high logic level
2) Inputs with initial low logic level

Table 16 Static output characteristics for 2EDN753x, 2EDN853x

Parameter Symbol Values Unit Note or Test Condition
Min. Typ. Max.
High level (sourcing) output RONSRC 0.4 0.8 1.4 Ω ISRC = 50 mA
resistance
High level (sourcing) output ISRCPEAK – 5.0 – A –
current 1)
Low level (sinking) output RONSNK 0.35 0.6 1.2 Ω ISNK = 50 mA
resistance
Low level (sinking) output ISNKPEAK – -5.0 – A –
current 1)
1) Parameter is not subject to production test - verified by design/characterization

Table 17 Static output characteristics for 2EDN743x

Parameter Symbol Values Unit Note or Test Condition
Min. Typ. Max.
High level (sourcing) output RONSRC 0.5 1.0 1.7 Ω ISRC = 50 mA
resistance
High level (sourcing) output ISRCPEAK – 4.0 – A –
current 1)
Low level (sinking) output RONSNK 0.4 0.8 1.45 Ω ISNK = 50 mA
resistance
Low level (sinking) output ISNKPEAK – -4.0 – A –
current 1)
1) Parameter is not subject to production test - verified by design/characterization

Datasheet 16 Rev.1.0
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Dual-channel 5 A and 4 A, high-speed, low-side gate driver ICs
Electrical characteristics

Table 18 Dynamic Characteristics (see Figure 9, Figure 10, Figure 11 and Figure 12)
Parameter Symbol Values Unit Note or Test Condition
Min. Typ. Max.
Input/Enable to output tPDlh 15 19 25 ns CLOAD= 1.8 nF, VDD= 12 V;
propagation delay low to high transition at
Input/Enable
Input/Enable to output tPDhl 15 19 25 ns CLOAD= 1.8 nF, VDD= 12 V
propagation delay high to low transition at
Input/Enable
Input/Enable to output ∆tPD – – 2 ns –
propagation delay mismatch
between the two channels on
the same IC
Rise time 1) tRISE – 8.6 15 ns CLOAD = 1.8 nF, VDD = 12 V
Fall time 1) tFAll – 6 13 ns CLOAD = 1.8 nF, VDD = 12 V
Minimum input pulse width tPW – 6 10 ns CLOAD = 1.8 nF, VDD = 12 V
that changes output state 1)
VDD start-up time 1) tSTART – 1.8 – µs VDD rising to 12 V;
from UVLOON to OUTx see Figure 11
VDD deactivation time 1) tSTOP – 500 – ns VDD falling from 12 V;
from UVLOOFF to OUTx see Figure 11
Activation time of output tCLAMP,OUT – 20 – ns see Figure 13
clamping in UVLO condition 1)
1) Parameter is not subject to production test - verified by component verification

Datasheet 17 Rev.1.0
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Dual-channel 5 A and 4 A, high-speed, low-side gate driver ICs
Timing diagrams

6 Timing diagrams
Figure 9 shows the definition of rise, fall and delay times for the inputs of the non-inverting/direct version (with
enable pin high or open).

ENx (high)
VIN H
VINL

VIN H
VINL
INx
90%

OUT 10%

TRIS E TFAL L
TPDON TPDOF F

Figure 9 Propagation delay, rise and fall time definition for the direct/non-inverting configuration

Figure 10 shows the definition of rise, fall and delay times for the inputs of the inverting version (with enable pins
high or open).

ENx (high)
VINH
VIN L

INx VINH
VINL

90%

OUT 10%

TRIS E TFAL L
TPDON TPDOF F

Figure 10 Propagation delay, rise and fall time definition for the inverting configuration

Datasheet 18 Rev.1.0
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EiceDRIVER™ 2EDN753x/2EDN853x/2EDN743x
Dual-channel 5 A and 4 A, high-speed, low-side gate driver ICs
Timing diagrams

Figure 11 illustrates the undervoltage lockout function.

INx High logic level

ENx High logic level

UVLOON
UVLOOFF

VDD

OUTx

tSTART,VDD tSTOP,VDD

Figure 11 UVLO behaviour, input ENx and INx drives OUTx normally high

Figure 12 illustrates the minimum input pulse width that changes output state.

ENx (high)
VIN H
VINL

VIN H
VINL
INx TPW

90%

OUTx

Figure 12 Minimum input pulse width definition

Datasheet 19 Rev.1.0
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EiceDRIVER™ 2EDN753x/2EDN853x/2EDN743x
Dual-channel 5 A and 4 A, high-speed, low-side gate driver ICs
Timing diagrams

Figure 13 illustrates tCLAMP,OUT, the time required to clamp potential output induced overshoots in UVLO
condition (VDD < UVLOON)

VDD 1.2 V

OUT

tCLAMP,OUT
Figure 13 Activation time of output clamping in UVLO conditions (unloaded output)

Datasheet 20 Rev.1.0
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EiceDRIVER™ 2EDN753x/2EDN853x/2EDN743x
Dual-channel 5 A and 4 A, high-speed, low-side gate driver ICs
Typical characteristics

7 Typical characteristics

Figure 14 Typical undervoltage lockout behavior vs. temperature for 2EDN7x (4 V)

Figure 15 Typical undervoltage lockout behavior vs. temperature for 2EDN8x (8 V)

Datasheet 21 Rev.1.0
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EiceDRIVER™ 2EDN753x/2EDN853x/2EDN743x
Dual-channel 5 A and 4 A, high-speed, low-side gate driver ICs
Typical characteristics

Figure 16 Input characteristics (INx and ENx)

Figure 17 Propagation delay (INx) on different input logic levels (see Figure 9)

Datasheet 22 Rev.1.0
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EiceDRIVER™ 2EDN753x/2EDN853x/2EDN743x
Dual-channel 5 A and 4 A, high-speed, low-side gate driver ICs
Typical characteristics

Figure 18 Propagation delay (ENx) on different input logic levels (see Figure 10)

Figure 19 Rise/fall times with load on output (see Figure 9)

Datasheet 23 Rev.1.0
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EiceDRIVER™ 2EDN753x/2EDN853x/2EDN743x
Dual-channel 5 A and 4 A, high-speed, low-side gate driver ICs
Typical characteristics

Figure 20 Power consumption related to temperature and power supply

Figure 21 Current consumption versus frequency

Datasheet 24 Rev.1.0
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EiceDRIVER™ 2EDN753x/2EDN853x/2EDN743x
Dual-channel 5 A and 4 A, high-speed, low-side gate driver ICs
Application and implementation

8 Application and implementation

Note: The following information is given as an example for the implementation of the device only and shall
not be regarded as a description or warranty of a certain functionality, condition or quality of the device

Figure 22 and Figure 23 show typical applications for the 8-pin and 6-pin package versions respectively.

DSO, TSSOP, WSON 8-pins

Load1 Load2
ENB VDD
M1

ENA 1 ENA ENB 8

Rg1
PWMA 2 INA OUTA 7

33 GND VDD 6
M2
Rg2
PWMB 44 INB OUTB 5

CVDD

GND

Figure 22 Typical application for 8-pin packages

Load1 Load2
SOT23 6-pins

VDD M1

Rg1
PWMA 42 INA OUTA 37

PWMB 53 INB GND 26 M2

Rg2
64 VDD OUTB 15

CVDD

GND GND

Figure 23 Typical application for 6-pin packages

Datasheet 25 Rev.1.0
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EiceDRIVER™ 2EDN753x/2EDN853x/2EDN743x
Dual-channel 5 A and 4 A, high-speed, low-side gate driver ICs
Package outlines

9 Package outlines
Note: For further information on package types, recommendation for board assembly, please go to:
Infineon packages.

9.1 Device numbers and markings

Table 19 Product versions

Part number Orderable part number (OPN) Device marking
2N7534AF
2EDN7534F 2EDN7534FXTMA1 EiceDRIV
XXHYYWW
2N7434AF
2EDN7434F 2EDN7434FXTMA1 EiceDRIV
XXHYYWW
2N7533AF
2EDN7533F 2EDN7533FXTMA1 EiceDRIV
XXHYYWW
2N8534AF
2EDN8534F 2EDN8534FXTMA1 EiceDRIV
XXHYYWW
2N8533AF
2EDN8533F 2EDN8533FXTMA1 EiceDRIV
XXHYYWW
2N7534
2EDN7534R 2EDN7534RXTMA1 AR
HYYWW
2N7434
2EDN7434R 2EDN7434RXTMA1 AR
HYYWW
2N7533
2EDN7533R 2EDN7533RXTMA1 AR
HYYWW
2N8534
2EDN8534R 2EDN8534RXTMA1 AR
HYYWW
2N8533
2EDN8533R 2EDN8533RXTMA1 AR
HYYWW
2N7534
2EDN7534G 2EDN7534GXTMA1 AG
HYYWW
YW1)
2EDN7534B 2EDN7534BXTSA1
754
YW1)
2EDN7533B 2EDN7533BXTSA1
753
1) The date code digits "Y" and "W" in device marking for the SOT23-6 package are explained in Table 20 and Table 21

Datasheet 26 Rev.1.0
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EiceDRIVER™ 2EDN753x/2EDN853x/2EDN743x
Dual-channel 5 A and 4 A, high-speed, low-side gate driver ICs
Package outlines

Table 20 Year date code marking - digit “Y”

Year Y Year Y Year Y
2000 0 2010 0 2020 0
2001 1 2011 1 2021 1
2002 2 2012 2 2022 2
2003 3 2013 3 2023 3
2004 4 2014 4 2024 4
2005 5 2015 5 2025 5
2006 6 2016 6 2026 6
2007 7 2017 7 2027 7
2008 8 2018 8 2028 8
2009 9 2019 9 2029 9

Table 21 Week date code marking - digit “W”

Week W Week W Week W Week W Week W
1 A 12 N 23 4 34 h 45 v
2 B 13 P 24 5 35 j 46 x
3 C 14 Q 25 6 36 k 47 y
4 D 15 R 26 7 37 l 48 z
5 E 16 S 27 a 38 n 49 8
6 F 17 T 28 b 39 p 50 9
7 G 18 U 29 c 40 q 51 2
8 H 19 V 30 d 41 r 52 3
9 J 20 W 31 e 42 s – –
10 K 21 Y 32 f 43 t – –
11 L 22 Z 33 g 44 u – –

Datasheet 27 Rev.1.0
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EiceDRIVER™ 2EDN753x/2EDN853x/2EDN743x
Dual-channel 5 A and 4 A, high-speed, low-side gate driver ICs
Package outlines

9.2 PG-DSO-8

Figure 24 PG-DSO-8 outline

Datasheet 28 Rev.1.0
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EiceDRIVER™ 2EDN753x/2EDN853x/2EDN743x
Dual-channel 5 A and 4 A, high-speed, low-side gate driver ICs
Package outlines

Figure 25 PG-DSO-8 footprint

8 0.3
12 ±0.3
5.2

6.4 1.75
2.1

Figure 26 PG-DSO-8 packaging

Datasheet 29 Rev.1.0
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EiceDRIVER™ 2EDN753x/2EDN853x/2EDN743x
Dual-channel 5 A and 4 A, high-speed, low-side gate driver ICs
Package outlines

9.3 PG-TSSOP-8

Figure 27 PG-TSSOP-8 outline

Figure 28 PG-TSSOP-8 footprint

Datasheet 30 Rev.1.0
2021-10-29
EiceDRIVER™ 2EDN753x/2EDN853x/2EDN743x
Dual-channel 5 A and 4 A, high-speed, low-side gate driver ICs
Package outlines

Figure 29 PG-TSSOP-8 packaging

Datasheet 31 Rev.1.0
2021-10-29
EiceDRIVER™ 2EDN753x/2EDN853x/2EDN743x
Dual-channel 5 A and 4 A, high-speed, low-side gate driver ICs
Package outlines

9.4 PG-WSON-8

67$1' 2))
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%27720 9,(:

[
s  $ % &
&
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6($7,1*
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3/$1( &23/$1$5,7<

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s


,1'(;
  0$5.,1*
s
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/$6(5('

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7+( '5$:,1* ,6 ,1 &203/,$1&( :,7+ ,62  352-(&7,21 0(7+2'  > @

Figure 30 PG-WSON-8 outline

 

 [    [  

 [ 









 [ 
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FRSSHU VROGHU PDVN VWHQFLO DSHUWXUHV

Figure 31 PG-WSON-8 footprint

Datasheet 32 Rev.1.0
2021-10-29
EiceDRIVER™ 2EDN753x/2EDN853x/2EDN743x
Dual-channel 5 A and 4 A, high-speed, low-side gate driver ICs
Package outlines

PIN 1 4 0.3
INDEX MARKING

12
3.35
Min. 0.95
3.35 Max. 1.25

ALL DIMENSIONS ARE IN UNITS MM

THE DRAWING IS IN COMPLIANCE WITH ISO 128 & PROJECTION METHOD 1 [ ]

Figure 32 PG-WSON-8 packaging

9.5 PG-SOT23-6
s

 
67$1' 2))

 


 & $% [  & ' [

*$8*(
3/$1(
s



s

r 


r

s
&  &
6($7,1* &23/$1$5,7<   & [
3/$1( '
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%
0$5.,1*


 '2(6 127 ,1&/8'( 3/$67,& 25 0(7$/ 3527586,21 2)  0$; 3(5 6,'(
$// ',0(16,216 $5( ,1 81,76 00
7+( '5$:,1* ,6 ,1 &203/,$1&( :,7+ ,62  352-(&7,21 0(7+2'  > @

Figure 33 PG-SOT23-6 outline

Datasheet 33 Rev.1.0
2021-10-29
EiceDRIVER™ 2EDN753x/2EDN853x/2EDN743x
Dual-channel 5 A and 4 A, high-speed, low-side gate driver ICs
Package outlines

0.95 0.5 0.95 0.5

0.8
0.8
1.2

1.2
1.2

1.2
copper solder mask stencil apertures

All dimensions are in units mm

Figure 34 PG-SOT23-6 footprint

4
8
3.2

0.25
PIN 1
INDEX MARKING 3.3 1.55

All dimensions are in units mm

The drawing is in compliance with ISO 128-30, Projection Method 1 [ ]

Figure 35 PG-SOT23-6 packaging

Datasheet 34 Rev.1.0
2021-10-29
EiceDRIVER™ 2EDN753x/2EDN853x/2EDN743x
Dual-channel 5 A and 4 A, high-speed, low-side gate driver ICs
Revision history

10 Revision history

Version Date Changes

Rev.1.0 2021-10-29 Datasheet release

Datasheet 35 Rev.1.0
2021-10-29
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Published by
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Infineon Technologies AG With respect to any examples, hints or any typical
81726 Munich, Germany values stated herein and/or any information regarding
the application of the product, Infineon Technologies WARNINGS
hereby disclaims any and all warranties and liabilities
© 2021 Infineon Technologies AG. of any kind, including without limitation warranties of Due to technical requirements products may contain
All Rights Reserved. non-infringement of intellectual property rights of any dangerous substances. For information on the types
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In addition, any information given in this document is Technologies office.
Do you have a question about any subject to customer's compliance with its obligations
aspect of this document? stated in this document and any applicable legal Except as otherwise explicitly approved by Infineon
Email: [email protected] requirements, norms and standards concerning Technologies in a written document signed by
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Infineon Technologies in customer's applications. Infineon Technologies’ products may not be used in
The data contained in this document is exclusively any applications where a failure of the product or any
Document reference consequences of the use thereof can reasonably be
intended for technically trained staff. It is the
EiceDRIVER™ responsibility of customer's technical departments to expected to result in personal injury.
2EDN753x/2EDN853x/2EDN743x evaluate the suitability of the product for the intended
application and the completeness of the product
information given in this document with respect to
such application.