Appendix A − VHDL Summary Page 1 of 21

Appendix A VHDL Summary ............................................................................................................................... 2

A.1 Basic Language Elements ............................................................................................................................. 2
A.1.1 Comments ............................................................................................................................................. 2
A.1.2 Identifiers .............................................................................................................................................. 2
A.1.3 Data Objects.......................................................................................................................................... 2
A.1.4 Data Types ............................................................................................................................................ 2
A.1.5 Data Operators ...................................................................................................................................... 4
A.1.6 ENTITY ................................................................................................................................................ 5
A.1.7 ARCHITECTURE ................................................................................................................................ 6
A.1.8 PACKAGE............................................................................................................................................ 7
A.2 Dataflow Model Concurrent Statements ....................................................................................................... 8
A.2.1 Concurrent Signal Assignment.............................................................................................................. 8
A.2.2 Conditional Signal Assignment............................................................................................................. 9
A.2.3 Selected Signal Assignment .................................................................................................................. 9
A.2.4 Dataflow Model Example ................................................................................................................... 10
A.3 Behavioral Model Sequential Statements.................................................................................................... 10
A.3.1 PROCESS ........................................................................................................................................... 10
A.3.2 Sequential Signal Assignment............................................................................................................. 10
A.3.3 Variable Assignment ........................................................................................................................... 11
A.3.4 WAIT .................................................................................................................................................. 11
A.3.5 IF THEN ELSE ................................................................................................................................... 11
A.3.6 CASE .................................................................................................................................................. 12
A.3.7 NULL .................................................................................................................................................. 12
A.3.8 FOR..................................................................................................................................................... 12
A.3.9 WHILE................................................................................................................................................ 13
A.3.10 LOOP .................................................................................................................................................. 13
A.3.11 EXIT ................................................................................................................................................... 13
A.3.12 NEXT .................................................................................................................................................. 13
A.3.13 FUNCTION ........................................................................................................................................ 13
A.3.14 PROCEDURE ..................................................................................................................................... 14
A.3.15 Behavioral Model Example................................................................................................................. 15
A.4 Structural Model Statements ....................................................................................................................... 16
A.4.1 COMPONENT Declaration ................................................................................................................ 16
A.4.2 PORT MAP......................................................................................................................................... 16
A.4.3 OPEN .................................................................................................................................................. 17
A.4.4 GENERATE........................................................................................................................................ 17
A.4.5 Structural Model Example .................................................................................................................. 17
A.5 Conversion Routines ................................................................................................................................... 18
A.5.1 CONV_INTEGER()............................................................................................................................ 18
A.5.2 CONV_STD_LOGIC_VECTOR(,) .................................................................................................... 19
Index ....................................................................................................................................................................... 20

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Appendix A VHDL Summary

VHDL is a hardware description language for modeling digital circuits that can range from simple connection
of gates to complex systems. VHDL is an acronym for VHSIC Hardware Description Language, and VHSIC in turn
is an acronym for Very High Speed Integrated Circuits. This appendix gives a brief summary of the basic VHDL
elements and its syntax. Many advance features of the language are omitted. Interested readers should refer to other
references for detail coverage.

A.1 Basic Language Elements

A.1.1 Comments
Comments are preceded by two consecutive hyphens ( -- ) and are terminated at the end of the line.
Example:

-- This is a comment

A.1.2 Identifiers
VHDL identifier syntax:
• A sequence of one or more upper case letters, lower case letters, digits, and the underscore.
• Upper and lower case letters are treated the same, i.e. case insensitive.
• The first character must be a letter.
• The last character cannot be the underscore.
• Two underscores cannot be together.

A.1.3 Data Objects

There are three kinds of data objects: signals, variables, and constants.
The data object SIGNAL represents logic signals on a wire in the circuit. A signal does not have memory, thus, if
the source of the signal is removed, the signal will not have a value.
A VARIABLE object remembers its content and is used for computations in a behavioral model.
A CONSTANT object must be initialized with a value when declared and this value cannot be changed.
Example:

SIGNAL x: BIT;
VARIABLE y: INTEGER;
CONSTANT one: STD_LOGIC_VECTOR(3 DOWNTO 0) := "0001";

A.1.4 Data Types

BIT and BIT_VECTOR

The BIT and BIT_VECTOR types are predefined in VHDL. Objects of these types can have the values ‘0’ or ‘1’.
The BIT_VECTOR type is simply a vector of type BIT.
Example:

SIGNAL x: BIT;
SIGNAL y: BIT_VECTOR(7 DOWNTO 0);

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x <= '1';
y <= "0010";

STD_LOGIC and STD_LOGIC_VECTOR

The STD_LOGIC and STD_LOGIC_VECTOR types provide more values than the BIT type for modeling a real circuit
more accurately. Objects of these types can have the following values:
‘0’ − normal 0.
‘1’ − normal 1.
‘Z’ − high impedance.
‘−’ − don’t care.
‘L’ − weak 0.
‘H’ − weak 1.
‘U’ − uninitialized.
‘X’ − unknown.
‘W’ − weak unknown.

The STD_LOGIC and STD_LOGIC_VECTOR types are not predefined and so the two library statements must be
included in order to use these types:

LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
If objects of type STD_LOGIC_VECTOR are to be used as binary numbers in arithmetic manipulations, then either
one of the following two USE statements must also be included:

USE ieee.std_logic_signed.ALL;

for signed number arithmetic or

USE ieee.std_logic_unsigned.all;

for unsigned number arithmetic.

Example:

LIBRARY ieee;
USE ieee.std_logic_1164.ALL;

SIGNAL x: STD_LOGIC;
SIGNAL y: STD_LOGIC_VECTOR(7 DOWNTO 0);

x <= 'Z';
y <= "001-";

INTEGER

The predefined INTEGER type defines binary number objects for use with arithmetic operators. By default, an
INTEGER signal uses 32 bits to represent a signed number. Integers using fewer bits can also be declared with the
RANGE keyword.

Example:

SIGNAL x: INTEGER;

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SIGNAL y: INTEGER RANGE –64 to 64;

BOOLEAN

The predefined BOOLEAN type defines objects having the two values TRUE and FALSE.
Example:

SIGNAL x: BOOLEAN;

Enumeration TYPE

An enumeration type allows the user to specify the values that the data object can have.
Syntax:
TYPE identifier IS (value1, value2, … );
Example:

TYPE state_type IS (S1, S2, S3);

SIGNAL state: state_type;
state <= S1;

ARRAY

The ARRAY type groups single data objects of the same type together into a one or multi- dimensional array.
Syntax:
TYPE identifier IS ARRAY (range) OF type;
Example:

TYPE byte IS ARRAY(7 DOWNTO 0) OF BIT;

TYPE memory_type IS ARRAY(1 TO 128) OF byte;
SIGNAL memory: memory_type;
memory(3) <= "00101101";

SUBTYPE

A SUBTYPE is a subset of a type, that is, a type with a range constraint.

Syntax:
SUBTYPE identifier IS type RANGE range;
Example:

SUBTYPE integer4 IS INTEGER RANGE –8 TO 7;

SUBTYPE cell IS STD_LOGIC_VECTOR(3 DOWNTO 0);

TYPE memArray IS ARRAY(0 TO 15) OF cell;

A.1.5 Data Operators

The VHDL Built-in operators are listed below.

Logical Operators Operation Example

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AND and a AND b

OR or a OR b
NOT not NOT a
NAND nand a NAND b
NOR nor a NOR b
XOR xor a XOR b
XNOR xnor a XNOR b

Arithmetic Operators
+ addition a+b
– subtraction a–b
* multiplication a*b
/ division a/b
MOD modulus a MOD b
REM remainder a REM b
** exponentiation a ** 2
& concatenation 'a' & 'b'
ABS absolute

Relational Operators
= equal
/= not equal
< less than
<= less than or equal
> greater than
>= greater than or equal

Shift Operators
sll shift left logical
srl shift right logical
sla shift left arithmetic
sra shift right arithmetic
rol rotate left
ror rotate right

A.1.6 ENTITY
An ENTITY declaration declares the external or user interface of the module similar to the declaration of a
function. It specifies the name of the entity and its interface. The interface consists of the signals to be passed into
the entity or out from it.
Syntax:

ENTITY entity-name IS
PORT (list-of-port-names-and-types);
END entity-name;
Example:

ENTITY Siren IS PORT (

M: IN BIT;
D: IN BIT;
V: IN BIT;
S: OUT BIT);
END Siren;

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A.1.7 ARCHITECTURE
The ARCHITECTURE body defines the actual implementation of the functionality of the entity. This is similar to
the definition or implementation of a function. The syntax for the architecture varies depending on the model
(dataflow, behavioral, or structural) you use.
Syntax for dataflow model::

ARCHITECTURE architecture-name OF entity-name IS

signal-declarations;
BEGIN
concurrent-statements;
END architecture-name;
The concurrent-statements are executed concurrently.
Example:

ARCHITECTURE Siren_Dataflow OF Siren IS

SIGNAL term_1: BIT;
BEGIN
term_1 <= D OR V;
S <= term_1 AND M;
END Siren_Dataflow;
Syntax for behavioral model:

ARCHITECTURE architecture-name OF entity-name IS

signal-declarations;
function-definitions;
procedure-definitions;
BEGIN
PROCESS-blocks;
concurrent-statements;
END architecture-name;
Statements within the process-block are executed sequentially. However, the process-block itself is a concurrent
statement.
Example:

ARCHITECTURE Siren_Behavioral OF Siren IS

SIGNAL term_1: BIT;
BEGIN
PROCESS (D, V, M)
BEGIN
term_1 <= D OR V;
S <= term_1 AND M;
END PROCESS;
END Siren_Behavioral;
Syntax for structural model

ARCHITECTURE architecture-name OF entity-name IS

component-declarations;
signal-declarations;
BEGIN
instance-name: PORT MAP-statements;
concurrent-statements;

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END architecture-name;
For each component declaration used, there must be a corresponding entity and architecture for that component.
The PORT MAP statements are concurrent statements.
Example:

ARCHITECTURE Siren_Structural OF Siren IS

COMPONENT myOR PORT (
in1, in2: IN BIT;
out1: OUT BIT);
END COMPONENT;

SIGNAL term1: BIT;

BEGIN
U0: myOR PORT MAP (D, V, term1);
S <= term1 AND M;
END Siren_Structural;

A.1.8 PACKAGE
A PACKAGE provides a mechanism to group together and share declarations that are used by several entity units.
A package itself includes a declaration and, optionally, a body. The package declaration and body are usually stored
together in a separate file from the rest of the design units. The file name given for this file must be the same as the
package name. In order for the complete design to synthesize correctly using MAX+PLUS II, you must first
synthesize the package as a separate unit. After that you can synthesize the unit that uses that package.

PACKAGE Declaration and Body

The PACKAGE declaration contains declarations that may be shared between different entity units. It provides the
interface, that is, items that are visible to the other entity units. The optional PACKAGE BODY contains the
implementations of the functions and procedures that are declared in the PACKAGE declaration.
Syntax for PACKAGE declaration:
PACKAGE package-name IS
type-declarations;
subtype-declarations;
signal-declarations;
variable-declarations;
constant-declarations;
component-declarations;
function-declarations;
procedure-declarations;
END package-name;
Syntax for PACKAGE body:
PACKAGE BODY package-name IS
function-definitions; -- for functions declared in the package declaration
procedure-definitions; -- for procedures declared in the package declaration
END package-name;

Example:

LIBRARY ieee;
USE ieee.std_logic_1164.ALL;

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PACKAGE my_package IS
SUBTYPE bit4 IS std_logic_vector(3 DOWNTO 0);
FUNCTION Shiftright (input: IN bit4) RETURN bit4; -- declare a function
SIGNAL mysignal: bit4; -- a global signal
END my_package;

PACKAGE BODY my_package IS

-- implementation of the Shiftright function
FUNCTION Shiftright (input: IN bit4) RETURN bit4 IS
BEGIN
RETURN '0' & input(3 DOWNTO 1);
END shiftright;
END my_package;

Using a PACKAGE

To use a package, you simply include a LIBRARY and USE statement for that package. Before synthesizing the
module that uses the package, you need to first synthesize the package by itself as a top-level entity.
Syntax:
LIBRARY WORK;
USE WORK.package-name.ALL;
Example:

LIBRARY work;
USE work.my_package.ALL;

ENTITY test_package IS PORT (

x: IN bit4;
z: OUT bit4);
END test_package;

ARCHITECTURE Behavioral OF test_package IS

BEGIN
mysignal <= x;
z <= Shiftright(mysignal);
END Behavioral;

A.2 Dataflow Model Concurrent Statements

Concurrent statements used in the dataflow model are executed concurrently. Hence, the ordering of these
statements does not affect the resulting output.

A.2.1 Concurrent Signal Assignment

Assigns a value or the result of evaluating an expression to a signal. This statement is executed whenever a
signal in its expression changes value. However, the actual assignment of the value to the signal takes place after a
certain delay and not instantaneously as for variable assignments.
Syntax:

signal <= expression;

Example:

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y <= '1';
z <= y AND (NOT x);

A.2.2 Conditional Signal Assignment

Selects one of several different values to assign to a signal based on different conditions. This statement is
executed whenever a signal in any one of the value or condition changes.
Syntax:

signal <= value1 WHEN condition ELSE

value2 WHEN condition ELSE
…
value3;
Example:

z <= in0 WHEN sel = "00" ELSE

in1 WHEN sel = "01" ELSE
in2 WHEN sel = "10" ELSE
in3;

A.2.3 Selected Signal Assignment

Selects one of several different values to assign to a signal based on the value of a select expression. This
statement is executed whenever a signal in the expression or any one of the value changes.
Syntax:

WITH expression SELECT

signal <= value1 WHEN choice1,
value2 WHEN choice2 | choice3,
…
value4 WHEN choice4;
All possible choices for the expression must be given. The keyword OTHERS can be used to denote all remaining
choices.
Example:

WITH sel SELECT

z <= in0 WHEN "00",
in1 WHEN "01",
in2 WHEN "10",
in3 WHEN OTHERS;

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A.2.4 Dataflow Model Example

-- outputs a 1 if the 4-bit input is a prime number, 0 otherwise

ENTITY Prime IS PORT (
number: IN BIT_VECTOR(3 DOWNTO 0);
yes: OUT BIT);
END Prime;

ARCHITECTURE Prime_Dataflow OF Prime IS

BEGIN
WITH number SELECT
yes <= '1' WHEN "0001" | "0010",
'1' WHEN "0011" | "0101" | "0111" | "1011" | "1101",
'0' WHEN OTHERS;
END Prime_Dataflow;

A.3 Behavioral Model Sequential Statements

The behavioral model allows statements to be executed sequentially just like in a regular computer program.
Sequential statements include many of the standard constructs such as variable assignments, if-then-else, and loops.

A.3.1 PROCESS
The PROCESS block contains statements that are executed sequentially. However, the PROCESS statement itself is
a concurrent statement. Multiple process blocks in an architecture will be executed simultaneously. These process
blocks can be combined together with other concurrent statements.
Syntax:

process-name: PROCESS (sensitivity-list)

variable-declarations;
BEGIN
sequential-statements;
END PROCESS process-name;
The sensitivity-list is a comma-separated list of signals in which the process is sensitive to. In other words,
whenever a signal in the list changes value, the process will be executed, that is, all the statements in the sequential
order listed. After the last statement has been executed, the process will be suspended until the next time that a
signal in the sensitivity list changes value before it is again executed.

Example:

PROCESS (D, V, M)
BEGIN
term_1 <= D OR V;
S <= term_1 AND M;
END PROCESS;

A.3.2 Sequential Signal Assignment

Assigns a value to a signal. This statement is just like its concurrent counterpart except that it is executed
sequentially, that is, only when execution reaches it.
Syntax:

signal <= expression;

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Example:

y <= '1';
z <= y AND (NOT x);

A.3.3 Variable Assignment

Assigns a value or the result of evaluating an expression to a variable. The value is always assigned to the
variable instantaneously whenever this statement is executed.
Variables are only declared within a process block.
Syntax:

signal := expression;

Example:

y := '1';
yn := NOT y;

A.3.4 WAIT
When a process has a sensitivity list, the process always suspends after executing the last statement. An
alternative to using a sensitivity list to suspend a process is to use a WAIT statement, which must also be the first
statement in a process1.
Syntax2:

WAIT UNTIL condition;

Example:

-- suspend until a rising clock edge

WAIT UNTIL clock’EVENT AND clock = '1';

A.3.5 IF THEN ELSE

Syntax:

IF condition THEN
sequential-statements1;
ELSE
sequential-statements2;
END IF;

IF condition1 THEN
sequential-statements1;
ELSIF condition2 THEN
sequential-statements2;
…
ELSE
sequential-statements3;

1
This is only a MAX+PLUS II restriction.
2
There are three different formats of the WAIT statement, however, MAX+PLUS II only supports one.

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END IF;

Example:

IF count /= 10 THEN -- not equal

count := count + 1;
ELSE
count := 0;
END IF;

A.3.6 CASE
Syntax:

CASE expression IS
WHEN choices => sequential-statements;
WHEN choices => sequential-statements;
…
WHEN OTHERS => sequential-statements;
END CASE;

Example:

CASE sel IS
WHEN "00" => z <= in0;
WHEN "01" => z <= in1;
WHEN "10" => z <= in2;
WHEN OTHERS => z <= in3;
END CASE;

A.3.7 NULL
The NULL statement does not perform any actions.
Syntax:

NULL;

A.3.8 FOR
Syntax:

FOR identifier IN start [TO | DOWNTO] stop LOOP

sequential-statements;
END LOOP;
Loop statements must have locally static bounds3. The identifier is implicitly declared, so no explicit declaration
of the variable is needed.

Example:

sum := 0;
FOR count IN 1 TO 10 LOOP
sum := sum + count;

3
This is only a MAX+PLUS II restriction.

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END LOOP;

A.3.9 WHILE4
Syntax:

WHILE condition LOOP

sequential-statements;
END LOOP;

A.3.10 LOOP4
Syntax:

LOOP
sequential-statements;
EXIT WHEN condition;
END LOOP;

A.3.11 EXIT4
The EXIT statement can only be used inside a loop. It causes execution to jump out of the innermost loop and is
usually used in conjunction with the LOOP statement.
Syntax:

EXIT WHEN condition;

A.3.12 NEXT
The NEXT statement can only be used inside a loop. It causes execution to skip to the end of the current iteration
and continue with the beginning of the next iteration. It is usually used in conjunction with the FOR statement.
Syntax:

NEXT WHEN condition;

Example:

sum := 0;
FOR count IN 1 TO 10 LOOP
NEXT WHEN count = 3;
sum := sum + count;
END LOOP;

A.3.13 FUNCTION
Syntax for function declaration:

4
Not supported by MAX+PLUS II.

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FUNCTION function-name (parameter-list) RETURN return-type;

Syntax for function definition:
FUNCTION function-name (parameter-list) RETURN return-type IS
BEGIN
sequential-statements;
END function-name;
Syntax for function call:
function-name (actuals);
Parameters in the parameter-list can be either signals or variables of mode IN only.
Example:

LIBRARY ieee;
USE ieee.std_logic_1164.ALL;

ENTITY test_function IS PORT (

x: IN std_logic_vector(3 DOWNTO 0);
z: OUT std_logic_vector(3 DOWNTO 0));
END test_function;

ARCHITECTURE Behavioral OF test_function IS

SUBTYPE bit4 IS std_logic_vector(3 DOWNTO 0);

FUNCTION Shiftright (input: IN bit4) RETURN bit4 IS

BEGIN
RETURN '0' & input(3 DOWNTO 1);
END shiftright;

SIGNAL mysignal: bit4;

BEGIN
PROCESS
BEGIN
mysignal <= x;
z <= Shiftright(mysignal);
END PROCESS;
END Behavioral;

A.3.14 PROCEDURE
Syntax for procedure declaration:
PROCEDURE procedure -name (parameter-list);
Syntax for procedure definition:
PROCEDURE procedure-name (parameter-list) IS
BEGIN
sequential-statements;
END procedure-name;
Syntax for procedure call:
procedure -name (actuals);
Parameters in the parameter-list are variables of modes IN, OUT, or INOUT.

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Example:

LIBRARY ieee;
USE ieee.std_logic_1164.ALL;

ENTITY test_procedure IS PORT (

x: IN std_logic_vector(3 DOWNTO 0);
z: OUT std_logic_vector(3 DOWNTO 0));
END test_procedure;

ARCHITECTURE Behavioral OF test_procedure IS

SUBTYPE bit4 IS std_logic_vector(3 DOWNTO 0);

PROCEDURE Shiftright (input: IN bit4; output: OUT bit4) IS

BEGIN
output := '0' & input(3 DOWNTO 1);
END shiftright;

BEGIN
PROCESS
VARIABLE mysignal: bit4;
BEGIN
Shiftright(x, mysignal);
z <= mysignal;
END PROCESS;
END Behavioral;

A.3.15 Behavioral Model Example

LIBRARY ieee;
USE ieee.std_logic_1164.all;

ENTITY bcd IS PORT (

I: IN STD_LOGIC_VECTOR (3 DOWNTO 0);
Segs: OUT std_logic_vector (1 TO 7));
END bcd;

ARCHITECTURE Behavioral OF bcd IS

BEGIN
PROCESS(I)
BEGIN
CASE I IS
WHEN "0000" => Segs <= "1111110";
WHEN "0001" => Segs <= "0110000";
WHEN "0010" => Segs <= "1101101";
WHEN "0011" => Segs <= "1111001";
WHEN "0100" => Segs <= "0110011";
WHEN "0101" => Segs <= "1011011";
WHEN "0110" => Segs <= "1011111";
WHEN "0111" => Segs <= "1110000";
WHEN "1000" => Segs <= "1111111";
WHEN "1001" => Segs <= "1110011";
WHEN OTHERS => Segs <= "0000000";
END CASE;

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END PROCESS;
END Behavioral;

A.4 Structural Model Statements

The structural model allows the manual connection of several components together using signals. All
components used must first be defined with their respective ENTITY and ARCHITECTURE sections, which can be in the
same file or they can be in separate files.
In the topmost module, each component used in the netlist is first declared using the COMPONENT statement. The
declared components are then instantiated with the actual components in the circuit using the PORT MAP statement.
SIGNALs are then used to connect the components together according to the netlist.

A.4.1 COMPONENT Declaration

Declares the name and the interface of a component that is used in the circuit description. For each component
declaration used, there must be a corresponding entity and architecture for that component. The declaration name
and the interface must match exactly the name and interface that is specified in the entity section for that component.
Syntax:

COMPONENT component-name IS
PORT (list-of-port-names-and-types);
END COMPONENT;
Example:

COMPONENT half_adder IS PORT (

xi, yi, cin: IN BIT;
cout, si: OUT BIT);
END COMPONENT;

A.4.2 PORT MAP

The PORT MAP statement instantiates a declared component with an actual component in the circuit by
specifying how the connections to this instance of the component are to be made.
Syntax:

label: component-name PORT MAP (association-list);

The association-list can be specified using either the positional or named method.
Example (positional association):

SIGNAL x0, x1, y0, y1, c0, c1, c2, s0, s1: BIT;
U1: half_adder PORT MAP (x0, y0, c0, c1, s0);
U2: half_adder PORT MAP (x1, y1, c1, c2, s1);
Example (named association):

SIGNAL x0, x1, y0, y1, c0, c1, c2, s0, s1: BIT;
U1: half_adder PORT MAP (cout=>c1, si=>s0, cin=>c0, xi=>x0, yi=>y0);
U2: half_adder PORT MAP (cin=>c1, xi=>x1, yi=>y1, cout=>c2, si=>s1);

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A.4.3 OPEN
The OPEN keyword is used in the PORT MAP association-list to signify that that particular port is not connected or
used.
Example:

U1: half_adder PORT MAP (x0, y0, c0, OPEN, s0);

A.4.4 GENERATE
The GENERATE statement works like a macro expansion. It provides a simple way to duplicate similar
components.
Syntax:

label: FOR identifier IN start [TO | DOWNTO] stop GENERATE

port-map-statements;
END GENERATE label;

Example:

-- using a FOR-GENERATE statement to generate four instances of the full adder

-- component for a 4-bit adder
ENTITY Adder4 IS PORT (
Cin: IN BIT;
A, B: IN BIT_VECTOR(3 DOWNTO 0);
Cout: OUT BIT;
SUM: OUT BIT_VECTOR(3 DOWNTO 0));
END Adder4;

ARCHITECTURE Structural OF Adder4 IS

COMPONENT FA PORT (
ci, xi, yi: IN BIT;
co, si: OUT BIT);
END COMPONENT;

SIGNAL Carryv: BIT_VECTOR(4 DOWNTO 0);

BEGIN
Carryv(0) <= Cin;

Adder: FOR k IN 3 DOWNTO 0 GENERATE

FullAdder: FA PORT MAP (Carryv(k), A(k), B(k), Carryv(k+1), SUM(k));
END GENERATE Adder;

Cout <= Carryv(4);

END Structural;

A.4.5 Structural Model Example

This example is based on the following circuit:

D
V S
M

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-- declare and define the 2-input OR gate

LIBRARY ieee;
USE ieee.std_logic_1164.ALL;

ENTITY myOR IS PORT (

in1, in2: IN STD_LOGIC;
out1: OUT STD_LOGIC);
END myOR;

ARCHITECTURE OR_Dataflow OF myOR IS

BEGIN
out1 <= in1 OR in2;
END OR_Dataflow;

-- topmost module for the siren

LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
ENTITY Siren IS PORT (
M: IN STD_LOGIC;
D: IN STD_LOGIC;
V: IN STD_LOGIC;
S: OUT STD_LOGIC);
END Siren;

ARCHITECTURE Siren_Structural OF Siren IS

-- declaration of the needed OR gate
COMPONENT myOR PORT (
in1, in2: IN STD_LOGIC;
out1: OUT STD_LOGIC);
END COMPONENT;

-- signal for connecting the output of the OR gate

-- with the input to the AND gate
SIGNAL term1: STD_LOGIC;

BEGIN
U0: myOR PORT MAP (D, V, term1);
S <= term1 AND M;
-- note how we can have both PORT MAP and signal assignment statements
END Siren_Structural;

A.5 Conversion Routines

A.5.1 CONV_INTEGER()
Converts a std_logic_vector type to an integer;
Requires:
LIBRARY ieee;
USE ieee.std_logic_unsigned.ALL;
Syntax:
CONV_INTEGER(std_logic_vector)
Example:

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Appendix A − VHDL Summary Page 19 of 21

LIBRARY ieee;
USE ieee.std_logic_unsigned.ALL;

SIGNAL four_bit: STD_LOGIC_VECTOR(3 DOWNTO 0);

SIGNAL n: INTEGER;

n := CONV_INTEGER(four_bit);

A.5.2 CONV_STD_LOGIC_VECTOR(,)
Converts an integer type to a std_logic_vector type.
Requires:
LIBRARY ieee;
USE ieee.std_logic_arith.ALL;
Syntax:
CONV_STD_LOGIC_VECTOR (integer, number_of_bits)
Example:

LIBRARY ieee;
USE ieee.std_logic_arith.ALL;

SIGNAL four_bit: std_logic_vector(3 DOWNTO 0);

SIGNAL n: INTEGER;

four_bit := CONV_STD_LOGIC_VECTOR(n, 4);

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Appendix A − VHDL Summary Page 20 of 21

Index

A L
ARCHITECTURE, 6 LOOP, 13
ARRAY, 4
N
B
NEXT, 13
Behavioral model, 6, 10 NULL, 12
example, 16
BIT, 2 O
BIT_VECTOR, 2
OPEN, 17
BOOLEAN, 4
OTHERS, 12
C
P
CASE, 12
PACKAGE, 7
Comments, 2
PORT MAP, 16
COMPONENT declaration, 16
PROCEDURE, 14
Concurrent signal assignment, 8
PROCESS, 10
Concurrent statements, 8
Conditional signal assignment, 9
CONV_INTEGER, 18 S
CONV_STD_LOGIC_VECTOR, 19 Selected signal assignment, 9
Conversion routines, 18 Sequential signal assignment, 10
Sequential statements, 10
D Signal assignment
Data objects, 2 concurrent, 8
Data operators, 4 conditional, 9
selected, 9
Data types, 2
sequential, 10
Dataflow model, 6, 8
STD_LOGIC, 3
example, 10
STD_LOGIC_VECTOR, 3
DOWNTO, 12
Structural model, 6, 16
example, 17
E
SUBTYPE, 4
ELSIF, 11
ENTITY, 5 T
Enumeration, 4
TO, 12
EXIT, 13
V
F
FOR, 12 Variable assignment, 11
FUNCTION, 13 VHD
Conversion routines, 18
VHDL
G
Basic language elements, 2
GENERATE, 17 Behavioral model, 6, 10
example, 16
I Concurrent statements, 8
Dataflow model, 6, 8
Identifiers, 2 example, 10
IF THEN ELSE, 11
Sequential statements, 10
INTEGER, 3
Structural model, 6, 16

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Appendix A − VHDL Summary Page 21 of 21

example, 17 NEXT, 13
VHDL syntax NULL, 12
ARCHITECTURE, 6 OPEN, 17
ARRAY, 4 OTHERS, 12
BIT, 2 PACKAGE, 7
BIT_VECTOR, 2 PORT MAP, 16
BOOLEAN, 4 PROCEDURE, 14
CASE, 12 PROCESS, 10
Comments, 2 Signal assignment
COMPONENT declaration, 16 concurrent, 8
CONV_INTEGER, 18 conditional, 9
CONV_STD_LOGIC_VECTOR, 19 selected, 9
Data objects, 2 sequential, 10
Data operators, 4 STD_LOGIC, 3
Data types, 2 STD_LOGIC_VECTOR, 3
DOWNTO, 12 SUBTYPE, 4
ELSIF, 11 TO, 12
ENTITY, 5 Variable assignment, 11
Enumberation, 4 WAIT, 11
EXIT, 13 WHEN, 12
FOR, 12 WHILE, 13
FUNCTION, 13
GENERATE, 17 W
Identifiers, 2
WAIT, 11
IF THEN ELSE, 11
WHEN, 12
INTEGER, 3
LOOP, 13 WHILE, 13

Principles of Digital Logic Design Enoch Hwang Last updated 3/5/2003 5:22 PM