Ia Module 4 PLC Notes
Ia Module 4 PLC Notes
INDUSTRIAL AUTOMATION
COURSE CODE: 5042 (REV 2021)
PROGRAMMABLE LOGIC CONTROLLER
MODULE IV NOTES
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Architecture of PLC
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6. Peripheral devices
They are divided into several categories like programming aids, operational aids, I/O
enhancements and computer interface devices.
Programming aids provide documentation and program recording capabilities- can be done
using PC compatible software.
Operational aids include variety of resources like color graphics CRTs or other equipment
which can be used to monitor specific process variables
I/O enhancement group are special hardware modules that can be plugged into the PLC, which
provides intelligence and remote I/O capabilities.
Computer interface group provides PLC to PLC communication or network interaction with
various computer systems.
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Advantages of PLCs
1. Ease of programming and reprogramming in the plant
2. A programming language that is based on relay wiring symbols familiar to most plant
electric personnel.
3. High reliability and minimum maintenance
4. Ability to communicate with computer systems in the plant
5. Moderate to low initial investment cost
6. Rugged construction
7. Modular design
Applications of PLCs
1. They are used in glass manufacturing, for controlling the material ratio
2. They are used to control machines used for paper manufacturing
3. They are used to mix raw materials in the correct quantity, in cement manufacturing industry
4. They are used to control the wind turbines
5. They are used in boilers in thermal power plants
6. In process automation plants (mining, oil and gas)
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Comments –Comments are displayed at the start of each rung and are used to describe the
logical expressions and control operations that the rung, or groups of rungs, are executing.
Understanding ladder diagrams is made a lot easier by using comments.
Electrical devices are shown in their normal condition. Thus a switch, which is normally
open until some object closes it, is shown as open on the ladder diagram. A switch that is
normally closed is shown closed.
A particular device can appear in more than one rung of a ladder. The same letters and/or
numbers are used to label the device in each situation.
The inputs and outputs are all identified by their addresses, the notation used depending on
the PLC manufacturer. This is the address of the input or output in the memory of the PLC.
When the PLC is in its run mode, it goes through the entire ladder program to the end, the
end rung of the program being clearly denoted, and then promptly resumes at the start.
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Examples
Ladder logic to switch a bulb ON/OFF
In the ladder logic diagram we can see there is an input contact (N-O) “I0.0” which is a toggle
switch in the physical connections to the plc. There is also an output coil addressed as “Q0.0” which
can be a Motor, Bulb or any signaling device in the physical connection.
2. AND GATE
In AND Gate, when both inputs (I1 and I2) are high then the output (Q1) will be high. For all other
inputs, output (Q1) will be the low.
connecting two
s output. In the
lamp (Q1) will
2) are open then
Q1= I1 . I2
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3. OR GATE
Working: If both inputs are low in the OR gate, then the output will be low. For all other cases, the
output will be high.
In case both or anyone inputs (I1 and I2) are closed then coil (Q1) will on.
Q1=I1+I2
4. NAND GATE
NAND gate is operated as an AND gate and followed by the inverter. In NAND Gate, the output
will be low when both inputs are high. For all other
cases, the output will be high.
If both switches (I1 and I2) or anyone switch (I1 or I2) are closed, the lamp will be glow. In the
case, both switches are open then the lamp will not be glow.
5. NOR GATE
NOR Gate is operated OR Gate followed by the NOT
Gate. When both inputs are low then the output will be
high.
The Coil (Q1) will be activated if both inputs are closed. Coil (Q1) will be deactivated if any one
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6. EX-OR GATE
Working: If both inputs are same, the output will become low. For any other input condition, the
output will be high.
7. EX-NOR GATE
Working: When both inputs (I1 and I2) are same then the output will high.
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Half-Adder
A half adder can add two binary bits A and B. It has two outputs. One is sum and the other is carry.
The expression for sum is same as the EXOR gate expression and that of carry is same as AND
gate. The expressions are as given:
Half subtractor
This circuit is used to subtract one binary bit from another. There are two inputs A and B
and there are two outputs. One output is the difference and the other one is borrow. The expressions
are as given:
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ADD:
SUB:
SUB block is used to do the Subtraction of the two values
stored in source A and source B and store the output in
destination address. Value stored in N7:1 is subtracted from
the value stored in N7:0 and result is stored in N7:3.
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MUL:
DIV:
DIV block is used to do the Division of the two values stored in
source A and source B and store the output in destination address.
Value stored in N7:0 is divided by the value stored in N7:1 and result
is stored in the destination address.
SQR
SQR block is used to find the square root of the value stored
in source address and results the value in destination address.
The number whose square root is to be found is to be stored
in N7:0. The result of operation will be available at the
destination address N7:1.
NEQ:
NEQ block is used to negate the value stored in source
address and results the value in destination. The value
which is to be negated can be stored in N7:0. Result will be
available at the destination address N7:1.
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The GEQ instruction can be used to test whether one value (source
A) is greater than or equal to another (source B).
If the value at source A is greater than or equal to the value at source
B, the instruction is logically true.
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The LIM instruction can be used to test for values within or outside a
specified range, depending on how you set the limits.
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When the switch connected to input(S1) I:1/0 is first closed, timed output O:2/1 is set to 1
immediately and the lamp is switched on.
If this switch is now opened, logic continuity is lost and the timer begins counting.
After 15 s, when the accumulated time equals the preset time, the output is reset to 0 and the lamp
switches off.
Up counter example
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Down counter
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• With the program in the state shown, the CTD done bit will be set (1) and output 0:2/0 will be
energized because the accumulated value of 4 is greater than the preset value of 2.
• When the CTD instruction rung makes a false-to-true transition, the accumulated value decreases by
one count to 3.
• When the input rung condition makes another false-to-true transition, the accumulated value will
decreases to 2.
• When the input makes one more false-to true transition, the accumulated value will drop to 1.
• At this point the accumulated value of 1 is less than the preset value of 2 so the done bit will be reset
(0) de-energizing output O:2/0.
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• The section or zone being controlled begins with the first MCR instruction and ends with the second
MCR.
• When the first MCR instruction is false, or disabled, all rungs below it, in this case outputs M and
PL1, will be de-energized even if the programmed logic for each rung is true.
• Assume the motor M is running and the MCR instruction becomes disabled. The motor will
immediately become de-energized and stop operating. When the MCR instruction then become
enabled, the motor will not revert back to its previous
Jump Instruction
In PLC programming it is sometimes desirable to be able to jump over certain program instructions
when certain conditions exist. The jump (JMP) instruction is an output instruction used for this purpose.
When the jump instruction is used, the PLC will not execute the instructions of a rung that is jumped.
• The jump instruction with its associated label instruction (LBL) must have the same address..
• When the jump instruction is true, all logic between the jump and label instructions is bypassed and
the processor continues scanning after the LBL instruction.
The label instruction must be programmed as the first instruction on the rung where it resides
The label instruction is always true, and the remaining instructions on the rung must make up a
verifiable rung
The program of figure illustrates the use of a jump instruction
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Subroutine Functions
A subroutine is a short program that is used by the main program to perform a specific
function. Large programs are often broken into subroutine program files, which are called and executed
from the main program.
When a subroutine is called from the main program, the program is able to escape from the main
program and go to a program subroutine to perform certain functions and then return to the main
program. In situations in which a machine has a portion of its cycle that must be repeated several
times during one machine cycle, the subroutine can save a great deal of duplicate programming. The
sequence of rungs could be programmed one time into a subroutine and just called when needed.
The subroutine instructions can be summarized as follows:
Jump to Subroutine (JSR)—The JSR instruction redirects logic execution from the current ladder file
to the specific subroutine file. When rung conditions are true for this output instruction,
Subroutine (SBR)—The SBR instruction is the first input instruction on the first rung in the subroutine
file. It serves as an identifier that the program file is a subroutine. This file number is used in the JSR
instruction to identify the target to which the program should jump. It is always true, and although its
use is optional, it is still recommended.
Return (RET)—The RET instruction is an output instruction that marks the end of the subroutine file.
It causes the scan to return to the main program at the instruction following the JSR instruction where
it exited the program. The scan returns from the end of the file if there is no RET instruction. The rung
containing the RET instruction may be conditional if this rung precedes the end of the subroutine. In
this way, the processor omits the balance of a subroutine only if its rung condition is true.
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