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Memory

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13 views14 pages

Memory

Uploaded by

dhwanitvibhani
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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MEMORY ORGANIZATION

• Memory Hierarchy
• Main Memory
• Auxiliary Memory
• Cache Memory
• Associative Memory
• Virtual Memory
• Memory Management Hardware
Memory
• Memory is used to store data and
instructions.
Unit Description Power
Bit Smallest Unit (0 or 1) -
Nibble 4 bits -
Byte 8 bits -
1 KB (Kilo Byte) 1024 bytes 2 10
1 MB (Mega Byte) 1024 KB 2 20
1 GB (Giga Byte) 1024 MB 2 30
1 TB (Tera Byte) 1024 GB 2 40
1 PB (Peta Byte) 1024 TB 2 50
1 EB (Exa Byte) 1024 PB 2 60
1 ZB (Zetta Byte) 1024 EB 2 70
Types of Memory
• There are mainly 3 types of Memory
1) Primary or Main Memory
2) Secondary or Auxiliary Memory
3) Cache Memory

(1) Primary Memory :


– The memory unit that communicates directly with the CPU is called
primary or main memory.
– Primary Memory is an essential component of a computer system.
– Program and data are loaded into the primary memory before processing.
– CPU interacts directly with the primary memory to perform READ or
WRITE operations.
– There are two types of primary memory:
(1) RAM (Random Access Memory)
- RAM is a volatile memory that temporarily stores the files you are working on
and as the data
loses when the power is turned off.
- RAM is measured in megabytes and the speed is measured in nanoseconds and
RAM chips can read
data faster than ROM.
- Types of RAM: The two widely used forms of modern RAM are:
Static RAM (SRAM): which store the bit information in FlipFlop.
Dynamic RAM (DRAM) : which store the bit information on a
(2) ROM (Read Only Memory)
- ROM is non-volatile memory which means the information is stored
permanently on the chip.
- Non-volatile memory is used for parts of the computer that do not change,
such as the initial boot-up portion of the software.
- Types of ROM
1. PROM (Programmable read-only memory):
It can be programmed by user. Once programmed, the data and instructions
in it cannot be changed.
2. EPROM (Erasable Programmable read only memory):
It can be reprogrammed. To erase data from it, expose it to ultra violet
light. To reprogram it, erase all the previous data.
3. EEPROM (Electrically Erasable Programmable read only memory):
The data can be erased by applying electric field, no need of ultra violet
light. We can erase only portions of the chip.

(2) Secondary Memory:


- Devices that provide backup storage are called auxiliary memory or secondary memory.
- Secondary memory is non-volatile and has a large storage capacity than primary memory.
- It is slower and cheaper than the main/primary memory .
- It cannot be accessed directly by the CPU.
- Contents of secondary storage need to be first brought into the main memory for the CPU to access.
(3) Cache Memory:
- special very-high-speed memory to increase the processing speed.
- Act as buffer between RAM and CPU.
- It reduce the average time to access data from the main memory.
- It is costlier than main memory.
MEMORY HIERARCHY

Memory Hierarchy is to obtain the highest possible


access speed while minimizing the total cost of the memory system
Auxiliary memory
Magnetic
tapes I/O Main
processor memory
Magnetic
disks

CPU Cache
memory

Register

Cache

Main Memory

Magnetic Disk

Magnetic Tape
Typical RAM and ROM Chips
Typical RAM Chip 

128 = 27 
•A three-state buffer output can be placed in one of three
possible states: a signal equivalent to logic 1, a signal
equivalent to logic 0, or a high impedance state.
•The logic 1 and 0 are normal digital signals.
•The high impedance state behaves like an open circuit,
which means that the output does not carry a signal and
has no logic significance.
• The unit is in operation only when CS1 = 1 and CS2 = 0.
• The bar on top of the second select variable indicates
that this input is enabled when it is equal to 0.
Typical ROM Chip

512 = 29 
Memory Address Map

• Although there are 16 lines in the address bus, the table


shows only 10 lines because the other 6 are not used in
this example and assumed to be zero.
• The small x's under the address bus lines designate
those lines that must be connected to the address
inputs in each chip.
• The RAM chips have 128 bytes and need seven address
lines.
• The ROM chip has 512 bytes and needs 9 address lines.
• The x's are always assigned to the low-order bus lines:
lines 1 through 7 for the RAM and lines 1 through 9 for
the ROM.
• It is now necessary to distinguish between four RAM
chips by assigning to each a different address.
Example
• Assume computer needs 1024 bytes of memory (1024 x 8)
• 512 bytes of RAM by using 128 bytes RAM chips (128x 8)
&
• 512 bytes of ROM by using 512 bytes ROM chips (512x 8)
• To solve this,
1) No. of RAM chips = Total capacity of RAM / capacity of
single chip
= 512/128
= 4 chips
2) No. of ROM chips = Total capacity of ROM / capacity
of single chip
= 512/512
= 1 chip
Main Memory

MEMORY ADDRESS MAP


Address space assignment to each memory chip

Example: 512 bytes RAM and 512 bytes ROM

Hexa Address bus


Component address 10 9 8 7 6 5 4 3 2 1
RAM 1 0000 - 007F 0 0 0 x x x x x x x
RAM 2 0080 - 00FF 0 0 1 x x x x x x x
RAM 3 0100 - 017F 0 1 0 x x x x x x x
RAM 4 0180 - 01FF 0 1 1 x x x x x x x
ROM 0200 - 03FF 1 x x x x x x x x x

Memory Connection to CPU


- RAM and ROM chips are connected to a CPU
through the data and address buses

- The low-order lines in the address bus select


the byte within the chips and other lines in the
address bus select a particular chip through
its chip select inputs
Main Memory

CONNECTION OF MEMORY TO CPU


Address bus CPU
16-11 10 9 8 7-1 RD WR Data bus

Decoder
3 2 1 0
CS1
CS2

Data
RD 128 x 8
RAM 1
WR
AD7

CS1
CS2

Data
RD 128 x 8
RAM 2
WR
AD7

CS1
CS2

Data
RD 128 x 8
RAM 3
WR
AD7

CS1
CS2
RD 128 x 8 Data
RAM 4
WR
AD7

CS1
CS2
1- 7
Data

512 x 8
8
} AD9 ROM
9
Decoder
• A decoder is a combinational circuit that
converts binary information from the n coded
inputs to a maximum of 2“ unique outputs.
• If the n-bit coded information has unused bit
combinations, the decoder may have less
than 2" outputs.
• The decoders presented in this section are
called n-to-m-line decoders, where m :5 2".
Their purpose is to generate the 2" (or fewer)
binary combinations of the n input variables.
A decoder has n inputs and m outputs and is
also referred to as an n x m decoder.

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