FACULTY OF ENGINEERING SCIENCES AND TECHNOLOGY

Digital Logic Design

Name: _______________________________________________

Roll Number: _________________________________________

Compiled and Tested by:

Dr. Irfan Anis
Engr. Ghalib Nadeem

IQRA University, Main Campus, Karachi

 FACULTY OF ENGINEERING SCIENCES AND TECHNOLOGY

List of Experiments

Lab No Topics Remarks Mapping

1. Use the logic gates & familiarize with Combinational logic CLO1, 2

Use De-Morgan’s laws and verification of Boolean Laws and

2. CLO1, 2
Rules.

3. Follow the instruction to execute the 4 variable Karnaugh-Map. CLO1, 2

4. Assemble Half and Full Adder Circuits CLO1, 2

5. Use 74HC85IC to assemble Comparator CLO1, 2

6. Design 4x2 Priority Encoder CLO1, 2

7. Perform conversion of binary numbers to gray codes CLO1, 2

8. Design Odd Parity Generator and Checker for a 3-bit Data CLO1, 2

9. Design 4x1 Multiplexer CLO1, 2

10. Design 2x4 Decoder / 1x4 De-multiplexer CLO1, 2

Perform experimentally seven segment display by using 7448

11. CLO1, 2
driver IC
Construct RS Latch Using NAND gate, testing of JK flip-flop
12. CLO1, 2
and develop D- Flip-Flop using JK FF.

13. Design 4-bit Up/Down counter using IC 74193 CLO1, 2

Construct Serial in Serial out shift register using JK Flip Flop

14. CLO1, 2
and implement it using 74273 IC

15. Open Ended lab CLO1, 2

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Rubric for Manual Assessment

Exceeds Expectations Meets Expectations Developing Unsatisfactory
Criteria
(>=88%) (74%-87%) (60%-73%) (<60%)
Able to setup
Able to setup experiment experiment Can setup major Can’t set up
Experimental independently with independently with part of the the experiment
Setup complete understanding adequate experiment with even with
of each step understanding of assistance assistance
each step
Able to follow the Able to follow
procedure completely Able to follow the major part of the Unable to
Procedure with simplification or procedure procedure with follow the
develop alternate completely errors or procedure
procedure omissions
Able to achieve all the Able to achieve
Unable to
Experimental desired results with Able to achieve all most of the
achieve the
Results alternate ways to the desired results desired results
desired results
improve measurements with errors
Few sections of
All sections of the All sections of
All sections of the the manual
Laboratory manual are very well the manual
manual are contain
Manual written and technically contain multiple
technically accurate. technical
accurate. technical errors.
errors.

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Score Allocation

S.No Experimental Setup: Procedure: Experimental Results: Laboratory Manual: Score:

1 (___) /3 (___) /2 (___) /3: (___) /2 (___) /10

2 (___) /3 (___) /2 (___) /3: (___) /2 (___) /10

3 (___) /3 (___) /2 (___) /3: (___) /2 (___) /10

4 (___) /3 (___) /2 (___) /3: (___) /2 (___) /10

5 (___) /3 (___) /2 (___) /3: (___) /2 (___) /10

6 (___) /3 (___) /2 (___) /3: (___) /2 (___) /10

7 (___) /3 (___) /2 (___) /3: (___) /2 (___) /10

8 (___) /3 (___) /2 (___) /3: (___) /2 (___) /10

9 (___) /3 (___) /2 (___) /3: (___) /2 (___) /10

10 (___) /3 (___) /2 (___) /3: (___) /2 (___) /10

11 (___) /3 (___) /2 (___) /3: (___) /2 (___) /10

12 (___) /3 (___) /2 (___) /3: (___) /2 (___) /10

13 (___) /3 (___) /2 (___) /3: (___) /2 (___) /10

14 (___) /3 (___) /2 (___) /3: (___) /2 (___) /10

15 (___) /3 (___) /2 (___) /3: (___) /2 (___) /10

Total Obtained Score (___)150

Formula= (Total Obtained Score / 150) x 15 Examined by: _________________

Score: ___________ out of 15 (Signature of Instructor)

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 FACULTY OF ENGINEERING SCIENCES AND TECHNOLOGY

Instructor:

Prerequisites: None

Objectives:
Understand the working and hand on experience of digital logic and introduction of different
Hardware and Software tool use to design digital circuit.

Contents:
Logic gate IC pin out and its working, understand of Truth table and Boolean expression, reducing
circuit using De Morgan’s theorem, real world application design of half/full adder &half/full
subtractor, equation derivation using Karnaugh maps, using of magnitude comparator IC, display
digital output using BCD to 7-segment decoder, designing of different gate using universal gate,
application of Mux and De-mux, understand the working of SR latch, D Flip Flop and JK
Master/Slave Flip Flop and counter design using Synchronous & Asynchronous Sequential circuit.

Learning Outcomes:
Mapping of CLOs and PLOs

CLOs *BT Level GAs

CLO-1: Measure the different parameters/outputs of GA-03

P3
various sequential and combinational circuits using key (Design/ Development
(Guided Response)
concepts of digital logic design. of solutions)

GA-9
CLO-2: Discuss the optimist approach to fulfill the A3
requirement of a digital combinational or sequential (Individual and
(Valuing)
circuit. Teamwork)

*BT = Bloom’s Taxonomy P= Psychomotor A=Affective GA = Graduate Attributes

CLO Assessment Mechanism

Assessment tools CLO-1 CLO-2 Total

Lab Manual + Lab Performance 15% - 15%

Project 05% 05% 10%

Midterm Exam 20% 05% 25%

Final Exam 40% 10% 50%

Total 80% 20% 100%

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 FACULTY OF ENGINEERING SCIENCES AND TECHNOLOGY

Grading Policy
Marks *GPA Grade
Greater than 88 4 A
Between 81 to 87 3.5 B+
Between 74 to 80 3 B
Between 67 to 73 2.5 C+
Between 60 to 66 2 C
Below 60 0 F
*GPA = Grade Point Average

Recommended Book:
• Digital Design (4th Edition) 4th Edition
by M. Morris R. Mano (Author), Michael D. Ciletti
• Introduction to Digital Circuits by Theodore F. Bogart
• Digital Electronics Principles and Applications by Tokheim

Administrative Instructions:
▪ Title and Group members name for Lab/Course project should be submitted by 4th week of
lab.
▪ According to institute policy, 80% attendance is mandatory to appear in the final
examination but 100% will be expected. Approved leaves will not be considered towards
attendance.
▪ Every student should bring calculator, book and manual in each lab.
▪ Every student is expected to be in lab before schedule starting time.
▪ In any case there will be no rescheduling and makeup of labs.

Total Lab Assessment

Assessment Criteria Criteria Marks Obtained Marks
Total
CLOs CLO1 CLO2 CLO3 CLO1 CLO2 CLO3

Lab Manual+ Lab Performance 15 - - - -

Project (CEA) 05 05 - -

Midterm Exam 20 5 - -

Final Exam 40 10 - -
-
Total 80 20 -

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General Laboratory Procedure

While there is no specific document to be submitted at the beginning of the Lab –unless your instructor
advises you otherwise-, you are expected to read the experiment fully before you come to the laboratory?
Interestingly, you can even try parts of the experiment at home. Here is a list of programs that will equip
you with a virtual lab at your home.
Troubleshooting
Things will not always go as expected; this is the nature of the learning process. While conducting the
Experiment think before you do anything. If you do so you will avoid wasting time going down dead-end
streets. Be logical and systematic. First, look for obvious errors that are easy to fix. Is your measuring
device correctly set and connected? Are you looking at the proper scale? Is the power supply set for the
correct voltage? Is the signal generator correctly set and connected? How are the variables in the code set?
Is there a syntax error? And so on. Next, check for obvious misconnections or broken connections, at least
in simple circuits.
As you work through your circuit, use your Lab Manual record tests and changes that you make as you go
along; don't rely on your memory for what you have tried. Identify some test points in the system at which
you know what the signal should be and work your way backwards from the output through the test points
until you find a good signal.
Neatness
When you have finished for the day, return all modules to their proper storage bins, return all test leads and
probes to their storage racks, return all equipment to its correct location, and clean up the lab station. If
appropriate switch off the unneeded equipment. Save your files in the Computer and on any USB device
for your records because you might not get the same PC System again for the next experiment. Also email
your file contents to your email address as a backup.
Laboratory Safety

Always pay attention to what you are doing and you’re surrounding during the experiments, notify the
Instructor for any unlikely event or mishap, and leave the Laboratory with the permission of Instructor
immediately.
All students must read and understand the information in this document with regard to laboratory safety
and emergency procedures prior to the first laboratory session.

Your personal laboratory safety depends mostly on YOU. Efforts have been made to address situations
that may pose a hazard in the lab but the information and instructions provided cannot be considered all-
inclusive.
Students must adhere to written and verbal safety instructions throughout the academic term. Since
additional instructions may be given at the beginning of laboratory sessions, it is important that all students
arrive at each session on time. With good judgment, the chance of an accident in this course is very small.

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Nevertheless, research and teaching workplaces (labs, shops, etc.) are full of potential hazards that can
cause serious injury and or damage to the equipment. Working alone and unsupervised in laboratories is
forbidden if you are working with hazardous substances or equipment. With prior approval, at least two
people should be present so that one can shut down equipment and call for help in the event of an emergency.
Safety training and/or information should be provided by a faculty member, teaching assistant, lab safety
contact, or staff member at the beginning of a new assignment or when a new hazard is introduced into the
workplace.
Emergency Response
1. It is your responsibility to read safety and fire alarm posters and follow the instructions during an
emergency
2. Know the location of the fire extinguisher, eye wash, and safety shower in your lab and know how to
use them.
3. Notify your instructor immediately after any injury, fire or explosion, or spill.
4. Know the building evacuation procedures.

Common Sense
Good common sense is needed for safety in a laboratory. It is expected that each student will work in a
responsible manner and exercise good judgment and common sense. If at any time you are not sure how to
handle a particular situation, ask your Teaching Assistant or Instructor for advice DO NOT TOUCH
ANYTHING WITH WHICH YOU ARE NOT COMPLETELY FAMILIAR!!! It is always better to
ask questions than to risk harm to yourself or damage to the equipment.

Personal and General laboratory safety

1. Never eat, drink, or smoke while working in the laboratory.
2. Read labels carefully.
3. Do not use any equipment unless you are trained and approved as a user by your supervisor.
4. Wear safety glasses or face shields when working with hazardous materials and/or equipment.
5. Wear gloves when using any hazardous or toxic agent.
6. Clothing: When handling dangerous substances, wear gloves, laboratory coats, and safety shield or
glasses. Shorts and sandals should not be worn in the lab at any time. Shoes are required when working
in the machine shops.
7. If you have long hair or loose clothes, make sure it is tied back or confined.
8. Keep the work area clear of all materials except those needed for your work. Coats should be hung in
the hall or placed in a locker. Extra books, purses, etc. should be kept away from equipment that requires
air flow or ventilation to prevent overheating.
9. Disposal - Students are responsible for the proper disposal of used material if any in appropriate
containers.
10. Equipment Failure - If a piece of equipment fails while being used, report it immediately to your lab
assistant or tutor. Never try to fix the problem yourself because you could harm yourself and others.
11. If leaving a lab unattended, turn off all ignition sources and lock the doors.
12. Never pipette anything by mouth.
13. Clean up your work area before leaving.
14. Wash hands before leaving the lab and before eating.
15. Unauthorized person(s) shall not be allowed in a laboratory for any reason.

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Electrical safety
1. Obtain permission before operating any high voltage equipment.
2. Maintain an unobstructed access to all electrical panels.
3. Wiring or other electrical modifications must be referred to the Electronics Shop or the Building
Coordinator.
4. Avoid using extension cords whenever possible. If you must use one, obtain a heavy- duty one that is
electrically grounded, with its own fuse, and install it safely. Extension cords should not go under doors,
across aisles, be hung from the ceiling, or plugged into other extension cords.
5. Never, ever modify, attach or otherwise change any high voltage equipment.
6. Always make sure all capacitors are discharged (using a grounded cable with an insulating handle)
before touching high voltage leads or the "inside" of any equipment even after it has been turned off.
Capacitors can hold charge for many hours after the equipment has been turned off.
7. When you are adjusting any high voltage equipment or a laser which is powered with a high voltage
supply, USE ONLY ONE HAND. Your other hand is best placed in a pocket or behind your back. This
procedure eliminates the possibility of an accident where high voltage current flows up one arm, through
your chest, and down the other arm.
8. Discard damaged cords, cords that become hot, or cords with exposed wiring.
9. Before equipment is energized ensure, (1) circuit connections and layout have been checked by a
Teaching Assistant (TA) and (2) all colleagues in your group give their assent.
10. Know the correct handling, storage and disposal procedures for batteries, cells, capacitors, inductors and
other high energy-storage devices.
11. Experiments left unattended should be isolated from the power supplies. If for a special reason, it must
be left on, a barrier and a warning notice are required.
12. Equipment found to be faulty in any way should be reported to the Lab Engineer immediately and taken
out of service until inspected and declared safe.
13. Voltages above 50 Vrms AC and 120 V DC are always dangerous. Extra precautions should be
considered as voltage levels are increased.
14. Never make any changes to circuits or mechanical layout without first isolating the circuit by switching
off and removing connections to power supplies.
15. Know what you must do in an emergency.
16. Emergency Power Off: Every lab is equipped with and Emergency Power Off System.
17. Only authorized personnel are permitted to reset power once the Emergency Power Off system has been
engaged.

Electrical Emergency Response

The following instructions provide guidelines for handling two types of electrical emergencies:
1. When someone suffers serious electrical shock, he or she may be knocked unconscious. If the victim is
still in contact with the electrical current, immediately turn off the electrical power source. If you cannot
disconnect the power source, depress the Emergency Power Off switch.
2. Do not touch a victim that is still in contact with a live power source; you could be electrocuted.
3. Have someone call for emergency medical assistance immediately. Administer first-aid, as appropriate.

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4. If an electrical fire occurs, try to disconnect the electrical power source, if possible. If the fire is small
and you are not in immediate danger; and you have been properly trained in fighting fires, use the correct
type of fire extinguisher to extinguish the fire. When in doubt, push in the Emergency Power Off button.
5. NEVER use water to extinguish an electrical fire.

Mechanical safety
1. When using compressed air, use only approved nozzles and never direct the air towards any person.
2. Guards on machinery must be in place during operation.
3. Exercise care when working with or near hydraulically- or pneumatically-driven equipment. Sudden or
unexpected motion can inflict serious injury.

Additional Safety Guidelines

1. Never do unauthorized experiments.
2. Never work alone in laboratory.
3. Keep your lab space clean and organized.
4. Do not leave an on-going experiment unattended.
5. Always inform your instructor if you break a thermometer. Do not clean mercury yourself!!
6. Never taste anything. Never pipette by mouth; use a bulb.
7. Never use open flames in laboratory unless instructed by TA.
8. Check your glassware for cracks and chips each time you use it. Cracks could cause the glassware to fail
during use and cause serious injury to you or lab mates.
9. Maintain unobstructed access to all exits, fire extinguishers, electrical panels, emergency showers, and
eye washes.
10. Do not use corridors for storage or work areas.
11. Do not store heavy items above table height. Any overhead storage of supplies on top of cabinets should
be limited to lightweight items only. Also, remember that a 36" diameter area around all fire sprinkler
heads must be kept clear at all times.
12. Areas containing lasers, biohazards, radioisotopes, and carcinogens should be posted accordingly.
However, do not post areas unnecessarily and be sure that the labels are removed when the hazards are
no longer present.
13. Be careful when lifting heavy objects. Only shop staff may operate forklifts or cranes.
14. Clean your lab bench and equipment, and lock the door before you leave the laboratory.

Clothing
1. Dress properly during a laboratory activity.
2. Long hair, dangling jewelry, and loose or baggy clothing are a hazard in the laboratory.
3. Long hair must be tied back, and dangling jewelry and baggy clothing must be secured.
4. Shoes must completely cover the foot.
5. No sandals allowed on lab days.
6. A lab coat or smock should be worn during laboratory experiments.

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Accidents and Injuries

1. Do not panic.
2. Report any accident (spill, breakage, etc.) or injury (cut, burn, etc.) to the teacher immediately, no matter
how trivial it seems.
3. If you or your lab partner is hurt, immediately (and loudly) yell out the teacher's name to get the teacher's
attention.

General Warning Signs

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 FACULTY OF ENGINEERING SCIENCES AND TECHNOLOGY

Lab-01
Objectives:
Use the logic gates & familiarize with Combinational logic.

Components Required

• Bread board
• 5 V - power supply
• Multi-meter
• Logic probe
• LEDs with resistors
• Connecting wires
• Switches

Following ICs and their datasheets

• 7408 quad 2 input AND

• 7432 quad 2 input OR gate
• 7404 hex inverter
• 7400 quad 2 input NAND
• 7402 quad 2 input NOR gate
• 7486 quad 2 input EXOR gate

Theory

Logic Gates:

Logic gates are the fundamental building blocks of digital systems. These devices are able to
make decisions, in the sense that they produce one output level when some
combinations of input levels are present and a different output when other combinations
are applied; hence given the name Logic Gates. The two levels produced by digital circuitry
are referred as HIGH and LOW, TRUE and FALSE, ON and OFF, or simply 1 and 0. There
are only three basic gates: AND, OR and NOT. The other gates are merely combinations of
these basic gates. Logic gates can be interconnected to perform a variety of
logical operations. This interconnection of gates to achieve prescribed outcomes is called
logic design.

AND Gate

An AND gate's output is 1 if and only if all its inputs are 1. e.g if A and B. are two inputs of
an AND gate then output, F of the gate is given as: F = A . B

OR Gate

An OR gate's output is 1 if at least one of its input is 1 e.g. if A and B are two inputs to an
OR gate then output, F of the gate is given as: F = A+B

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NOT Gate (Inverter)

Its output is 1 when its input is 0 and its output

is 0 when the
input is 1; i.e. it complements a digital variable. If A is the intput to a gate then output, F of the
gate is given as: F= A`

NAND Gate

Its output is 1 if at least one of its inputs is 0. This gate performs the same logic as an AND
gate followed by an inverter. If A and B are two inputs to a NAND gate then output, F of
the gate is given as: F = A . B

NOR Gate

The output of a NOR gate is 1 if and only if all its inputs are 0. This
gate performs the same logic function as an OR gate followed by an inverter. If A
and B are two inputs to a NAND gate then output, F of the gate is given as: F= A+B All the
above gates have one output and two or more inputs except the NOT gate, which has only
one input.

EXOR Gate

EXOR operation is that if even numbers of binary inputs are logic 1 output will be logic
1; otherwise output will be logic 0. for 2 inputs, it becomes a bit comparison
operation. The Output is high only if either A or B is high, output goes low if both inputs
are high or low. If A and B are two inputs to a NAND gate then output, F of the gate is
given as: F=
A B.

Procedure for Testing Logic Gates in Given ICs

1. Set the power supply to 5V.with the help of a multimeter check the voltage at
the output knobs of the power supply.
2. Connect wires; long enough to reach the breadboard, with the two knobs of the power
supply. Again using multimeter, check voltages at the non-connected end of the wires.
3. Insert the 7408 quad 2 input AND gate IC on to the bread board and make supply and
ground connections by joining wire between 5V and pin # 14 as well as 0V and
Pin #7.
4. Consult IC's internal connection diagram for input and the output pins of the first AND
gate. Connect input pins to logic 0 (0V) and observe the output using LED or logic probe.
You can also connect switches at the input lines to facilitate togging between 1 and 0.
5. Try different combinations of logic levels at the two inputs. Again observe the output.
6. Repeat the last two steps for all other gates of the same IC. Record the observations.
7. Repeat this procedure for all other ICs.

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Observations

AND Gate
Input A Input B Expected Output Observed Output
0 0
A.B 0 1
1 0
1 1

OR Gate
Input A Input B Expected Output Observed Output
0 0
A+B 0 1
1 0
1 1

NAND Gate
Input A Input B Expected Output Observed Output
0 0
A.B 0 1
1 0
1 1

NOR Gate
Input A Input B Expected Output Observed Output
0 0
A+B
0 1
1 0
1 1

XOR Gate
Input A Input B Expected Output Observed Output
0 0
A B
0 1
1 0
1 1

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X-NOR Gate
Input A Input B Expected Output Observed Output
0 0
A B 0 1
1 0
1 1

NOT Gate
Input A Expected Output Observed Output
A 0
1

Task 1.1: Procedure for Implementation of the Given Circuit

1. Set the power supply to 5V.

2. Insert ICs on the bread board and make their supply and ground connections.
3. As given in the logic diagram, make connections using wires and gates in the ICs.
4. Apply different combinations at the three inputs and observe the output.

Circuit Diagram

Figure 1.2
Observations
Logic expression for the given logic diagram:

A B C Expected output Observed output

0 0 0
0 0 1
0 1 0
0 1 1
1 0 0
1 0 1
1 1 0
1 1 1

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Internal IC Diagrams

Figure 1: 7400 (NAND )

Fi gure 2: 7404 (N OT )

Fi gu re 3
NOR

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Figure 4: AND

Fi gure 5: OR

Fi gure 6: XO R

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IQRA University, Main Campus, Karachi

 FACULTY OF ENGINEERING SCIENCES AND TECHNOLOGY

Conclusion:
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 FACULTY OF ENGINEERING SCIENCES AND TECHNOLOGY

Lab-02
Objectives:
Use De-Morgan’s laws and verification of Boolean Laws and Rules.

Components & Apparatus Required

Bread board/Digital Logic Trainer
5 V -DC Power Supply
Logic probe
ICs 7410, 7427, 7432, 7408 & 7404

Theory

In Boolean algebra, the two De Morgan’s laws are very important as these play key role in
manipulating logic functions into SOP/POS forms. For two inputs, these laws are:

In this experiment, you will using 3-input NAND and NOR gates to verify De Morgan’s laws for three
inputs

Procedure & Observations

Using 3-input NAND gate & NOT+OR gates to verify:

1. Take IC 7410 triple 3-inputs NAND gate and insert it in bread board/Digital Logic trainer.
2. Connect the circuit as shown below by connecting the DC supply (5V) and ground to pin#14 and 7 and
logic inputs A, B and C to pin# 1, 2 and 13. Then take output from pin# 12.

3. In Boolean form this output is .

4. Change inputs according to the table below and record your observations in observation table 2.1
5. Now implement Boolean function using NOT and OR gates.
6. Connect the circuit show below by using NOT and OR gates ICs (refer to ICs internal diagram
provided at the end of experiment manual) on bread board/ Digital Logic Trainer.

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Observation Table 2.1

Input A Input B Input C Output

0 0 0
0 0 1
0 1 0
0 1 1
1 0 0
1 0 1
1 1 0
1 1 1

7. Apply the logic inputs A, B, and C to the circuit and record your observations in the following tables.
Observation Table 2.2

Input A Input B Input C Output

0 0 0
0 0 1
0 1 0
0 1 1
1 0 0
1 0 1
1 1 0
1 1 1
You will agree that the outputs of two tables are same. Hence De Morgan’s law is verified.

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Using 3-inputs NOR Gate and NOT+AND gates to verify that:

1. Take IC 7427 triple 3-inputs NOR gate and insert it in bread board/Digital logic trainer.
2. Connect the circuit as shown below by connecting the DC supply (5V) and ground to pin#14 and 7 and
logic inputs A, B and C to pin# 1, 2 and 13. Then take output from pin# 12.

3. In Boolean form this output is

4. Change inputs according to the table below and record your observations:

Observation Table 2.3

Input A Input B Input C Output

0 0 0
0 0 1
0 1 0
0 1 1
1 0 0
1 0 1
1 1 0
1 1 1

5. Now implement Boolean function using NOT and AND gates.

6. Connect the circuit show below by using NOT and AND gates ICs (refer to ICs internal diagram
provided at the end of experiment manual) on bread board/ Digital Logic Trainer.

7. Apply the logic inputs A, B, and C to the circuit and record your observations in the following tables:

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Observation Table 2.4

Input A Input B Input C Output

0 0 0
0 0 1
0 1 0
0 1 1
1 0 0
1 0 1
1 1 0
1 1 1

You will agree that the outputs of two tables are same. Hence De Morgan’s law is verified.

3-Input NAND Gate IC (7410) 3-Input NOR Gate IC (7427)

Task 2.1: Verify and implement the following:

1. A + AB = A
2. A (B+C) = AB + AC

Conclusion:
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______________________________________________________________________________
______________________________________________________________________________
______________________________________________________________________________
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Lab-03

Objectives:
Follow the instruction to execute the 4 variable Karnaugh-Map.

Given Logic Expression

F (A, B, C, D) = (0, 1, 2, 4, 5, 6, 8, 9, 12, 13, 14)

Components and Apparatus Required

• Bread board
• 5 V – Power supply
• Multimeter
• logic probe
• LEDs with resistors
• Connecting wires

Following Digital ICs and their Datasheets

7408 Quad 2-input AND Gate
7432 Quad 2-input OR Gate
7404 Hex Inverter

Procedure
1. Construct the truth table of given logic expression.
2. Use Karnaugh- map to reduce the given function.
3. Draw the circuit diagram for the obtained reduced function.
4. Implement the reduced circuit using digital ICs on a bread board.
5. Observe the output and record it in the observation table and check it with the truth table.
Reduction Of Logic Of Expression Using Karnaugh Map

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Logic Diagram (Reduced Form)

Result
The reduced form (SOP Expression) of the given logic function is:

Constructed Truth Table

A B C D Expected Observed
0 0 0 0
0 0 0 1
0 0 1 0
0 0 1 1
0 1 0 0
0 1 0 1
0 1 1 0
0 1 1 1
1 0 0 0
1 0 0 1
1 0 1 0
1 0 1 1
1 1 0 0
1 1 0 1
1 1 1 0
1 1 1 1

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Task 3.1: Use the Karnaugh Map (POS Expression) to reduce the logical expression

F (A, B, C, D) = (0, 1, 2, 4, 5, 6, 8, 9, 12, 13, 14)

Task Result:
The reduced form (SOP Expression) of the given logic function is:

Conclusion:
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Lab-04
Objectives:
Assemble Half and Full Adder Circuits.

Components and Apparatus Required

1. Following ICs and their Datasheets:

1. 7408 Quad 2-input AND Gate.
2. 7432 Quad 2-input OR Gate.
3. 7486 Quad 2-input XOR Gate
2. Bread board/Digital Trainer.
3. 5 V - Power Supply.
4. Multimeter.
5. Logic Probe.
6. LEDs with Resistors.
7. Connecting wires.

Half Adder
A combinational circuit that performs the addition of two bits without accounting for the
previous carry is called half adder. It needs two binary inputs and two binary outputs. The
input variables designate the augends and addend bits. The output variables produce the sum and
carry. The simplified sum of product is an expression for a half adder. S = x y
C = x.y

Sum
Output

Carry
Output

Full Adder
Full adder is the combinational circuit that performs the addition of three input bits. It consists of
three inputs and two outputs. Two of the input variables, represent the two significant bits to be
added. The third input, represents the carry from the previous lower significant position. The
output variables produce the sum and carry. The simplified sums of product expressions for a half
adder are:

S = x XOR y XOR z
C = (x XOR y) z + x y

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Implementation & Observation

Implement the half adder and full adder circuits on a bread board or digital trainer
(prepare the pin diagram; refer to laboratory session 01 for procedure) and record the
observations in the following tables:

Half Adder

Inputs Outputs
X Y Carry Sum
0 0
0 1
1 0
1 1

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Full Adder

Inputs Outputs
X Y Z Carry Sum
0 0 0
0 0 1
0 1 0
0 1 1
1 0 0
1 0 1
1 1 0
1 1 1

Task 4.1: Design a 2 bit parallel full adder.

Conclusion:
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Lab-05
Objectives:

Use 74HC85IC to assemble Comparator

Components & Apparatus Required

Bread board / Digital Trainer
5v power supply
Multi-meter
Logic probe
LEDs with Resistors
Connecting Wires

Following ICs and their Datasheets:

74HC85 4 bit Comparator
7408 Quad 2-input AND Gate
7404 Hex Inverter
7486 Quad 2-input XOR Gate.

Theory
Comparator
The basic function of a comparator is to compare the magnitudes of two binary
quantities to determine the relationship of those quantities. In its simplest form a
comparator circuit determines whether two numbers are equal.

One bit Comparator

A
Y2 (A=B)
B

Y1 (A>B)

Y0 (A<B)

Figure 5.1

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Observation

Data Expected Output Observed Output

A B Y0(A<B) Y1(A>B) Y2(A=B) Y0(A<B) Y1(A>B) Y2(A=B)
0 0 0 0 1
0 1 1 0 0
1 0 0 1 0
1 1 0 0 1

Four-bit Comparator

To determine an inequality of binary numbers A and B, you first examine the highest-order bit in each
number. The following conditions are possible:

1. If A3 = 1 and B3 = 0, number A is greater than number B.

2. If A3 = 0 and B3 = 1 number A is less than number B.
3. If A3 = B3, then you must examine the next lower bit position for an inequality.

These three operations are valid for each bit position in the numbers. The general procedure
used in a comparator is to check for an inequality in a bit position, starting with the highest-
order bits (MSBs). When such an inequality is found, the relationship of the two numbers is
established, and any other inequalities in lower order bit positions must be ignored because it is
possible for an opposite indication to occur; the highest-order indication must take precedence.

Circuit Diagram

Figure 5.2: Pins of 74HC85 IC

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Testing Procedure

• Make connection as show in the circuit diagram.

• Apply different combinations of 1s and 0s at data inputs.
• Observed the output and record your observation in the following table.

Observation

B3 B2 B1 B0 A3 A2 A1 A0 A<B A=B A>B

0 0 0 0 0 0 0 1
0 0 0 1 0 0 0 0
1 0 1 0 1 0 1 0
1 0 0 1 1 0 1 0
1 1 0 0 0 1 0 1
0 1 0 1 0 0 1 1
1 0 0 0 0 1 1 1
1 1 1 0 1 1 0 1
1 1 1 1 1 1 1 1
0 0 1 0 0 1 0 0
0 0 0 1 1 0 0 0

Task 5.1: Design an 8-bit comparator.

Conclusion:
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Lab-06

Objectives:
Design 4x2 Priority Encoder

Components & Apparatus Required

• Bread board/Digital Trainer

• 5v power supply
• Multimeter
• Logic probe
• LEDs with Resistors
• Connecting wires,

Following ICs and their Datasheets

• 74148 8 x 3 octal priority Encoder

• 7408 Quad 2-jnput or 7421 Dual 4-input AND Gates
• 7432 Quad 2-input OR Gates
• 7404 Hex Inverter.

Theory

Encoder

An encoder is a digital function that produces a reverse operation from that of a decoder. An Encoder
has 2n (or less) inputs lines and n output lines. The output lines generate the binary code for the 2n
inputs variables.

Priority Encoder

A simple encoder may produce an erroneous output if more than one of its inputs is high. A Priority
Encoder is one that responds to just one input among those that may be simultaneously
high, in accordance with some priority system. The most common priority system is based on
the relative magnitudes of the inputs: whichever decimal input is largest is the one that is encoded.

Design of a 4 X 2 Priority Encoder

The following equations represent the outputs of a 4 x 2 priority encoder:

A = D2 + D3
_
B = D1D2 +D3

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As can be seen from the equations that input D0, which has a binary code 00, is not used in any equation.
A binary code 00 at the output indicates two conditions: Either D0 is selected or no input is selected.
In order to differentiate these two conditions, we will provide an additional output, Z to indicate
if at least one of the inputs is a 1. The equation for Z will be:

Z = D0 + D2 + D3 +D4

If Z is 1, then the binary code 00 at the output indicates that D0 is selected and if Z is 0, then it indicates
that no input line is selected.

Implementation & Observations

Implement the 4 x 2 priority encoder circuit figure 5.1 on bread board (prepare the pin diagram; refer
to laboratory session.01 for implementation procedure) and record the observation in the following
table:

D3 D2 D1 D0 Expected Observed
A B Z A B Z
0 0 0 0 0 0 0
0 0 0 1 0 0 1
0 0 1 X 0 1 1
0 1 X X 1 0 1
1 X X X 1 1 1

Task 6.1: Design a 4x2 Priority encoder having priority system based on the relative magnitudes of
the inputs: whichever decimal input is smallest is the one that is encoded.

Task 6.2: Testing of 74148 8 x 3 octal priority Encoder

The 74148 is a priority encoder with active-Low input for decimal digits. There are nine inputs
lines (including an enable input) and five output lines, of which three represents the binary code
for the octal digit. Function of various pins of this IC is described below:

1. 0 through 7: Active low data inputs representing the octal digits 2.

A2, A1, A0: Active low output lines representing the binary code
3. El: Active low enable Input .
4. EO: Active low output indicating none of the inputs is high
5. GS: Active low output indicating any of the inputs is high
6. VCC and GND: Supply connections; lines

Therefore if GS, A2, Al, and A0 are all low, then it shows that line 0 is selected and if EO, A2,
Al, and AO are all low then it shows that none of the inputs selected. EO and. GS cannot be in
the same state provided that El is enabled.

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Figure 6.2: Pins of 74148

Testing Procedure

1. Make connections as shown in the circuit diagram.

2. Apply different combinations of 1s and 0s at data inputs.
3. Observe the output and record your observations in the following table.

Observation

0 1 2 3 4 5 6 7 A2 A1 A0 GS E0
1 1 1 1 1 1 1 1
1 1 1 1 1 1 1 0
1 1 1 1 1 1 0 1
1 1 1 1 1 0 1 1
1 1 1 1 0 1 1 1
1 1 1 0 1 1 1 1
1 1 0 1 1 1 1 1
1 0 1 1 1 1 1 1
0 1 1 1 1 1 1 1

Conclusion:
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Lab-07
Objectives:
Perform conversion of binary numbers to gray codes.

Components & Apparatus Required

• Bread board/Digital Trainer

• 5v power supply
• Multimeter
• Logic probe
• LEDs with Resistors
• IC 7486
• Connecting wires

Procedure

1. The circuit connections are made as shown in fig.

2. Pin (14) is connected to +Vcc and Pin (7) to ground.
3. In the case of binary to gray conversion, the inputs B0, B1, B2 and B3 are given at respective pins and
outputs G0, G1, G2, G3 are taken for all the 16 combinations of the input.
4. In the case of gray to binary conversion, the inputs G0, G1, G2 and G3 are given at respective pins and
outputs B0, B1, B2, and B3 are taken for all the 16 combinations of inputs.
The values of the outputs are tabulated.

Circuit Diagram

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Observation table for Binary to Gray Code

Input Expected Output Observed Output

B3 B2 B1 B0 G3 G2 G1 G0 G3 G2 G1 G0
0 0 0 0 0 0 0 0
0 0 0 1 0 0 0 1
0 0 1 0 0 0 1 1
0 0 1 1 0 0 1 0
0 1 0 0 0 1 1 0
0 1 0 1 0 1 1 1
0 1 1 0 0 1 0 1
0 1 1 1 0 1 0 0
1 0 0 0 1 1 0 0
1 0 0 1 1 1 0 1
1 0 1 0 1 1 1 1
1 0 1 1 1 1 1 0
1 1 0 0 1 0 1 0
1 1 0 1 1 0 1 1
1 1 1 0 1 0 0 1
1 1 1 1 1 0 0 0

Observation table for Gray Code to Binary

Input Expected Output Observed Output
G3 G2 G1 G0 B3 B2 B1 B0 B3 B2 B1 B0
0 0 0 0 0 0 0 0
0 0 0 1 0 0 0 1
0 0 1 1 0 0 1 0
0 0 1 0 0 0 1 1
0 1 1 0 0 1 0 0
0 1 1 1 0 1 0 1
0 1 0 1 0 1 1 0
0 1 0 0 0 1 1 1
1 1 0 0 1 0 0 0
1 1 0 1 1 0 0 1
1 1 1 1 1 0 1 0
1 1 1 0 1 0 1 1
1 0 1 0 1 1 0 0
1 0 1 1 1 1 0 1
1 0 0 1 1 1 1 0
1 0 0 0 1 1 1 1

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Task 7.1: Implement a Binary to Gray and Gray to Binary on simulator.

Conclusion:
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Lab - 08
Objectives:
Design Odd Parity Generator and Checker for a 3-bit Data.

Components & Apparatus Required

• Bread board/Digital Trainer

• 5 V - Power Supply
• Multimeter
• Logic Probe
• LEDs with Resistors
• Connecting wires

Following ICs and their Datasheets

• 7486 Quad 2-mput Exclusive-OR Gates

• 7404 Hex Inverter

Theory

Parity Generator

When binary data is transmitted and processed; as are all electrical signals-susceptible to noise that can
either alter or distort its contents. So it may be effectively changed from 1s to 0s and vice versa. To
overcome this problem one or more bits are often added to data as an aid in detecting errors caused by
noise. The most common of these is a parity bit that signifies whether the total number of 1s in a code group
is odd or even .In an odd parity system the parity bit is made 0 or 1 as necessary to make the total number
1s even. Table 6.1 shows how parity bits would be added to BCD code group in both systems. bit itse

Decimal BCD Value Parity Bit

ABCD Odd parity Even parity
0 0000 1 0
1 0001 0 1
2 0010 0 1
3 0011 1 0
4 0100 0 1
5 0101 1 0
6 0110 1 0
7 0111 0 1
8 1000 0 1
9 1001 1 0

Table 1: Odd and Even Parity in BCD

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When digital data is received, a parity checking circuit generates an error signal if the total
number of 1s odd in an even parity system or if it is even in an odd parity system, Parity check always
detects a single error (one bit change from 0 to 1 or 1 to 0) but may not detect two or more errors.
Odd parity is used more often than even parity because even parity does not detect a situation
where all Os are created due to short circuit or other fault condition.

Design Of A 3-BIT Odd Parity Generator & Checker

Let x, y, and z be the three bits that constitute the message and are the input to the Odd Parity
Generator Circuit. Since it is an odd parity system, the bit P is generated so as to make the total
number of 1s odd (including P). The function P can be expressed as follows:

Therefore, we can implement

P with a 3-variable XNOR gate. Of course, we don't have a 3 input XNOR gate in our lab kits,
but you can easily build one from 2 XOR gates from a 7486 and 1 inverter (HINT: XOR is
associative, like AND or OR, so

The circuit of the above logic equation is given by:

The 3-bit message and the parity bit are transmitted to their destination, where they are applied
to a Parity Checker Circuit. An error occurs during transmission if the parity of the four bits
received is even, since the binary information transmitted was originally odd. The output C
of the parity checker should be a 1 when an error occurs, i.e., when the number of is in the four
inputs is even. Therefore, the function C can be expressed as:

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Implementation & Observation

Implement the 3-bit Generator and checker circuits on a bread board/Digital Trainer (prepare
the pin diagram and refer to laboratory session 01 for implementation procedure) and record
the observations in the following table:

X Y Z P X Y Z P C
0 0 0 0 0 0 0
0 0 1 0 0 0 1
0 1 0 0 0 1 0
0 1 1 0 0 1 1
1 0 0 0 1 0 0
1 0 1 0 1 0 1
1 1 0 0 1 1 0
1 1 1 0 1 1 1

Odd parity generation Odd parity check

Task 8.1: Design a 8 bit even parity generator.

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Conclusion:
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Lab-09
Objectives:
Design 4x1 Multiplexer.

Components & Apparatus Required

1. Following ICs and their Datasheets:

I. 7411 Triple 3-input AND Gates.
II. 7432 Quad 2-input OR Gates.
III. 7404 Hex Inverter.
IV. 74151 8 x 1 MUX
2. Bread board/Digital Trainer.
3. 5V power supply.
4. Multimeter.
5. Logic Probe.
6. LEDs with Resistors
7. Connecting wires.

Theory

Multiplexers

A digital data Multiplexer (MUX) is a combinational circuit having several data inputs and a
single output. A set of data-select inputs is used to control when of the data an input is routed to
the single output. A multiplexer is also called a data selector because of this ability to select which
n
data input is connected to the output. Normally there are 2 input lines and n selection lines
whose bit combination determine which input is selected.

Design Of 4 x 1 Multiplexer

A 4 x 1 multiplexer is capable of selecting one of four data inputs (see figure 1). The 2- bit
binary number at the data select inputs, Si and So, specifies which of the four data inputs is to
2
be routed to the output. Since there are two data select inputs, therefore they can select 2 = 4
different data inputs lines.

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Figure 9.1

Figure 9.2
Procedure

Implement the 4x1 Multiplexer circuit on a bread board/Digital Trainer as shown in figure # 2;
prepare the pin diagram (by referring to laboratory session 01 for implementation procedure for
NOT, AND and OR gates) and record the observations in the following, table. For each data
select combination, specify the switch number as well as the binary value present on that
selected switch.

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Observation
D3 D2 D1 D0 S1 So OUTPUT
0 1 0 1 0 0
0 1 0 1 0 1
0 1 0 1 1 0
0 1 0 1 1 1
1 0 1 0 0 0
1 0 1 0 0 1
1 0 1 0 1 0
1 0 1 0 1 1

Task 9.1: TESTING OF 74151A -8 x 1 MUX

The 74151A IC has eight data inputs and three data-selection lines. Function of various pins of
this IC is described below:
1. D0 through D7: Data input lines
2. A, B, C, : Data select lines with C being the MSB
3. Y: Output line.
4. W: Inverted output line.
5. G': Active low enable line
6. VCC and GND: Supply connections lines

Testing Procedure

1. Make connections as shown in the figure 3 on bread board/Digital Trainer.

2. Select the data input D0 (applied both 0 & 1) with the help of data selectors A, B and C.
3. Apply different data (1 or 0) at data inputs that are labeled as D0 to D7.
4. Observe the output, which shows the data from D0.
5. Select all the eight data inputs one by one and record your observations in the following table.

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Figure 9.3

Conclusion:
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Lab-10
Objectives:
Design a 2x4 Decoder / 1x4 De-multiplexer.

Components & Apparatus Required

• Bread board/Digital Trainer

• 5 V - Power Supply
• Multimeter
• Logic Probe
• LEDs with Resistors
• Connecting Wires

Following ICs and their Datasheets

• 7408 Quad 2-input or 7411 Triple 3-input AND Gates

• 7404 Hex Inverter
• 74138 3x8 Decoder

Theory:

Decoder
A Decoder is a combinational circuit that converts binary information from n input lines to a maximum
of 2n unique output lines. In practical applications, decoders are often used for selecting one of
several devices.

De-multiplexer
A decoder with an enable input can function as a Demultiplexer. A Demultiplexer (DMUX) id a circuit
that receives information on a single line and transmits this information on one of 2n possible output
lines. The selection of a specific output line is controlled by the bit values of n selection lines.

Design Of 2 x 4 Decoder / 1 x 4 De-multiplexer

A 2 x 4 decoder is capable of selecting one of four output lines (see figure 1 (a)). The 2- bit binary
numbers at the data inputs, Si and So, specifies which of the four data inputs is to be selected. If we
add an enable pin and use it as an input line, then this decoder can be converted to a 1 x 4
Demultiplexer, where Si arid So will select a line to which data input is to be routed (see figure 1
(b)).

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Figure 10.1

Figure 10.2: Circuit Diagram for 2 x 4 Decoder/ 1 x 4 Demultipler

Implementation & Observations

Implement the 2x4 Decoder /1 x 4 De multiplexer circuit (figure 2) on a bread board (prepare the
pin diagram by referring to laboratory session 1 for implementation procedure) and record the
observations in the following table.

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Enable / Data Input S1 So Do D1 D2 D3

0 0 0
0 0 1
0 1 0
0 1 1
1 0 0
1 0 1
1 1 0
1 1 1

Testing Of 74138 3 x 8 Decoder

The 74138 IC has three inputs and eight output lines. It has three enable inputs and for IC to
function all three inputs need to be enabled. Function of various pins of this IC is described
below

1. YO through Y7: Active low data outputs

2. A, B, C: Input / select lines with C being the MSB
3. Gl: Active high enable Input
4. G2A' and G2B': Active low enable Inputs
5. VCC and GND: Supply connections line

Circuit Diagram

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Testing Procedure

1. Make connections as shown in the circuit diagram.

2. Apply different combinations of Is and 0s at data inputs
3. Observe the output and record your observations in the following table.

Observation

C B A Y0 Y1 Y2 Y3 Y4 Y5 Y6 Y7
0 0 0
0 0 1
0 1 0
0 1 1
1 0 0
1 0 1
1 1 0
1 1 1

Task 10.1: Design 1x4 De-multiplexer using logic gates

Conclusion:
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LAB - 11
Objectives:
Perform experimentally seven segment display by using 7448 driver IC.

Components & Apparatus Required

• Bread board/Digital Logic Trainer

• 5 V - Power Supply
• Multi-meter
• Logic Probe
• LEDs with Resistors
• Connecting Wires
• Seven Segment Displays (Common Anode / Common Cathode)

Following ICs and their Datasheets

7447 / 7448 BCD to Seven Segment Driver

Theory

Seven Segment Displays

A 7-Segment display consists of seven light-emitting elements. The segments are designated by letters a
through (figure 9.1). By illuminating various combinations of segments, the numerals 0 through
can be displayed. Seven Segment displays are commonly constructed with light- emitting diode
(LEDs) and with liquid-crystal displays (LCDs). LEDs generally provide greater illumination levels but
require much greater power than LCDs. An LED can be a common-anode type or common cathode type.
In common anode type, a high voltage is applied at the common terminal of the display and low voltage is
applied at a segment’s terminal for illumination. In the common cathode type, a high voltage is applied at
the common terminal of the display and low voltage is applied at a segment’s terminal for illumination.

Figure 11.1

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7448 BCD to Seven Segment Driver

7448 IC is particularly used to drive Seven Segment. Its input is a BCD number and output
drives a Seven Segment display. 7448 is used to drive common-anode displays whereas 1s
used to drive common cathode displays. 7448 is a 16 pin IC. Function of various pins of
these ICs is described below:

1. A, B, C, D: Inputs representing BCD digits (D being the MSB).

2. OA through OG: Outputs to drive segments a through g of the display. (Active low in 7447 and
active high in 7448).
3. RBI: Ripple Blanking Input. Turns off all the segments if kept low, provided that LT is kept high
and all other inputs (A, B, C, D, BI) are kept low. Should be kept high otherwise.
4. BI/RBO: Wire-AND logic serving as a Blanking Input and / or Ripple Blanking Output.
5. BI: Turns off all the segments if low.
6. RBO: Goes to a low level (response condition) along with other outputs, when RBI and inputs A, B,
C, and D are low with LT input at high level.
7. LT: Lamp Test input. Tests whether all segments are working or not. Illuminates all segments if kept
low, provided that BI is kept high. Should be kept high other wise.Vcc and GND: Supply connections
lines

Figure 11.2
Implementation & Observation

• Make connections as shown in the circuit diagram (refer to laboratory session 01 or implementation
procedure).
• Apply different combinations of is and 0s at data inputs.

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Observe the output and record your observations in the following table.

Decimal BCD Inputs Seven Segment Outputs

Digit
D C B A a b c d e f g
0 0 0 0 0
1 0 0 0 1
2 0 0 1 0
3 0 0 1 1
4 0 1 0 0
5 0 1 0 1
6 0 1 1 0
7 0 1 1 1
8 1 0 0 0
9 1 0 0 1

Task 11.1: Design a seven-segment driver using logic gates.

Conclusion:
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LAB – 12

Objectives:
Construct RS Latch Using NAND gate, testing of JK flip-flop and develop D- Flip-Flop using JK FF.

Components & Apparatus Required

• Digital logic trainer / Bread board

• 5 V - Power Supply
• Multimeter
• Logic Probe
• LEDs with Resistors
• Connecting wires

Following ICs and their Datasheets

7473 / 7476 JK Flip-Flop

Theory:

Latch
A Latch circuit can maintain a binary state indefinitely (as long as the power is delivered to the circuit)
until directed by an input signal to switch states. The major differences among various types of
Latches are in the number of inputs they posses and in the manner in which the inputs affect the binary
state. The figure of SR latch is given in figure below.

Figure 12.1:
SR Latch

JK Flip-Flop
JK flip-flop is an edge triggered device. A typical flip flop has three inputs: J, K and a clock
input. The flip-flop can be either positive or negative edge triggered. The output Q is available in
complemented form as well.

Beside the usual inputs and output, most of the flip-flop IC also possess two asynchronous inputs,
namely preset and Clear. These inputs are usually active low. If used Preset and Clear inputs keep the
flip-flop in set and reset state respectively, irrespective of the other inputs. Both of these inputs
cannot be used simultaneously, otherwise they will bring the flipflop in unstable state.

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(a) Positive-edge triggering

(b) Active low Preset (PR) and Clear (CLR) with positive-edge triggering
(c) Active low Preset (PR) and Clear (CLR) with negative-edge triggering

Testing Of 7473 / 7476 Dual JK Flip-Flop

Both the ICs 7473 and 7476 are similar in functionality except for one difference. The flipflops in 7473
have only one type of active low asynchronous input, which is the Clear input, whereas the flip-
flops in 7476 have both preset and Clear inputs. Both these ICs have negative edge triggered flip-flops.

Circuit Diagram

Figure 12.2: Pin connections of 7476

Testing Procedure

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1. Make connections as shown in the diagram (Figure 1 and Figure 2).

2. Apply different combinations of 1s and 0s at S and R inputs
3. Apply different combinations of 1s and 0s at J and K inputs
4. Observe the output and record your observations in the following table.

Observations

S R Q
0 0
0 1
1 0
1 1

J K Q
0 0
0 1
1 0
1 1

Task 12.1: Design a D-Flip Flop using JK-Flip Flop.

Conclusion:
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 FACULTY OF ENGINEERING SCIENCES AND TECHNOLOGY

LAB#13
Objective:
Design 4-bit Up/Down counter using IC 74193.

Components & Apparatus Required

• Digital logic trainer / Bread board.

• DC Power supply (5V & V).
• Logic probe.
• IC 74193 (1No.)

Theory

In this experiment, you will observe the working of synchronous 4-bit binary UP / DOWN counter IC. You
will see how counter can be preset to a number and can be made count from there both upward and
downward. You will also see how counters also act as frequency dividers.

Procedure & Observations

1. Connect the circuit as shown below.

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2. Connect the clear input (pin#14) to logic High and observe the outputs of Counter (pin#7,6,2,3) by
connecting them to Logic probe (or LEDs).

QD, QC, QB, QA =

Connect pin#14 back to logic low.

3. Connect the data inputs (D, C, B, A i.e. pin#9, 10, 1, 15) to logic 0110.
4. Now, activate the LOAD input (pin#11) by connecting it to logic Low (0V). What do you observe
at the outputs (pin#7,6,2,3).

QD, QC, QB, QA =

You will see that the counter will be preset to the data loaded into it (0110).
Connect Load input back to logic High (5V).

5. At the count UP clock input (pin#5) connect the pulse-wave output of frequency 1Hz. Now
what do you observe?

6. Observe the output at carry (pin#12). How will you relate this output to the four outputs QD,
QC, QB, QA?

7. Now change the pulse-wave output of frequency 1 Hz from the count UP clock input (pin#5)
to the count DOWN clock input (pin#4). What do you observe at the outputs?

8. Observe the output at Borrow (pin#13). How will you relate this output to the four outputs QD, QC,
QB, QA?

9. Now set the square-wave generator frequency at 10 KHz and voltage at 5V then connect its
output to pin#4. Observe the signal at pin#4 and pin#13 on oscilloscope Ch-1 & 2 and measure the
frequency of both outputs.

Fclk = fBorrow =

Task 13.1: Design an 8-bit up and down counter.

Conclusion:
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 FACULTY OF ENGINEERING SCIENCES AND TECHNOLOGY

LAB-14
Objectives:
Construct Serial in Serial out shift register using JK Flip Flop and implement it using 74273 IC.

Component & Apparatus Required

• Bread board/Digital Logic Trainer

• 5 V - Power Supply
• Logic Probe
• LEDs with Resistors
• Connecting Wires
• 74273

Theory

In digital electronics register (or shift register) is combination of flip-flops in such a

Manner that the data is shifted down the line from input to output. They can be combined for serial inputs
and parallel inputs as well as serial outputs and parallel outputs. So there are four types of registers: Serial
in Serial out (SISO), Serial in Parallel Out (SIPO), Parallel In Serial Out (PISO) and Parallel In Parallel
Out (PIPO). The register, in digital circuitry, can be used as data storage device, convert the data between
serial and parallel interface etc.
IC 74273 contains 8 D type flip-flops. The following are pin description of IC 74273.

• 1D through 8D active high data inputs.

• 1Q through 8Q active high data outputs.
• CLR active low clear for resetting the flip-flops.
• VCC and GND: Supply connections line.

Serial in Serial out (SISO) register (4-bit data) can be implemented by using the 4 D flip- flops as show
below:

Figure 14.1

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Figure 14.2

Implementation & Observation

• Make connections using figure 1 and figure 2.

• Set the clock at 1000 Hz 5 V square wave from function generator.
• Apply different combinations of 1s and 0s at data inputs.
• When you apply logic 0 at clear input then register reset and as it is active low and when you reset it
to logic 1 then the register will give the output.
• Observe the output and record your observations in the following table.

Observation Table

Clear I/P Data I/Ps Data O/Ps

0 1
1 0
1 1
1 0
1 0
1 1

Task 14.1: Construct Serial in Parallel out shift register.

Conclusion:
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 FACULTY OF ENGINEERING SCIENCES AND TECHNOLOGY

Experiment no:15
Open-Ended LAB

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Experimental Setup:
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Procedure:
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Experimental Results:
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