Digital System Design (EC303PC)

COURSE FILE
Subject (Name) : Digital System Design
Name (of the Faculty Member) : Bavusaheb. B. Kunchanur
Designation : Asst. Professor
Regulation /Course : R 18 / EC303PC
Code
Year / Semester : III / I
Department : Electronics and Communication
Engineering

Academic Year : 2019-20

BAVUSAHEB.B.KUNCHANUR, Assistant Professor, Dept of ECE

 Digital System Design (EC303PC)

DEPARTMENT OF
ELECTRONICS AND
COMMUNICATION ENGINEERING

R-18

DIGITAL SYSTEM DESIGN

II B. Tech
2019-20
Course File Prepared by

BAVUSAHEB B KUNCHANUR
Assistant Professor

HOD Principal

BAVUSAHEB.B.KUNCHANUR, Assistant Professor, Dept of ECE

 Digital System Design (EC303PC)

COURSE FILE CONTENTS

S.No. Topics Page No.

1 Vision, Mission, PEO’s, PO’s & PSO’S
2 Syllabus (University Copy)
3 Course Objectives, Course Outcomes And Topic Outcomes
4 Course Prerequisites
5 Course Information Sheet (CIS)
a). Course Description
b). Syllabus
c). Gaps in Syllabus
d). Topics beyond syllabus
e). Web Sources-References
f). Delivery / Instructional Methodologies
g). Assessment Methodologies-Direct
h). Assessment Methodologies –Indirect
i). Text books & Reference books
6 Micro Lesson Plan
7 Teaching Schedule
8 Unit Wise Hand Written notes
9 OHP/LCD SHEETS /CDS/DVDS/PPT (Soft/Hard copies)
10 University Previous Question papers
11 MID exam Descriptive Question Papers
12 MID exam Objective Question papers
13 Assignment topics with materials
14 Tutorial topics and Questions
15 Unit wise-Question bank
1 Two marks question with answers 5 questions
2 Three marks question with answers 5 questions
3 Five marks question with answers 5 questions
4 Objective question with answers 10 questions
5 Fill in the blanks question with answers 10 questions
16 Course Attainment
17 CO-PO Mapping
18 Beyond syllabus Topics with material
19 Result Analysis-Remedial/Corrective Action
20 Record of Tutorial Classes
21 Record of Remedial Classes
22 Record of guest lecturers conducted

BAVUSAHEB.B.KUNCHANUR, Assistant Professor, Dept of ECE

 Digital System Design (EC303PC)

Part – 2

S.NO TOPICS
1 Attendance Register/Teacher Log Book

2 Time Table

3 Academic calendar

4 Continuous Evaluation – marks (Test, Assignments etc)

5 Status Report Internal Exams & Syllabus coverage

6 Teaching Dairy/Daily Delivery Record Micro lesson Plan

7 Continuous Evaluation – MID marks

8 Assignment Evaluation-marks/Grades

9 Special Descriptive Tests Marks

10 Sample students descriptive answer sheets

11 Sample students assignment sheets

BAVUSAHEB.B.KUNCHANUR, Assistant Professor, Dept of ECE

 Digital System Design (EC303PC)

1. a). Vision
To be renowned department imparting both technical and non-technical skills to the
students through implementing new engineering pedagogy and research to produce
competent new age electrical engineers

1. b). Mission
➢ To transform the students into motivated and knowledgeable new age electrical
engineers.
➢ To advance the quality of education to produce world class technocrats with an ability to
adapt to the academically challenging environment.
➢ To provide a progressive environment for learning through organized teaching
methodologies, contemporary curriculum and research in the thrust areas of electrical
engineering

1. c). Program Educational Objectives

PEO 1: Apply their knowledge and skills to provide solutions to electrical and electronics
engineering problems in industry and governmental organizations or to enhance student
learning in educational institutions
PEO 2: Work as a team with a sense of ethics and professionalism, and communicate effectively
to manage cross-cultural and multidisciplinary teams.
PEO 3:Update their knowledge continuously through lifelong learning that contributes to
personal and organizational growth.

d) Program Objectives
PO1. Apply knowledge of Mathematics, Science and Engineering to solve the complex problems in
Electrical and Electronics Engineering.
PO2. Identify, formulate, design, analyze and implement an electrical and electronics system,
component, or process to meet desired needs.
PO3. Design system components that meet economic, environmental, social, political, ethical,
health and safety and sustainability requirements.
PO4. Conduct investigations of complex engineering problems including design of experiments,
analysis and interpretation of data, and synthesis of information to provide valid
conclusions.
PO5. Construct, select and apply appropriate techniques, resources, and modern simulation tools
to solve complex electrical and electronics circuits.

BAVUSAHEB.B.KUNCHANUR, Assistant Professor, Dept of ECE

 Digital System Design (EC303PC)

PO6. Apply contextual knowledge to assess social, health, safety and cultural issues and endure
the responsibilities relevant to professional engineering practice.
PO7. Utilize core engineering knowledge in a global, economic, environmental and societal
context for sustainable development.
PO8. Solve professional, legal and ethical issues pertaining to core engineering and its related
fields.
PO9. Function effectively as a team member or a leader to accomplish a common goal in a
multi- disciplinary team.
PO10. Communicate effectively with the engineers and society at large through the ability to
comprehend and write effective reports, make effective presentations, give and receive
clear instructions.
PO11. Apply knowledge of engineering and management principles to manage projects
effectively in diverse environments as a member or leader of a team.
PO12. Engage in independent and lifelong learning for continued professional development.

BAVUSAHEB.B.KUNCHANUR, Assistant Professor, Dept of ECE

 Digital System Design (EC303PC)

2) Syllabus (University Copy)

BAVUSAHEB.B.KUNCHANUR, Assistant Professor, Dept of ECE

 Digital System Design (EC303PC)

BAVUSAHEB.B.KUNCHANUR, Assistant Professor, Dept of ECE

 Digital System Design (EC303PC)

3.a) COURSE OBJECTIVES

• To understand common forms of number representation in logic circuits
• To learn basic techniques for the design of digital circuits and fundamental
concepts used in the design of digital systems.
• To understand the concepts of combinational logic circuits and sequential circuits.
• To understand the Realization of Logic Gates Using Diodes & Transistors.
• To implement synchronous state machines using flip-flops
3.b) COURSE OUTCOMES
After completion of the course the students will be able to
CO 1: Develop a digital logic and apply it to solve real life problems.
CO2: Develop competence in Combinational Logic Problem formulation and Logic
Optimization
CO3: Develop competence in analysis of synchronous and asynchronous sequential
circuits
CO4: Analyze and solve various engineering problems with finite state machine
CO5: Design and analyze Logic gates with different technologies

CO1: Develop a digital logic and apply it to solve real life problems
CO2: Analyze and design combinational circuits.
CO3: Analyze and design sequential circuits.
CO4:
CO5:

BAVUSAHEB.B.KUNCHANUR, Assistant Professor, Dept of ECE

 Digital System Design (EC303PC)

3.c) TOPIC OUTCOMES

Sl.No Topic Outcome
1 Introduction about Switching theory Introduction
and logic design
2 Unit I:Number System and Boolean Number System and Bolean algebra
algebra And Switching Functions
:Review of number systems
3 Complements of Numbers Complements of Numbers
4 Codes-Binary Codes Codes-Binary Codes
5 Binary Coded Decimal Code and its Binary Coded Decimal Code and its Properties
Properties
6 Unit Distance Codes Unit Distance Codes
7 Error Detecting and Correcting Error Detecting and Correcting Codes.
Codes.
8 Boolean Algebra: Basic Theorems Boolean Algebra: Basic Theorems and Properties
and Properties
9 Switching Functions Switching Functions
10 Canonical and Standard Form Canonical and Standard Form
11 Algebraic Simplification of Digital Algebraic Simplification of Digital Logic Gates
Logic Gates
12 Properties of XOR Gates Properties of XOR Gates
13 Universal Gates Universal Gates
14 Multilevel NAND/NOR Multilevel NAND/NOR realizations.
realizations.
15 Problems & Revision Problems & Revision
16 UNIT - II Minimization and Minimization and Design of Combinational Circuits:
Design of Combinational Circuits: Introduction
Introduction
17 The Minimization of switching The Minimization of switching function using theorem
function using theorem
18 The Karnaugh Map Method-Up to The Karnaugh Map Method-Up to Five Variable Maps
Five Variable Maps
19 Don’t Care Map Entries Don’t Care Map Entries

BAVUSAHEB.B.KUNCHANUR, Assistant Professor, Dept of ECE

 Digital System Design (EC303PC)

20 Tabular Method Tabular Method

21 Design of Combinational Logic: Design of Combinational Logic: Adders
Adders
22 Subtractors, comparators Subtractors, comparators
23 Multiplexers, De multiplexers Multiplexers, De multiplexers
24 Decoders Decoders
25 Encoders and Code converters Encoders and Code converters
26
Hazards and Hazard Free Relations Hazards and Hazard Free Relations

27 Revision Revision
28 UNIT - III Sequential circuits Sequential Machines Fundamentals and Applications:
Fundamentals and Applications: Introduction
Introduction
29 Basic Architectural Distinctions Basic Architectural Distinctions between
between Combinational and Combinational and Sequential circuits
Sequential circuits
30 The Binary Cell, Fundamentals of The Binary Cell, Fundamentals of Sequential Machine
Sequential Machine Operation Operation
31 Latches, Flip Flops: SR Latches, Flip Flops: SR
32 JK, Race Around Condition in JK JK, Race Around Condition in JK
33 JK Master Slave, D and T Type Flip JK Master Slave, D and T Type Flip Flops
Flops
34 Excitation Table of all Flip Flops Excitation Table of all Flip Flops
35
Design of a Clocked Flip-Flop, Design of a Clocked Flip-Flop, Timing and Triggering
Timing and Triggering Consideration
Consideration

36 Clock Skew, Conversion from one Clock Skew, Conversion from one type of Flip-Flop to
type of Flip-Flop to another. another.
37 Registers and Counters: Shift Registers and Counters: Shift Registers
Registers

BAVUSAHEB.B.KUNCHANUR, Assistant Professor, Dept of ECE

 Digital System Design (EC303PC)

38 Data Transmission in Shift Data Transmission in Shift Registers

Registers
39 Operation of Shift Registers Operation of Shift Registers
40 Shift Register Configuration Shift Register Configuration
41 Bidirectional Shift Registers, Bidirectional Shift Registers, Applications of Shift
Applications of Shift Registers Registers
42 Design and Operation of Ring and Design and Operation of Ring and Twisted Ring
Twisted Ring Counter Counter
43 Operation Of Asynchronous And Operation Of Asynchronous And Synchronous
Synchronous Counters. Counters.
44 Revision Revision
45 Unit IV: Sequential Circuits - I: Sequential Circuits - I: Introduction, State Diagram
Introduction, State Diagram
46 Analysis of Synchronous Sequential Analysis of Synchronous Sequential Circuits
Circuits
47 Approaches to the Design of Approaches to the Design of Synchronous Sequential
Synchronous Sequential Finite State Finite State Machines
Machines
48 Synthesis of Synchronous Synthesis of Synchronous Sequential Circuits
Sequential Circuits
49 Serial Binary Adder, Sequence Serial Binary Adder, Sequence Detector
Detector
50 Parity-bit Generator, Design of Parity-bit Generator, Design of Asynchronous Counters
Asynchronous Counters
51 Design of Synchronous Modulo N – Design of Synchronous Modulo N –Counters.
Counters.
52 Revision Revision
53 Unit V: Realization of Logic Gates AND, OR and NOT Gates using Diodes
Using Diodes & Transistors and Transistors
54 DCTL, RTL, DTL, TTL, CML and Different logic families and their comparison
CMOS Logic Families and its
Comparison
55 DCTL, RTL, DTL, TTL, CML and Different logic families and their comparison

BAVUSAHEB.B.KUNCHANUR, Assistant Professor, Dept of ECE

 Digital System Design (EC303PC)

CMOS Logic Families and its

Comparison
56 Classification of Integrated circuits, Differentiate logic families
comparison of various logic
families
57 standard TTL NAND Gate- standard TTL NAND Gate-
Analysis & characteristics, Analysis & characteristics,
58 TTL open collector O/Ps, Tristate TTL open collector O/Ps, Tristate TTL, MOS & CMOS
TTL, MOS & CMOS open drain open drain and tristate outputs
and tristate outputs
59 CMOS transmission gate, IC CMOS transmission gate, IC interfacing- TTL driving
interfacing- TTL driving CMOS & CMOS & CMOS driving TTL.
CMOS driving TTL.
60 Revision Revision

4. COURSE PRE–REQUISITES
1. Basic knowledge of mathematics

BAVUSAHEB.B.KUNCHANUR, Assistant Professor, Dept of ECE

 Digital System Design (EC303PC)

5.a). COURSE DESCRIPTION:

PROGRAMME: B.Tech (Electrical & Electronics DEGREE: BTECH

Engineering)
COURSE: DIGITAL SYSTEM DESIGN YEAR: II SEM: I CREDITS: 3
COURSE CODE: EC303PC COURSE TYPE: CORE
REGULATION: R16
COURSE AREA/DOMAIN: CORE CONTACT HOURS: 3+1 (L+T))
hours/Week.
CORRESPONDING LAB COURSE CODE (IF LAB COURSE NAME: DIGITAL SYSTEM
ANY): DESIGN LAB
YES

5.b). SYLLABUS:
Unit Details Hours
Number Systems: Number systems, Complements of Numbers, Codes- Weighted
and Non-weighted codes and its Properties, Parity check code and Hamming code.
I Boolean Algebra: Basic Theorems and Properties, Switching Functions- 15
Canonical and Standard Form, Algebraic Simplification, Digital Logic Gates, EX-
OR gates, Universal Gates, Multilevel NAND/NOR realizations.
Minimization of Boolean functions: Karnaugh Map Method - Up to five
Variables, Don’t Care Map Entries, Tabular Method, Combinational Logic
II 12
Circuits: Adders, Subtractors, Comparators, Multiplexers, Demultiplexers,
Encoders, Decoders and Code converters, Hazards and Hazard Free Relations
Sequential Circuits Fundamentals: Basic Architectural Distinctions between
Combinational and Sequential circuits, SR Latch, Flip Flops: SR, JK, JK Master
Slave, D and T Type Flip Flops, Excitation Table of all Flip Flops, Timing and
III Triggering Consideration, Conversion from one type of Flip-Flop to another. 17
Registers and Counters: Shift Registers – Left, Right and Bidirectional Shift
Registers, Applications of Shift Registers - Design and Operation of Ring and
Twisted Ring Counter, Operation of Asynchronous and Synchronous Counters
Sequential Machines: Finite State Machines, Synthesis of Synchronous
Sequential Circuits- Serial Binary Adder, Sequence Detector, Parity-bit Generator,
IV 8
Synchronous Modulo N –Counters. Finite state machine-capabilities and
limitations, Mealy and Moore models
Realization of Logic Gates Using Diodes & Transistors: AND, OR and NOT
Gates using Diodes and Transistors, DCTL, RTL, DTL, TTL, CML and CMOS
V 8
Logic Families and its Comparison, Classification of Integrated circuits,
comparison of various logic families, standard TTL NAND GateAnalysis &

BAVUSAHEB.B.KUNCHANUR, Assistant Professor, Dept of ECE

 Digital System Design (EC303PC)

characteristics, TTL open collector O/Ps, Tristate TTL, MOS & CMOS open drain
and tristate outputs, CMOS transmission gate, IC interfacing- TTL driving CMOS
& CMOS driving TTL.
Contact classes for syllabus coverage 60
Tutorial classes 05
Classes for beyond syllabus 01
Total No. of classes 66

5. d). TOPICS BEYOND SYLLABUS/ADVANCED TOPICS:

1 Digital design using verilog NPTEL

5. e). WEB SOURCE REFERENCES:

Sl. No. Name of book/ website
a. http://nptel.ac.in/courses/117105080/1

b. http://nptel.ac.in/courses/117105080/2

c. http://nptel.ac.in/courses/117105080/5

5. f). DELIVERY/INSTRUCTIONAL METHODOLOGIES:

 CHALK & TALK  STUD. ASSIGNMENT  WEB RESOURCES
 LCD/SMART BOARDS  STUD. SEMINARS ☐ ADD-ON COURSES

5.g). ASSESSMENT METHODOLOGIES-DIRECT

 ASSIGNMENTS  STUD.  TESTS/MODEL  UNIV.
SEMINARS EXAMS EXAMINATION
 STUD. LAB  STUD. VIVA ☐ MINI/MAJOR ☐CERTIFICATIONS
PRACTICES PROJECTS
☐ADD-ON COURSES ☐ OTHERS

5.h). ASSESSMENT METHODOLOGIES-INDIRECT

 ASSESSMENT OF COURSE OUTCOMES  STUDENT FEEDBACK ON
(BY FEEDBACK, ONCE) FACULTY (TWICE)
☐ASSESSMENT OF MINI/MAJOR PROJECTS ☐ OTHERS
BY EXT. EXPERTS

BAVUSAHEB.B.KUNCHANUR, Assistant Professor, Dept of ECE

 Digital System Design (EC303PC)

5.i). TEXT/REFERENCE BOOKS:

T/R BOOK TITLE/AUTHORS/PUBLICATION
Text Book Switching and Finite Automata Theory- ZviKohavi&NirajK. Jha, 3rdEdition,
Cambridge.
Text Book DigitalDesign-MorrisMano,5rdEdition,Pearson.
Reference
Modern Digital electronics RPJain4thEdition,McGrawHill
Book
Reference
SwitchingTheoryandLogicDesign–AAnandKumar,3rdEdition,PHI,
Book

BAVUSAHEB.B.KUNCHANUR, Assistant Professor, Dept of ECE

 Digital System Design (EC303PC)

6. MICRO LESSION PLAN

Topic wise Coverage [Micro Lesson Plan]

S.No. Topic Scheduled date Actual date

1 Introduction about Switching theory and logic

design
2 Unit I:Number System and Boolean algebra
And Switching Functions :Review of number
systems
3 Complements of Numbers

4 Codes-Binary Codes
5 Binary Coded Decimal Code and its Properties
6 Unit Distance Codes

7 Error Detecting and Correcting Codes.

8 Boolean Algebra: Basic Theorems and

Properties
9 Switching Functions

10 Canonical and Standard Form

11 Algebraic Simplification of Digital Logic Gates

12 Properties of XOR Gates

13 Universal Gates

14 Multilevel NAND/NOR realizations.

15 Problems & Revision

16 UNIT - II Minimization and Design of
Combinational Circuits: Introduction
17 The Minimization of switching function using
theorem
18 The Karnaugh Map Method-Up to Five

BAVUSAHEB.B.KUNCHANUR, Assistant Professor, Dept of ECE

 Digital System Design (EC303PC)

Variable Maps
19 Don’t Care Map Entries
20 Tabular Method
21 Design of Combinational Logic: Adders
22 Subtractors, comparators
23 Multiplexers, De multiplexers
24 Decoders
25 Encoders and Code converters
26 Hazards and Hazard Free Relations
27 Revision
28 UNIT - III Sequential Machines Fundamentals
and Applications: Introduction
29 Basic Architectural Distinctions between
Combinational and Sequential circuits
30 The Binary Cell, Fundamentals of Sequential
Machine Operation
31 Latches, Flip Flops: SR
32 JK, Race Around Condition in JK
33 JK Master Slave, D and T Type Flip Flops
34 Excitation Table of all Flip Flops
35 Design of a Clocked Flip-Flop, Timing and
Triggering Consideration
36 Clock Skew, Conversion from one type of Flip-
Flop to another.
37 Registers and Counters: Shift Registers
38 Data Transmission in Shift Registers
39 Operation of Shift Registers
40 Shift Register Configuration
41 Bidirectional Shift Registers, Applications of
Shift Registers
42 Design and Operation of Ring and Twisted Ring
Counter
43 Operation Of Asynchronous And Synchronous

BAVUSAHEB.B.KUNCHANUR, Assistant Professor, Dept of ECE

 Digital System Design (EC303PC)

Counters.
44 Revision
45 UNIT – IV Sequential Circuits - I: Introduction,
State Diagram
46 Analysis of Synchronous Sequential Circuits
47 Approaches to the Design of Synchronous
Sequential Finite State Machines
48 Synthesis of Synchronous Sequential Circuits
49 Serial Binary Adder, Sequence Detector
50 Parity-bit Generator, Design of Asynchronous
Counters
51 Design of Synchronous Modulo N –Counters.
52 Revision
53 Unit V: Realization of Logic Gates Using
Diodes & Transistors
54 DCTL, RTL, DTL, TTL, CML and CMOS
Logic Families and its Comparison
55 DCTL, RTL, DTL, TTL, CML and CMOS
Logic Families and its Comparison
56 Classification of Integrated circuits, comparison
of various logic families
57 standard TTL NAND Gate-
Analysis & characteristics,
58 TTL open collector O/Ps, Tristate TTL, MOS &
CMOS open drain and tristate outputs
59 CMOS transmission gate, IC interfacing- TTL
driving CMOS & CMOS driving TTL.
60 Revision

BAVUSAHEB.B.KUNCHANUR, Assistant Professor, Dept of ECE

 Digital System Design (EC303PC)

7). Teaching Schedule

Text Books
Book 1 Switching and Finite Automata Theory- ZviKohavi&NirajK. Jha, 3rdEdition,
Cambridge.
Book 2 DigitalDesign-MorrisMano,5rdEdition,Pearson.
Reference Books
Book 3 Modern Digital electronics RPJain4thEdition,McGrawHill
Book 4 SwitchingTheoryandLogicDesign–AAnandKumar,3rdEdition,PHI,
Chapters No’s No of
Unit Topic Book 1 Book 2 Book 3 Book 4 classes

Review of number systems 1 1 7

Error detecting and correcting

I 1 3
codes

Boolean Algebra 2 2 5

The Minimization of switching

3 3 3
functions using K-MAP

Design of Combinational Logic 4 4 7

II Hazards and Hazard Free

4 2
Relations

Latches, Flip Flops 5 6 5

Conversion from one type of 6

III 5 4
Flip-Flop to another.

Registers and Counters 6 6 8

State Diagram, Analysis of

6 2
Synchronous Sequential Circuits
IV Synthesis of Synchronous
6 3
Sequential Circuits

BAVUSAHEB.B.KUNCHANUR, Assistant Professor, Dept of ECE

 Digital System Design (EC303PC)

Design of Synchronous Modulo

6 3
N
Mealy and Moore models 7 2

minimization of completely
specified and incompletely 7 3
V specified sequential machines

Partition techniques 7 3

Contact classes for syllabus coverage 60

Tutorial classes 05
Classes for Beyond syllabus 01
Total No. of classes 66

BAVUSAHEB.B.KUNCHANUR, Assistant Professor, Dept of ECE

 Digital System Design (EC303PC)

8) HAND WRITTEN NOTES

9) OHP/LCD SHEETS /CDS/DVDS/PPT

(Soft/Hard copies)

BAVUSAHEB.B.KUNCHANUR, Assistant Professor, Dept of ECE

 Digital System Design (EC303PC)

10) UNIVERSITY QUESTION PAPERS

11) MID exam Descriptive Question Papers

12) MID exam Objective Question papers

BAVUSAHEB.B.KUNCHANUR, Assistant Professor, Dept of ECE

 Digital System Design (EC303PC)

13) Assignment Topics

UNIT-I
1. Number system and base conversions
2. Complement of numbers
3. Error detecting and correcting code
4. Canonical and standard form
5. Realization of NAND, NOR Gates
UNIT-II
1. The K-Map Method of minimization
2. Tabulation method of minimization
3. Design of adders and subtractors
4. Design of multiplexers and demultiplexers
5. Encoders and code converters
UNIT-III
1. Fundamentals of Sequential Machine Operation
2. Latches, Flip Flops: SR
3. Excitation Table of all Flip Flops
4. Shift Registers
5. Conversion from one type of Flip-Flop to another.
UNIT-IV
1. Analysis of Synchronous Sequential Circuits
2. Serial Binary Adder
3. Sequence Detector
4. Parity-bit Generator
5. Design of Synchronous Modulo N –Counters.
UNIT-V
1. Limitations of finite state machine
2. Mealy model minimization
3. Moore model minimization
4. Partition techniques
5. Merger chart methods

BAVUSAHEB.B.KUNCHANUR, Assistant Professor, Dept of ECE

 Digital System Design (EC303PC)

14 TUTORIAL TOPICS AND

QUESTIONS

BAVUSAHEB.B.KUNCHANUR, Assistant Professor, Dept of ECE

 Digital System Design (EC303PC)

15) UNIT WISE-QUESTION BANK

UNIT 1

TWO-MARK QUESTIONS:

1. Represent binary number 1101 - 101 in power of 2 and find its decimal equivalent
N = 1 x 2 3 + 1 x 2 2 + 0 x 2 1 + 1 x 2 0 + 1 x 2 -1 + 0 x 2 -2 + 1 x 2 -3 = 13.625 10
2. Convert (634) 8 to binary
634
110 011 100
= 110 011 100
3. Convert (9 B 2 - 1A) H to its decimal equivalent.
N = 9 x 16 2 + B x 16 1 + 2 x 16 0 + 1 x 16 -1 + A (10) x 16 -2
= 2304 + 176 + 2 + 0.0625 + 0.039
= 2482.1 10
4. What are the different classifications of binary codes?
1. Weighted codes 2. Non - weighted codes 3. Reflective codes 4. Sequential codes 5.
Alphanumeric codes 6. Error Detecting and correcting codes
5.Convert 0.640625 decimal numbers to its octal equivalent.
0.640625 x 8 = 5.125
0.125 x 8 = 1.0
Ans. = 0.640 625 10 = 0.51

THREE-MARK QUESTIONS:

1. Convert decimal number 22.64 to hexadecimal number.

16 22 -6
16 1 -1
0
0.64 x 16 = 10.24
0.24 x 16 = 3.84
0.84 x 16 = 13.44
.44 x 16 = 7.04
Ans. = (16. A 3 D 7) 16.3
2. What are the two steps in Gray to binary conversion?
The MSB of the binary number is the same as the MSB of the gray code number. So
write it down.
To obtain the next binary digit, perform an exclusive OR operation b/n the bit just written
down and the next gray code bit. Write down the result.

BAVUSAHEB.B.KUNCHANUR, Assistant Professor, Dept of ECE

 Digital System Design (EC303PC)

3. Convert 10111011 is binary into its equivalent gray code.

Binary Code: 1 0 1 1 1 0 1 0 1 1
Gray code: 1 1 1 0 0 1 1 0
1010
0011
1101
4. Find the excess -3 code and 9’s complement of the number 403 10
403
010000000011
001100110011+
0 1 1 1 0 0 1 1 0 1 1 0 excess 3 code
9’s complement 1 0 0 0 1 1 0 0 1 0 0 1
5. Simplify the following expression
y = (A + B) (A = C) (B + C)
= (A A + A C + A B + B C) (B + C)
= (A C + A B + B C) (B + C)
=ABC+ACC+ABB+ABC+BBC+BCC
=ABC=ABC

FIVE-MARK QUESTIONS:

1) What is number systems and explain the types of number system?

Ans: Numeric systems

A number system is a system of writing for expressing numbers. It is the mathematical notation
for representing numbers of a given set by using digits or other symbols in a consistent manner.
It provides a unique representation to every number and represents the arithmetic and algebraic
structure of the figures. It also allow us to operate arithmetic operations like addition, subtraction
and division

Types of number system

Binary Number System

• Represents two types of digits 0's and 1's, so the base of number system is 2.

• Uses two types of electronic pulses, where absence of pulse shows 0 and presence of
pulse shows 1.

• Each binary digit is called as bit.

BAVUSAHEB.B.KUNCHANUR, Assistant Professor, Dept of ECE

 Digital System Design (EC303PC)

• Left-most bit of a number is known as Most Significant Bit (MSB) and right-most bit is
known as Least Significant Bit (LSB). Its same for all number system.

• A group of 4 bit is called as nibble and group of 8 bit is called as byte.

• Value of digit is determined by the position of digit in the number, where lowest value is
for the right-most position and each successive position to the left has a higher place
value. Its same for all number system.

• Examples: a) (010101)2 b) (1010.101)2

Octal Number System

• Represents 8 types of digits from 0 to 7, so the base of number system is 8.

• It takes exactly three binary digits to represent an octal digit.

• Binary 000 is same as octal digit 0, binary 001 is same as octal 1, and so on.

• Insufficient to convert values into bytes(8 bit), so not widely used in computers.

• Examples: a) (03105)8 b) (4237.23)8

Decimal Number System

• Represents 10 types of digits from 0 to 9, so the base of number system is 10.

• This is the most familiar number system with everyone.

• Examples a) (582938)10 b) (3797.902)10

Hexadecimal Number System

• Represents 16 types of digits from 0 to 9 and alphabets from A to F, so the base of

number system is 16.

• Digits from 10 to 15 are represented as 10-A, 11-B, 12-C, 13-D, 14-E, 15-F.

• As numeric digits and alphabets are used to represent digits, this number system is also
called as alphanumeric number system.

• More complex number system and widely used in computer system.

• Examples: a) (AF38)16 b) (CE7.5B)16

2) Convert the following number system to its equivalent decimal number system?
a) Binary Number − 111012

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 Digital System Design (EC303PC)

b) Octal Number − 258

a)Ans:Steps

• Step 1 − Determine the column (positional) value of each digit (this depends on the
position of the digit and the base of the number system).

• Step 2 − Multiply the obtained column values (in Step 1) by the digits in the
corresponding columns.

• Step 3 − Sum the products calculated in Step 2. The total is the equivalent value in
decimal.

c) Given binary number 111012

• Step Binary Decimal Number
Number

Step 1 111012 ((1 × 24) + (1 × 23) + (1 × 22) + (0 × 21) + (1 ×

20))10

Step 2 111012 (16 + 8 + 4 + 0 + 1)10

Step 3 111012 2910

Binary Number − 111012 = Decimal Number − 291

b) Octal Number − 258

Ans:Octal Number − 258

Calculating Binary Equivalent −

Step 1 − Convert to Decimal

Step Octal Number Decimal Number

Step 1 258 ((2 × 81) + (5 × 80))10

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 Digital System Design (EC303PC)

Step 2 258 (16 + 5 )10

Step 3 258 2110

Octal Number − 258 = Decimal Number − 2110

Step 2 − Convert Decimal to Binary

Step Operation Result Remainder

Step 1 21 / 2 10 1

Step 2 10 / 2 5 0

Step 3 5/2 2 1

Step 4 2/2 1 0

Step 5 1/2 0 1

Decimal Number − 2110 = Binary Number − 101012

Octal Number − 258 = Binary Number − 101012

3) a) Find 2’S complement of (1 0 1 0 0 0 1 1) 2

b) Subtract (1 1 1 0 0 1) 2 from 1 0 1 0 1 1 2 using 2’s complement method
c)What are the advantages of 1’s complement subtraction?

Ans:

a) Given number (1 0 1 0 0 0 1 1) 2

0 1 0 1 1 1 0 0 1 1’s Complement

+00000001

0 1 0 1 1 1 0 1 0 2’s complement.

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 Digital System Design (EC303PC)

b) Given 1 0 1 0 1 1
+ 0 0 0 1 1 1--- 2’s comp. of 1 1 1 0 0 1
1 1 0 0 1 0 Ans. in 2’s complement form
- 0 0 1 1 1 0 Answer in true form.
c)
• The 1’s complement subtraction can be accomplished with an binary adder. Therefore,
this method is useful in arithmetic logic circuits.
• The is complement of a number is easily obtained by inverting each bit in the number
4) Explain the need for error detection and correction?

Ans:

Let the code-words be 10010101 and 11010100, it is possible to determine how many
corresponding bits differ, just EXCLUSIVE OR the two code-words, and count the number of
1’s in the result. The number of bits position in which code words differ is called the Hamming
distance. If two code words are a Hamming distance d-apart, it will require d single-bit errors to
convert one code word to other. The error detecting and correcting properties depends on its
Hamming distance.
• To detect d errors, you need a distance (d+1) code because with such a code there is no way
that d-single bit errors can change a valid code word into another valid code word. Whenever
receiver sees an invalid code word, it can tell that a transmission error has occurred.
• Similarly, to correct d errors, you need a distance 2d+1 code because that way the legal code
words are so far apart that even with d changes, the original codeword is still closer than any
other code-word, so it can be uniquely determined.
Types of errors: These interferences can change the timing and shape of the signal. If the signal
is carrying binary encoded data, such changes can alter the meaning of the data. These errors can
be divided into two types: Single-bit error and Burst error.
Single-bit Error : The term single-bit error means that only one bit of given data unit (such as a
byte, character, or data unit) is changed from 1 to 0 or from 0 to 1

Single bit errors are least likely type of errors in serial data transmission. To see why, imagine a
sender sends data at 10 Mbps. This means that each bit lasts only for 0.1 μs (micro-second). For
a single bit error to occur noise must have duration of only 0.1 μs (micro-second), which is very
rare. However, a single-bit error can happen if we are having a parallel data transmission. For

BAVUSAHEB.B.KUNCHANUR, Assistant Professor, Dept of ECE

 Digital System Design (EC303PC)

example, if 16 wires are used to send all 16 bits of a word at the same time and one of the wires
is noisy, one bit is corrupted in each word.
Burst Error
The term burst error means that two or more bits in the data unit have changed from 0 to 1 or
vice-versa. Note that burst error doesn’t necessary means that error occurs in consecutive bits.
The length of the burst error is measured from the first corrupted bit to the last corrupted bit.
Some bits in between may not be corrupted.

Error Detecting Codes Basic approach used for error detection is the use of redundancy, where
additional bits are added to facilitate detection and correction of errors.

Popular techniques are:

• Simple Parity check

• Two-dimensional Parity check

• Checksum

• Cyclic redundancy check

Error Correcting Codes: The techniques that we have discussed so far can detect errors, but do
not correct them. Error Correction can be handled in two ways.
• One is when an error is discovered; the receiver can have the sender retransmit the entire
data unit. This is known as backward error correction.
• In the other, receiver can use an error-correcting code, which automatically corrects
certain errors. This is known as forward error correction.
In theory it is possible to correct any number of errors atomically. Error-correcting codes are
more sophisticated than error detecting codes and require more redundant bits. The number of
bits required to correct multiple-bit or burst error is so high that in most of the cases it is
inefficient to do so. For this reason, most error correction is limited to one, two or at the most
three-bit errors.

BAVUSAHEB.B.KUNCHANUR, Assistant Professor, Dept of ECE

 Digital System Design (EC303PC)

5) Write a table stating all the postulates and theorems of Boolean Algebra that are
required for logic minimization?
Ans: Algebra deals with the rules or laws, which are known as laws of Boolean algebra by
which the logical operations are carried out.
There are also few theorems of Boolean algebra that are needed to be noticed carefully because
these make calculation fastest and easier. Boolean logic deals with only two variables, 1 and 0 by
which all the mathematical operations are to be performed.
Boolean algebra or switching algebra is a system of mathematical logic to perform different
mathematical operations in binary system. There only three basis binary operations, AND, OR
and NOT by which all simple as well as complex binary mathematical operations are to be done.
There are many rules in Boolean algebra by which those mathematical operations are done. In
Boolean algebra, the variables are represented by English Capital Letter like A, B, C etc and the
value of each variable can be either 1 or 0, nothing else. In Boolean algebra an expression given
can also be converted into a logic diagram using different logic gates like AND gate, OR
gate and NOT gate, NOR gates, NAND gates, XOR gates, XNOR gatesetc.

Some basic logical Boolean operations,

AND Operation

OR Operation

NotOperation

Some basic laws for Boolean Algebra

A. 0 = 0 where
A can be either 0 or 1.
A . 1 = A where A can be either 0 or 1.
A . A = A where A can be either 0 or 1.
A . Ā = 0 where A can be either 0 or 1.
A + 0 = A where A can be either 0 or 1.

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 Digital System Design (EC303PC)

A + 1 = 1 where A can be either 0 or 1.

A + Ā = 1
A + A = A
A + B = B + A where A and B can be either 0 or 1.
A . B = B . A where A and B can be either 0 or 1.

The laws of Boolean algebra are also true for more than two variables like,
Cumulative Law for Boolean Algebra

According to Cumulative Law, the order of OR operations and AND operations conducted on
the variables makes no differences.
Associative Laws for Boolean Algebra
This law is for several variables, where the OR operation of the variables result is same though
the grouping of the variables. This law is quite same in case of AND

operators.
Distributive Laws for Boolean Algebra
This law is composed of two operators, AND and OR. Let us
show one use of this law to prove the expression
Proof:

FILL IN THE BLANKS

1. Most computers store data in strings of ________ bits called a ________.

2. The ________ code represents alphanumeric characters as seven-bit binary numbers.
3. Hexadecimal 16 is ________ in decimal.
4. An unweighted code in which only one bit changes from one code number to the next is
________.

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 Digital System Design (EC303PC)

5. The largest BCD number that can be represented with four binary bits is ________.
6. The decimal number –128 is represented in the signed 2's complement system as
________.
7. The 2's complement of the binary number 1000 is ________.
8. The output of a NOR gate is HIGH if ________.
9. The Boolean expression for a 3-input AND gate is ________.
10. The DeMorgan's theorem to the expression is_________

ANSWERS:

Q.No Answer

1 8, byte

2 ASCII

3 2210

4 Gray

5 15

6 1000 0000

7 1000

8 all inputs are LOW

9 X = ABC

10

MULTIPLE CHOICE QUESTIONS

1. Which output expression might indicate a product-of-sums circuit construction?

A.

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 Digital System Design (EC303PC)

B.

C.

D.
2. Binary 0010111101111110 is ________ in hexadecimal.

A. 77F216

B. 4EEE16

C. 2F7E16

D. 2F7716

3. Hexadecimal AA is ________ in decimal

A. 16510

B. 17010

C. 18610

D. 17616
4. The output of an AND gate with three inputs, A, B, and C, is HIGH when ________.
A. A = 1, B = 1, C = 0

B. A = 0, B = 0, C = 0

C. A = 1, B = 1, C = 1

D. A = 1, B = 0, C = 1

5. One of De Morgan's theorems states that . Simply stated, this means that
logically there is no difference between
A. a NOR and an AND gate with inverted inputs

B. a NAND and an OR gate with inverted inputs

C. an AND and a NOR gate with inverted inputs

D. a NOR and a NAND gate with inverted inputs

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 Digital System Design (EC303PC)

6. A truth table for the SOP expression has how many input
combinations?
A. 1

B. 2

C. 4

D. 8

7. When grouping cells within a K-map, the cells must be combined in groups of ________.
A. 2s

B. 1, 2, 4, 8, etc.

C. 4s

D. 3s
8. Converting the Boolean expression LM + M(NO + PQ) to SOP form, we get ________
A. LM + MNOPQ

B. L + MNO + MPQ

C. LM + M + NO + MPQ

D. LM + MNO + MPQ
9. Derive the Boolean expression for the logic circuit shown below

B.

C.

D.

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 Digital System Design (EC303PC)

10. From the truth table below, determine the standard SOP expression.

A.

B.

C.

D.

ANSWERS:

Q. No 1 2 3 4 5 6 7 8 9 10

Answer D D B C A D D B D C

BAVUSAHEB.B.KUNCHANUR, Assistant Professor, Dept of ECE

 Digital System Design (EC303PC)

UNIT-II

TWO-MARK QUESTIONS:

1. What are combinational circuits?

A combinational circuit consists of logic gates whose outputs at any time are
determined from the present combination of inputs. A combinational circuit performs an
operation that can be specified logically by a set of Boolean functions. It consists of input
variables, logic gates.
2. Define magnitude comparator?
A magnitude comparator is a combinational circuit that compares two numbers, A
and B, and determines their relative magnitudes. The outcome of the comparison is
specified by three binary variables that indicate whether a>b, A = b, or A < B.
3. What are decoders?
A decoder is a combinational circuit that converts binary information from n input
lines to a maximum of2n unique output lines. If the n bit coded information has unused
combinations, he decoder may have fewer than 2n outputs.
4. What are encoders?
An encoder is a digital circuit that performs the inverse operation of a decoder. An
encoder has 2n and n output lines. The output lines generate the binary code
corresponding to the input value.
5. Define binary adder.
A binary adder is a digital circuit that produces the arithmetic sum of two binary
numbers. It can be constructed with full adders constructed in cascade, with the output
carry from each full adder connected to the input carry of the next full adder in the chain.

THREE-MARK QUESTIONS:

1. Give the design procedures for the designing of a combinational circuit.

The procedure involves the following steps, From the specification of the circuit,
determine the required number of inputs and outputs and assign a symbol to each. Derive
the truth table that defines the required relationships between inputs and outputs. Obtain
the simplified Boolean functions for each output as a function of the input variables.
Draw the logic diagram and verify the correctness of the design.

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 Digital System Design (EC303PC)

2. What is overflow?
Over flow is a problem in digital computers because the number of bits that hold
the number is finite and a result that contains n + 1 bits cannot be accommodated. For this
reason many computers detect the occurrence of an overflow, and when it occurs a
corresponding flip flop is set that can be checked by the user. An overflow condition can
be detected by observing the carry into sign bit position and the carry out of the sign bit
position. If these two carries are not equal, an overflow has occurred.

3. Define priority encoder?

A priority encoder is an encoder circuit that includes the priority function. The
operation of priority encoder is such that if two or more inputs are equal to 1 at the same
time, the input having the highest priority will take precedence.
4. Define binary decoder?
A decoder which has an n- bit binary input code and a one activated output out-of
-2n output code is called binary decoder. A binary decoder is used when it is necessary to
activate exactly one of 2n outputs based on an n-bit input value.

FIVE-MARK QUESTIONS:

1) Design 4 bit Gray to binary code converter?

Solution:
Gray to Binary:

No. Gray Binary

G3 G2 G1 G0 D C B A
0 0 0 0 0 0 0 0 0
1 0 0 0 1 0 0 0 1
2 0 0 1 1 0 0 1 0
3 0 0 1 0 0 0 1 1
4 0 1 1 0 0 1 0 0
5 0 1 1 1 0 1 0 1
6 0 1 0 1 0 1 1 0
7 0 1 1 0 0 1 1 1
8 1 1 0 0 1 0 0 0
9 1 1 0 1 1 0 0 1
10 1 1 1 1 1 0 1 0
11 1 1 1 0 1 0 1 1
12 1 0 1 0 1 1 0 0
13 1 0 1 1 1 1 0 1

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 Digital System Design (EC303PC)

14 1 0 0 1 1 1 1 0
15 1 0 0 0 1 1 1 1
Table : Gray to Binary Converter

Equations:

Diagram:

2) Design half adder and Full adders?

Answer:

Half Adder
A logic circuit block used for adding two one bit numbers or simply two bits is called as a half
adder circuit. This circuit has two inputs which accept the two bits and two outputs, with one
producing sum output and other produce carry output.
As we discussed above that binary addition is commonly performed by Ex-OR gate, but for the
first three rules , it performs the binary addition and when the two inputs are logic 1, it does not
develop any carry.
To accomplish the binary addition with Ex-OR gate, there is need of additional circuitry to
perform the carry operation. Hence, a half adder is formed by connecting AND gate to the input
terminals of the Ex-OR gate so as to produce the carry as shown in below figure.

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 Digital System Design (EC303PC)

In the above half adder , inputs are labeled as A and B. The sum output is labeled with the
summation symbol ?and the carry output or carry out is labeled with Co. Half adder is mainly
used for addition of augend and addend of first order binary numbers.
Half adder has limited number of applications, and practically not used in the application
especially multi-digit addition. In such applications carry of the previous digit addition must be
added along with two bits; hence it is three bits addition.

Full Adder

A binary full adder is a multiple output combinational logic network that performs the arithmetic
sum of three input bits. As we have seen that the half adder cannot respond to the three inputs
and hence the full adder is used to add three digits at a time.

It consists of three inputs, in which two are input variables represent the two significant bits to be
added, labeled as A and B, whereas the third input terminal is the carry from the previous lower
significant position and labeled as Cin. The two outputs are a sum and a carry outputs which are
labeledas ?andCout respectively.

Full adder can be formed by combining two half adders

and an OR gate as shown in above where output and
carry-in of the first adder becomes the input to the
second half adder that produce the total sum output. The
total carry out is produced by ORing the two half adder

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 Digital System Design (EC303PC)

carry outs as shown in figure. The full adder block diagram and truth table is shown below.

3) Explain how a full adder can be built using two half adders?

Answer:Half Adder: Half adder is a combinational circuit that performs simple addition of two

Schematic Representation of Half Adder

Full Adder

Full adder is a digital circuit used to calculate the sum of three binary bits which is the main
difference between this and half adder. Full adders are complex and difficult to implement
when compared to half adders. Two of the three bits are same as before which are A, the
augends bit and B, the addend bit. The additional third bit is carry bit from the previous stage
and is called Carry – in generally represented by CIN. It calculates the sum of three bits along
with the carry. The output carry is called Carry – out and is represented by COUT.The block
diagram of a full adder with A, B and CIN as inputs and S, CoUT as outputs is shown below

Schematic Representation of Full Adder

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 Digital System Design (EC303PC)

Implementation of Full Adder using Half Adders

A full adder can be formed by logically connecting two half adders. The block diagram that
shows the implementation of a full adder using two half adders is shown below.

We know the equations for S and COUT

from earlier calculations as

S = A ̅ B ̅ Cin + A ̅ BC ̅ in + ABCin

Cout = AB + ACin + BCin

We can rewrite the equation for sum as follows.

S = A ̅ B ̅ Cin + A ̅ BC ̅ in + ABCin

= Cin (A ̅ B ̅ + AB) + C ̅ in (A ̅ B + A B ̅ )

Therefore S = CIN XOR (A XOR B)

= Cin (A X-NOR B) + C ̅ in (A X-OR B)

= Cin XOR (A XOR B)

Cout is simplified as

COUT = A B + A CIN + B CIN.

COUT = AB + A CIN + B CIN (A + ̅A)

= ABCIN + AB + ACIN + ̅A B CIN

= AB (1 +CIN) + ACIN + ̅A B CIN

= A B + ACIN + ̅A B CIN

= AB + ACIN (B + ̅B ) + ¬ ̅A B CIN

= ABCIN + AB + A ̅B CIN + ̅A B CIN

= AB (CIN + 1) + A ̅B CIN + ̅A B CIN

= AB + A ̅B CIN + ̅A B CIN

= AB + CIN ( ̅AB + A ̅B )

Therefore COUT = AB + CIN (A EX – OR B)

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 Digital System Design (EC303PC)

4) Design 7 Segment Display Decoder Circuit?

Solution:

Segment Display Decoder Circuit Design

Step 1: The first step of the design involves analysis of the common cathode 7-segment display.
A 7-segment display consists of an arrangement of LEDs in an ‘H’ form. A truth table is
constructed with the combination of inputs for each decimal number. For example, decimal
number 1 would command a combination of b and c (refer the diagram given below).

7 Segment LED

Step 2: The second step involves constructing the truth table

listing the 7 display input signals, decimal number and
corresponding 4 digit binary numbers.

The truth table for the decoder design depends on the type of 7-
segment display. As we mentioned above that for a common
cathode seven-segment display, the output of decoder or segment
driver must be active high in order to glow the segment.

The figure below shows the truth table of a BCD to seven-segment

decoder with common cathode display. In the truth table , there
are 7 different output columns corresponding to each of the 7
segments.

Suppose the column for segment a shows the different combinations for which it is to be
illuminated. So ‘a’ is active for the digits 0, 2, 3, 5, 6, 7, 8 and 9.

From the above truth table, the Boolean

expressions of each output functions can
be written as

a = F1 (A, B, C, D) = ∑m (0, 2, 3, 5, 7,
8, 9)

b = F2 (A, B, C, D) = ∑m (0, 1, 2, 3, 4,
7, 8, 9)

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 Digital System Design (EC303PC)

c = F3 (A, B, C, D) = ∑m (0, 1, 3, 4, 5, 6, 7, 8, 9)

d = F4 (A, B, C, D) = ∑m (0, 2, 3, 5, 6, 8)

e = F5 (A, B, C, D) = ∑m (0, 2, 6, 8)

f = F6 (A, B, C, D) = ∑m (0, 4, 5, 6, 8, 9)

g = F7 (A, B, C, D) = ∑m (2, 3, 4, 5, 6, 8, 9)

Step 3: The third step involves constructing the Karnough’s map for each output term and then
simplifying them to obtain a logic combination of inputs for each output.

K-Map Simplification

The below figures shows the k-map simplification for the common cathode seven-segment
decoder in order to design the combinational circuit.

BAVUSAHEB.B.KUNCHANUR, Assistant Professor, Dept of ECE

 Digital System Design (EC303PC)

From the above simplification, we get the output values as

Step 4: The final step involves drawing a combinational logic circuit for each output signal.
Once the task was accomplished, a combinational logic circuit can be drawn using 4 inputs
(A,B,C,D)and a 7- segment display (a,b,c,d,e,f,g) as output.

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 Digital System Design (EC303PC)

FILL IN THE BLANKS

1) Code conversion circuits mostly uses__________

2) When both inputs are 1 output of xor is_____________
3) Simplified expression of full adder carry is__________
4) Two bit subtraction is done by__________
5) Dual of nand function is_________
6) Full adder performs addition on_______ bits
7) Adding 1001 and 0010 gives output of_________
8) Magnitude comparator compares using operation of______
9) A circuit that converts n inputs to 2^n outputs is called______
10) Encoders are made by three_________

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 Digital System Design (EC303PC)

Answers:

Q.No Answer

1 AND-OR gates

2 0

3 c=xy+xz+yz

4 half subtract or

5 nor function

6 three

7 1011

8 subtraction

9 decoder

10 OR Gates

MULTIPLE CHOICE QUESTIONS

1) The function of a multiplexer is(b)

a) to decode information
b) to select 1 out of N input data sources and to transmit it to single channel
c) to transmit data on N lines
d) to perform serial to parallel conversion
2) A combinational circuit is one in which the output depends on the(A)
a) input combination at the time
b) input combination and the previous output
c) input combination at that time and the previous input combination
d) present output and the previous output
3) A combinational logic circuit which generates a particular binary word or number is(a)
a) Decoder
b) Multiplexer
c) Encoder
d) Demultiplexer
4) Which of the following circuit can be used as parallel to serial converter ?(A)
a) Multiplexer

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 Digital System Design (EC303PC)

b) Demultiplexer
c) Decoder
d) Digital counter
5) In which of the following adder circuits, the carry look ripple delay is eliminated ?(c)
a) Half adder
b) Full adder
c) Parallel adder
d) Carry-look-ahead adder
6) Which of the following adders can add three or more numbers at a time (c)
a) Parallel adder
b) Carry-look-ahead adder
c) Carry-save-adder
d) Full adder
7) A device that converts from decimal to binary numbered is called (a)
a) Decoder
b) encoder
c) CPU
d) Convertor
8) A circuit that compares two numbers and determine their magnitude is called(d)
a) height comparator
b) size comparator
c) comparator
d) magnitude comparator
9) One that is not outcome of magnitude comparator is(b)
a) a>b
b) a-b
c) a<b
d) a=b

10) All comparisons made by comparator is done using(a)

a) 1circuit
b) 2 circuit
c) 3 circuit
d) 4 circuit

Answers:

Q.No 1 2 3 4 5 6 7 8 9 10
Answer b a A a c c a d b a

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 Digital System Design (EC303PC)

UNIT-III

TWO-MARK QUESTIONS:

1) Give the comparison between combinational circuits and sequential circuits.

Memory unit is not required Memory unity is required Parallel adder is a
combinational circuit Serial adder is a sequential circuit
2) What do you mean by present state?
The information stored in the memory elements at any given time defines the
present state of the sequential circuit.
3) What do you mean by next state?
The present state and the external inputs determine the outputs and the next state
of the sequential circuit.
4) What are the types of counter?
1. Synchronous counter 2. Asynchronous Counter
5) Draw the logic diagram for T Flip Flop

THREE-MARK QUESTIONS:

1. What is race around condition?

In the JK latch, the output is feedback to the input, and therefore change in the output
results change in the input. Due to this in the positive half of the clock pulse if J and K
are both high then output toggles continuously. This condition is known as race around
condition.

2. Define shift Registers

The binary information in a register can be moved from stage to stage within the
register or into or out of the register upon application of clock pulses. This type of bit
movement or shifting is essential for certain arithmetic and logic operations used in
microprocessors. This gives rise to a group of registers called shift registers.
3. What are the types of shift register?
1. Serial in serial out shift register
2 Serial in parallel out shift register
3. Parallel in serial out shift register
4.Parallel in parallel out shift register
5. Bidirectional shift register shift register.
4. Define flip-flop and list various types of flip-flops?
BAVUSAHEB.B.KUNCHANUR, Assistant Professor, Dept of ECE
 Digital System Design (EC303PC)

Flip - flop is a sequential device that normally. samples its inputs and changes its
outputs only at times determined by clocking signal.
1] S.R. latch 2] D latch 3] Clocked J.K. flip-flop 4] T flip-flop
5. Draw the timing diagram of 4-bit ring counter.

FIVE-MARK QUESTIONS:

1. Convert a JK Flip Flop to i) SR ii) T iii) D

Answer:
a) Conversion of JK flip flop to SR flip flop:
In case of converting JK flip flop into SR flip flop, external inputs (inputs of
combinational circuit) are S and R, while J and K are the inputs of actual flip flop.
So we have to get values of J and K in terms of S, R and Qn. thus we prepare a
conversion table S, R, Qn, Qn+1, J and K.
The external inputs S and R and the output Qn can make 8 combinations. For each
combination find the corresponding Qn+1.
In the SR flip flop, the combination S=1 and R=1 is not permitted. So, the corresponding
output is invalid and, therefore the corresponding J and K are don’t cares.
Complete the table by writing the values of J and K required getting each Qn+1 from the
corresponding Qn.
The conversion table, K-maps and Logic diagram for the conversion of JK flip flop to SR
flip flop is shown below:

BAVUSAHEB.B.KUNCHANUR, Assistant Professor, Dept of ECE

 Digital System Design (EC303PC)

Conversion Table

Logic Diagram

K-Maps

b) Conversion of JK flip flop to T flip flop:

For the conversion of JK flip flop to T type of flip flop, T will be the external input (input
of combinational circuit) and the output of this combinational circuit is connected to the
inputs of actual flip flop (J and K).
Then we prepare conversion table and using this table express J and K in terms of T and
Qn.
The conversion table, K-Maps and logic diagram for the conversion of JK flip flop to T
type of flip flop is shown below:

BAVUSAHEB.B.KUNCHANUR, Assistant Professor, Dept of ECE

 Digital System Design (EC303PC)

Conversion Table

Logic Diagram

K-Maps

c) Conversion of JK flip flop to D flip flop:

In case of converting JK flip flop into D flip flop, D is the external input of combinational
circuit, whereas J and K are the inputs of actual flip flop.
D and Qn make four combinations. So, prepare a conversion table and using this table
express J and K in terms of D and Qn.
The conversion table, K-map and logic diagram for the conversion of JK flip flop to D
flip flop is shown below:

BAVUSAHEB.B.KUNCHANUR, Assistant Professor, Dept of ECE

 Digital System Design (EC303PC)

Conversion Table

K-Maps

Logic Diagram
2. Design of a Synchronous Decade Counter Using JK FlipFlop?
Answer:
A synchronous decade counter will count from zero to nine and repeat the sequence.
The state diagram of this counter is shown

BAVUSAHEB.B.KUNCHANUR, Assistant Professor, Dept of ECE

 Digital System Design (EC303PC)

Since there are ten states, four JK flip-flops are required. The truth tables of present and next
state for the decade counter are shown in Fig. 9.10. Using the excitation table of JK flip-flop and
the outputs of J and K are filled.

The Karnaugh maps of the output J0, K0, J1, K1, J2, K2, J3, and K3 are shown. The simplified
results are at the bottom of the Karnaugh maps.

BAVUSAHEB.B.KUNCHANUR, Assistant Professor, Dept of ECE

 Digital System Design (EC303PC)

BAVUSAHEB.B.KUNCHANUR, Assistant Professor, Dept of ECE

 Digital System Design (EC303PC)

Based on the results obtained from the Karnaugh maps, the circuit design of synchronous decade
counter is shown

A synchronous decade counter designed using JK flip-flop

3. Explain the operation of 4-bit Ring counter?

Answer:
Ring counter is a sequential logic circuit that is constructed using shift register. Same
data recirculates in the counter depending on the clock pulse.
Ring counters are of two types
1)Ordinary Ring counters
2) Johnson counter
4 bit Ring Counter
The ring counter is a cascaded connection of flip flops, in which the output of last flip
flop is connected to input of first flip flop. In ring counter if the output of any stage is 1,
then its reminder is 0. The Ring counters transfers the same output throughout the circuit.

BAVUSAHEB.B.KUNCHANUR, Assistant Professor, Dept of ECE

 Digital System Design (EC303PC)

That means if the output of the first flip flop is 1, then this is transferred to its next stage
i.e. 2nd flip flop. By transferring the output to its next stage, the output of first flip flop
becomes 0. And this process continues for all the stages of a ring counter. If we use n flip
flops in the ring counter, the ‘1’ is circulated for every n clock cycles.
The circuit diagram of the ring counter is shown below.

Here we design the ring counter by using D flip flop. This is a Mod 4 ring counter which
has 4 D flip flops connected in series. The clock signal is applied to clock input of each
flip flop, simultaneously and the RESET pulse is applied to the CLR inputs of all the flip
flops.
Operation of Ring Counter
Initially, all the flip flops in ring counter are reset to 0 by applying CLEAR signal. Before
applying the clock pulse, we apply the PRESET pulse to the flip flops which assigns the
value ‘1’ to the ring counter circuit. For each clock signal, the data circulates among all
the 4 flip flop stages of ring counter.
This 4 staged ring counter is called Mod 4 ring counter or 4 bit ring counter. To circulate
the data correctly in the ring counter, we must load the counter with required values like
all 0’s or all 1’s.

Circulation of data in Ring counters

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 Digital System Design (EC303PC)

We know that the ring counter is similar to that of the shift registers connected in series.
The above diagram shown the four stages of flip flops as the parallel in serial our shift
registers, with data inputs D0, D1, D2 and D3.
The data circulation in ring counter is explained below. By passing the reset signal,
initially the flip flops are at RESET state. When the PRESET is applied to the ring
counter the input of the circuit becomes 1.
This input is connected to the first flip flop in the series, so that the flip flop QA is set to
1 and all other outputs of remaining flip flops will be low.
If we make the data input of the flip flop ‘A’ to low, this gives us the data pulse as 0 1 0.
Then for the second clock signal, the output of first flip flop will again change and then
the output of ‘B’ will become high. This means the data pulse 0 0 1 occurs.
In this way, as the clock signal and input of first flip flop changes, the output of the other
flip flops changes. As the output of last flip flop in series is connected to the input of the
first flip flop, the data sequence rotates or circulates in the ring counter.
Truth table of ring counter
The truth table of the 4 bit ring counter is explained below.

When CLEAR input CLR = 0, then all flip flops are set to 1. When CLEAR input CLR =
1, the ring counter starts its operation. For one clock signal, the counter starts its
operation. On next clock signal, the counter again resets to 0000. Ring counter has 4
sequences: 0001, 0010, 0100, 1000, 000.

Timing diagram of Ring Counter

BAVUSAHEB.B.KUNCHANUR, Assistant Professor, Dept of ECE

 Digital System Design (EC303PC)

The timing diagram of the Ring counter will explain that the clock signal changes the
output of every stage of the counter, so that CLK signal will help the data to circulate
from one flip flop to another. As the 4 bit ring counter (4 stages or 4 flip flops) circulates
the preset digit within one clock signal, the output frequency of each flip flop is ¼ th of
the main clock frequency.
State diagram of ring counter

The state diagram of the 4 bit ring counter is shown in above picture. It denotes that the
position of the preset digit (in this case preset digit is 1) is changing its position from
LSB to MSB, for one clock signal.
Advantages
Can be implemented using D and JK flip-flops. It is a self-decoding circuit.
Disadvantages
Only four of the 15 states are being utilized.

4. Differentiate combinational and sequential logic circuits?

Answer:
Combinational Logic Ciruits Sequential Logic Circuits

BAVUSAHEB.B.KUNCHANUR, Assistant Professor, Dept of ECE

 Digital System Design (EC303PC)

• The digital logic circuits whose • The digital logic circuits whose
outputs can be determined using the outputs can be determined using
logic function of current state input the logic function of current state
are combinational logic circuits, inputs and past state inputs are
hence, these are also called as time called as sequential logic circuits
independent logic circuits.

• Thus, these combinational digital • These sequential digital logic

logic circuits don’t have the circuits are capable to retain the
capability to store a state inside earlier state of the system based on
them. the current inputs and earlier state.

• Hence, the combinational logic • The sequential logic circuits

circuits do not contain any memory contain memory elements
elements.

• The combinational logic circuit’s • The sequential logic circuit’s

behavior can be defined by using the behavior can be defined by using
set of output functions. the set of output functions and set
of next state or memory functions.

• The combinational digital logic • The latch is considered as the

circuits are fundamentally simplest element used to retain the
implemented using different types of earlier memory or state in the
devices such as multiplexers, sequential digital logic.
demultiplexers, encoders, decoders,
half adder, and full adders.

5. Convert a SR Flip-Flop to i) JK ii) D

Answer:
(i) SR flip flop to JK flip flop:
Following figure shows the conversion table, K-maps, and Logic diagram for the
conversion of SR flip flop to JK flip flop.

BAVUSAHEB.B.KUNCHANUR, Assistant Professor, Dept of ECE

 Digital System Design (EC303PC)

Conversion Table

Logic Diagram
In this case we are required to convert SR flip flop into JK flip flop. Therefore we have to
first design and connect the combinational circuit to the input of SR flip flop so that it
will produce same outputs as that of JK flip flop. Here the external inputs are J and K. S
and R will be the outputs of designed combinational circuit which are inputs of actual flip

BAVUSAHEB.B.KUNCHANUR, Assistant Professor, Dept of ECE

 Digital System Design (EC303PC)

flop. We write a truth table with J, K, Qn, Qn+1, S and R. where Qn is the present state
of the flip flop and Qn+1 will be the next state obtained when the particular J and K
inputs are applied.
J, K and Qn can have eight combinations. For each combination of J, K and Qn find the
corresponding Qn+1, i.e. determine to which next state the JK flip flop will go from the
present state Qn if the present inputs J and K are applied. Now complete the table by
writing the values of S and R required to get each Qn+1 from the corresponding Qn. i.e.
write what values of S and R are required to change the state of the flip flop from Qn to
Qn+1.
(ii) SR flip flop to D flip flop:

Similarly for the conversion of SR flip flop into the D flip flop we have connect
combinational circuit to the inputs of the SR flip flop. In this case D the external input of
the circuit. The output of the combinational circuit is connected to the inputs of the actual
flip flop i.e. SR flip flop. Then the output of this flip flop will be the same as D flip flop.

The conversion table, K-maps, and Logic diagram for the conversion of SR flip flop to D
flip flop.

Conversion Table

BAVUSAHEB.B.KUNCHANUR, Assistant Professor, Dept of ECE

 Digital System Design (EC303PC)

K-Maps

Logic Diagram

MULTIPLE CHOICE QUESTIONS

1) A ripple counter's speed is limited by the propagation delay of
a) each flip-flop
b) all flip-flops and gates
c) the flip-flops only with gates
d) only circuit gates
2) To operate correctly, starting a ring counter requires
a) clearing all the flip-flops
b) presetting one flip-flop and clearing all the others
c) clearing one flip-flop and presetting all the others
d) presetting all the flip-flops

BAVUSAHEB.B.KUNCHANUR, Assistant Professor, Dept of ECE

 Digital System Design (EC303PC)

3) What type of register would shift a complete binary number in one bit at a time and shift
all the stored bits out one bit at a time?
a) PIPO
b) SISO
c) SIPO
d) PISO

4) A comparison between ring and johnson counters indicates that

a) a ring counter has fewer flip-flops but requires more decoding circuitry
b) a ring counter has an inverted feedback path
c) a johnson counter has more flip-flops but less decoding circuitry
d) a johnson counter has an inverted feedback path
5) Mod-6 and mod-12 counters are most commonly used in
a) frequency counters
b) multiplexed displays
c) digital clocks
d) power consumption meters
6) What is a shift register that will accept a parallel input and can shift data left or right
called
a) tri-state
b) end around
c) bidirectional universal
d) conversion
7) Which sequential circuits generate the feedback path due to the cross-coupled connection
from output of one gate to the input of another gate?
a) Synchronous
b) Asynchronous
c) Both
d) None of the above
8) The behaviour of synchronous sequential circuit can be predicted by defining the signals
at ______.
a) discrete instants of time
b) continuous instants of time
c) sampling instants of time
d) at any instant of time
9) How is a J-K flip-flop made to toggle
a) J = 0, K = 0
b) J = 1, K = 0
c) J = 0, K = 1
d) J = 1, K = 1

BAVUSAHEB.B.KUNCHANUR, Assistant Professor, Dept of ECE

 Digital System Design (EC303PC)

10) The ‘T’ in the flip flop stands for

a) Time
b) Transfer
c) Toggle
d) Trigger

Answers
Q.No 1 2 3 4 5 6 7 8 9 10

Answer a b b d c c b a d c

FILL IN THE BLANKS

1) The master slave JK flip-flop is an effectively combination of______________
2) When an inverter is placed between both inputs of SR flip-flop then resulting flip-flop
is______
3) The D in the Flip-flop stands for_________
4) The number of flip-flops required in decade counter_____
5) The circuit used to store one bit of data is called___________
6) Reduction of flip-flops in a sequential circuit is referred to as______
7) Latches are___________ triggered
8) Two states are said to be equal if they have exactly same________
9) State table can be represented in a_______
10) Next state of D flip-flop is dependent on_______

Answers:
Q.No Answer

1 SR Flip-flop and a T flip-flop

2 D Flip-flop

3 Data/Delay

4 3

5 Flip-flop

6 state reduction

7 level

8 output

BAVUSAHEB.B.KUNCHANUR, Assistant Professor, Dept of ECE

 Digital System Design (EC303PC)

9 state diagram

10 D state

UNIT-IV

TWO-MARK QUESTIONS:

1. Define sequential circuit?

In sequential circuits the output variables dependent not only on the present input
variables but they also depend up on the past history of these input variables.
2. What are the types of sequential circuits?
1. Synchronous sequential circuits 2. Asynchronous sequential circuits
3. What is state diagram?
The time sequence of inputs, outputs and flip-flop states may be enumerated in a state
table and the information available in a state table may be represented graphically called
a state diagram.

4. What is a state table?

For the design of sequential counters we have to relate present states and next states. The
table, which represents the relationship between present states and next states, is called
state table.

5. What is excitation table?

an excitation table shows the minimum inputs that are necessary to generate a particular
next state (in other words, to "excite" it to the next state) when the current state is known.

3- MARK QUESTIONS
1. Limitations of Finite State Machines?
➢ Number of states in the composed FSM grows dramatically (state explosion
problem)
➢ Composing FSMs of n subsystems, with k1 , k2 , k3,……..kn, states respectively,
results in a system whose FSM has k1 x k2 x …. x kn states - This growth is
exponential with the number of subsystems , not linear (i.e., k1 + k2 +… + kn ).
➢ Since at any time, a global state of the system must be defined and a single
transition must occur, FSM model is not suitable for describing asynchronous
concurrent activities in the system.

2. State the differences between Moore and mealy state machine.

BAVUSAHEB.B.KUNCHANUR, Assistant Professor, Dept of ECE

 Digital System Design (EC303PC)

1) Mealy Machines tend to have less state

a) Different outputs on arcs (n^2) rather than states (n).
2) Moore Machines are safer to use
a) Outputs change at clock edge (always one cycle later).
b) In Mealy machines, input change can cause output change as soon as logic is
done a big problem when two machines are interconnected asynchronous
feedback. 3) Mealy Machines react faster to inputs
b) React in same cycle – don't need to wait for clock.
c) In Moore machines, more logic may be necessary to decode state into outputs
– more gate delays after.
3. Compare combinational and sequential circuits?

Combinational Circuits Sequential Circuits

No Memory Memory

No flip-flops, Flip-flops may be used

Only combinational gates Combinational gates may be used

No feedback Feedback is allowed

Output for a given set of The order of input change

Inputs is independent of is quite important and may
order in which these inputs produce significant differences
were changed, after the in the output.
Output stabilizes.

4. Write short notes on FSM?

a finite state machine (FSM) is a device that can exist in one of a finite number
of states. Associated with an FSM is a memory that is used to store an identifier of the
state, so that the machine may process its input (if any) and move to the next state. Due
to this coincidence, finite state machines are often studied in conjunction with flip-flops.

We are all familiar with finite state machines, although we rarely think of them as
such. Consider a washing machine. The states for this machine are: off, fill with water,
wash, spin, and rinse. The control unit for the FSM is the knob on the washer that we
turn to start it.
A standard digital clock that displays only hour, minute, and second, can be said to have
24 · 60 · 60 = 86,400 states – still a finite number. Normally the FSM construct is used
to model systems with far fewer states; in our work we shall normally limit a FSM to
either eight or sixteen states; that is N £ 23 or N £ 24.

5. Explain the operation of modulo n counters?

BAVUSAHEB.B.KUNCHANUR, Assistant Professor, Dept of ECE

 Digital System Design (EC303PC)

A single flip-flop used gives two states output and is referred to as mod-2 counter. With
two flip-flops four output states can be counted in ascending or in descending way and is
referred to as mod-4 or mod-22 counter. With ‘n’ flip-flops a mod-2ncounting is possible
either of ascending or of descending type.

To design an asynchronous counter to count till M or mod-M counter where M is not a

power of 2, following procedure is used.
Find the number of flip-flops required n
= log2 M. calculated value is not an integer value if the M # 2n then select n by rounding
to the next integer value.
First writer the sequence of counting till M either in ascending or in descending way.
Tabulate the value to reset the flip-flops in a mod-M count.
Find the flip-flop outputs which are to reset from the tabulated value.
Tap the output from these flip-flops and feed it to an NAND gate whose output is
connected to the clear pin.

FIVE- MARK QUESTIONS

1. Explain the Design of the 11011 Sequence Detector

A sequence detector accepts as input a string of bits: either 0 or 1. Its output goes to 1 when
a target sequence has been detected. There are two basic types: overlap and non-overlap. In
a sequence detector that allows overlap, the final bits of one sequence can be the start of
another sequence.

Our example will be a 11011 sequence detector. It raises an output of 1 when the last 5
binary bits received are 11011. At this point, a detector with overlap will allow the last two
1 bits to serve at the first of a next sequence. By example we show the difference between
the two detectors. Suppose an input string 11011011011.

11011 detector with overlap X 11011011011

Z 00001001001
11011 detector with no overlap Z 00001000001
Problem: Design a 11011 sequence detector using JK flip-flops. Allow overlap.

Step 1 – Derive the State Diagram and State Table for the Problem
The method to be used for deriving the state diagram depends on the problem. I show the
method for a sequence detector. At this point in the problem, the states are usually labeled by a
letter, with the initial state being labeled “A”, etc.

Step 1a – Determine the Number of States

It can be proven that an N-bit sequence detector requires at least N states to function correctly. It
can also be shown that a circuit with more than N states is unnecessarily complicated and a waste
of hardware; thus, an N-bit sequence detector has N states.

BAVUSAHEB.B.KUNCHANUR, Assistant Professor, Dept of ECE

 Digital System Design (EC303PC)

We are designing a sequence detector for a 5-bit sequence, so we need 5 states. We label these
states A, B, C, D, and E. State A is the initial state.

Step 1b – Characterize Each State by What has been Input and What is Expected
State Has Awaiting
A -- 11011
B 1 1011
C 11 011
D 110 11
E 1101 1

Step 1c – Do the Transitions for the Expected Sequence

Here is a partial drawing of the state diagram. It has only the sequence expected. Note that the
diagram returns to state C after a successful detection; the final 11 are used again.

Note the labeling of the transitions: X /

Z. Thus the expected transition from A to
B has an input of 1 and an output of 0.

The transition from E to C has an output of

1 denoting that the desired sequence has
been detected.

Step 1d – Insert the Inputs That Break the Sequence

Each state has two lines out of it – one line

for a 1 and another line for a 0.

The notes below explain how to handle the

bits that break the sequence.

A State A is the initial state. It is waiting

on a 1. If it gets a 0, the machine remains
in state A and continues to remain there
while 0’s are input.
B If state B gets a 0, the last two bits input were “10”. This does not begin the
sequence, so the machine goes back to state A and waits on the next 1.
C If state C gets a 1, the last three bits input were “111”. It can use the last two

BAVUSAHEB.B.KUNCHANUR, Assistant Professor, Dept of ECE

 Digital System Design (EC303PC)

of these 1’s to be the first two 1’s of the sequence 11011, so the machine stays
in state C awaiting a 0. We might have something like 1111011, etc.
D If state D gets a 0, the last four bits input were 1100. These 4 bits are not part of
the sequence, so we start over.
E If state E gets a 0, the last five bits input were 11010. These five bits are not part of
the sequence, so start over.

More precisely we should be discussing prefixes and suffixes. At state C with input 111, the two
bit suffix to the sequence input is 11 which is a two bit prefix of the desired sequence, so we stay
at C. At E, getting a sequence 11010, we note that the 1-bit suffix is a 0, which is not a prefix of
the desired sequence, the 2-bit suffix is 10, also not a prefix, etc.

2. Explain the operation of serial binary adder?

G: state that the carry-in is 0
H: state that the carry-in is1

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 Digital System Design (EC303PC)

Y = ab + ay + by
s=a⊕b⊕c

Since in both states G and H, it is possible to generate two outputs depending on

the input, a Moore-type FSM will need more than two states • G0 and G1: carry is 0 sum
is 0 or 1 • H0 andH1: carry is 1 sum is 0 or 1

BAVUSAHEB.B.KUNCHANUR, Assistant Professor, Dept of ECE

 Digital System Design (EC303PC)

3. Explain the operation of parity bit generator using mealy model?

Parity generator can be of two types:

(i) Even Parity Generator
(ii) Odd Parity Generator

Consider input “I” is a stream of binary bits. When an input comes, the even parity
generator checks whether the total number of 1’s received till then are even or odd. If even
then the output becomes “0” [O = 0], otherwise output would be “1” [O = 1].
Let’s design the Mealy state machine for the Even Parity Generator.
Define 2 states
S0: Number of 1’s received till now is even
S1: Number of 1’s received till now is odd

Now let’s understand how we get the transitions and corresponding outputs:
Let’s say we are at the state S0: Even number of 1’s received yet

for input “0”: Since the present state represents that till now even number of 1’s are received, an
input “0” will keep the number of 1’s received as even. So, the next state would be S0 and the
output (parity bit generated) would be “0”.
for input “1”: An input “1” will make the number of 1’s received as odd. So, the next state would
be S1 and the output (parity bit generated) would be “1”.

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 Digital System Design (EC303PC)

Let’s say we are at the state S1: Odd number of 1’s received yet

for input “0”: Since the present state represents that till now odd number of 1’s are received, an
input “0” will keep the number of 1’s received as odd. So, the next state would be S1 and the
output (parity bit generated) would be “1”.
for input “1”: An input “1” will make the number of 1’s received as even. So, the next state
would be S0 and the output (parity bit generated) would be “0”

4. Design a MOD 11 synchronous counter using T flip flop.

A synchronous counter is one which has the same clock input for all its flip flops. A MOD 11
synchronous counter counts from 0000 to 1010. Hence it will require four T flip flops.
Synchronous counters are designed by using excitation table to determine the combinational
logic of inputs to each flip flop. The excitation table for all the four T flip flops is shown:

From the above excitation table, we can draw K-maps to determine input to every flip flop

BAVUSAHEB.B.KUNCHANUR, Assistant Professor, Dept of ECE

 Digital System Design (EC303PC)

Four equations for four T flip flops are obtained. Using them, the MOD 11 synchronous counter
is designed as follows:

5. Design mod-10 synchronous counter using JK Flip Flops. Check for the lock out
condition. If so, how the lock-out condition can be avoided? Draw the neat state
diagram and circuit diagram with Flip Flops.

BAVUSAHEB.B.KUNCHANUR, Assistant Professor, Dept of ECE

 Digital System Design (EC303PC)

1) Truth Table:

2) K-maps:

J0=1

K0=1

J1=Q0 Q3

BAVUSAHEB.B.KUNCHANUR, Assistant Professor, Dept of ECE

 Digital System Design (EC303PC)

K1=Q0

J2=Q0 Q1

K2=Q0 Q1

J3=Q0 Q1 Q2

K3=Q0

BAVUSAHEB.B.KUNCHANUR, Assistant Professor, Dept of ECE

 Digital System Design (EC303PC)

4) Logic Circuit:

5) Lock out condition:

• In the above counter the logic states 1010, 1011, 1100, 1101, 1110 and 1111 are not used.
If by chance, the counter happens to find itself in any one of the unused states, its next
state would not be known. It may just be possible that the counter might go from one
unused state to another and never arrive at a used state. A counter whose unused states
have this feature is said to suffer from LOCK OUT.
• To avoid lock out and make sure that at the starting point the counter is in its initial state
or it comes to its initial state within few clock cycles, external logic circuitry is to be
provided and so we design the counter assuming the next state to be the initial state, from
each unused states.

UNIT-V

TWO-MARK QUESTIONS:

1. Define linear wave shaping.

Ans: a linear network The process which by the wave form of a non-sinusoidal signal is altered
by transmitting the signal through is termed as linear wave shaping.
2. Define linear network.
Ans: A network comprising of linear elements is called linear network.
3. What are the linear elements and why they called as linear elements.
Ans: Resistor, capacitor and inductor are linear elements since the current passing through them
is proportional to the voltage i.e. there is linear relation between the applied voltage and resulting
current.

BAVUSAHEB.B.KUNCHANUR, Assistant Professor, Dept of ECE

 Digital System Design (EC303PC)

4. Define time constant of RC circuit.

Ans: Time constant of the RC circuit is the time required for the output voltage (voltage across
the capacitor) to attain 63.2% of the final steady value.
5. When the capacitor voltage becomes equal to the steady state value.
Ans: After 5-time constants, the capacitor voltage becomes equal to steady state value (99.3% of
V)

Three mark questions:

1. Compare Mealy and Moore machines.

Mealy Machine vs. Moore Machine
The following table highlights the points that differentiate a Mealy Machine from a Moore
Machine.
Mealy Machine Moore Machine

Output depends both upon the present state Output depends only upon the present state.
and the present input

Generally, it has fewer states than Moore Generally, it has more states than Mealy
Machine. Machine.

The value of the output function is a The value of the output function is a function
function of the transitions and the changes, of the current state and the changes at the
when the input logic on the present state is clock edges, whenever state changes occur.
done.

Mealy machines react faster to inputs. In Moore machines, more logic is required to
They generally react in the same clock decode the outputs resulting in more circuit
cycle. delays. They generally react one clock cycle
later.

2. What are the capabilities and limitations of finite state machines.

Capabilities of FSM:
Let a FSM have n states. Let a long sequence of input be given to the machine. The machine will
progress starting from its beginning state to the next states according to the state transitions.
However, after some time the input string may be longer than n, the number of states . As there
are only n states in the machine, it must come to a state it was previously been in and from this
phase if the input remains the same the machine will function in a periodical repeating fashion.

BAVUSAHEB.B.KUNCHANUR, Assistant Professor, Dept of ECE

 Digital System Design (EC303PC)

From here a conclusion that “for a n state machine the output will become periodic after a
number of clock pulses less than equal to n” can be drawn.
States are memory elements. As for a finite state machine the number of states is finite , so finite
number of memory elements are required to design a finite state machine.

See the diagram

Limitations of FSM:
(a) No finite state machine can be produced for an infinite sequence.
(b) No finite state machine can multiply two arbitrary large binary number.

3. State ‘state equivalence theorem’

Theorem for State Equivalence
Two states Si and Sj are k+1 equivalent if and only if
• They are k-equivalent
• And their next states for all inputs are k-equivalent
If we have a set of states which are k-equivalent, then a subset of these, which may include all of
them or none of them are only going to be k+1 equivalent. There can not be another state coming
in, which is not k-equivalent and that is k+1-equivalent.
So as we increase the “k”, set of distinguishable states grows and set of equivalent states reduces.

4. What is compatibility graph?

A graph is a pairwise compatibility graph if there are positive numbers min and max and there
is a weighted tree whose leaves correspond to the vertices of in such a way that two vertices are
adjacent in precisely when for their weighted distance in : min ≤ d ≤ max holds.
5. What is a closed covering?
Closed covers:
• {(AD) ( ,BE) ( ,CF)}
• {(AB), (CD), (EF)}
Closed covering is not unique
• Aim is to find a closed covering that with a minimum number of compatibles
• Set of all maximal compatibles: clearly g a closed covering – This defines an upper bound on
the number of states in the machine that covers the original one: » The upper bound is
meaningless when the number of maximal compatibles is larger than the number of states in the
original machine • For the example: the lower bound is 2 and upper bound 4 – Thus, a closed
covering with three compatibles defines a minimal machine 2

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 Digital System Design (EC303PC)

Five marks questions

1. Explain finite state machine
A model of computation consisting of a set of states, a start state, an input alphabet, and a
transition function that maps input symbols and current states to a next state. Computation begins
in the start state with an input string. It changes to new states depending on the transition
function. There are many variants, for instance, machines having actions (outputs) associated
with transitions (Mealy machine) or states (Moore machine), multiple start states, transitions
conditioned on no input symbol (a null) or more than one transition for a given symbol and state
(nondeterministic finite state machine), one or more states designated as accepting states
(recognizer), etc.

Definition 1 A finite state machine is a 5-tuple, (S, A,R, _, s0) where S is a finite set of states, A
is a finite alphabet, R is a finite alphabet of responses and _ is a transition function such that for
any state,s 2 S and symbol a 2 A, _(s, a) = (s0, r0) indicates the next state, s0 and the output
symbol, r0 2 R.
s0 is the initial state.
Definition 2 A recogniser is a special kind of finite state machine in which the output alphabet
contains two special symbols: accept and reject. The machine responds to any finite sequence of
input
symbols, terminated with a special end of input symbol (_), with either accept or reject.

2. Explain Mealy and Moore models.

Mealy and Moore models are the basic models of state machines. A state machine which uses
only Entry Actions, so that its output depends on the state, is called a Moore model. A state
machine which uses only Input Actions, so that the output depends on the state and also on
inputs, is called a Mealy model. The models selected will influence a design but there are no
general indications as to which model is better. Choice of a model depends on the application,
execution means (for instance, hardware systems are usually best realized as Moore models) and

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 Digital System Design (EC303PC)

personal preferences of a designer or programmer. In practice, mixed models are often used with
several action types. On an example we will show the consequences of using a specific model.
As the example we have taken a Microwave Oven control. The oven has a momentary-action
push button Run to start (apply the power) and a Timer that determines the cooking length.
Cooking can be interrupted at any time by opening the oven door. After closing the door the
cooking is continued. Cooking is terminated when the Timer elapses. When the door is open a
lamp inside the oven is switched on, when the door is closed the lamp is off. During cooking the
lamp is also switched on. The cooking period (timeout value) is set by a potentiometer which
supplies a voltage to the control system: the voltage is represented by a numeric value 0..4095
which is scaled by the Ni object to 1799. This arrangement allows the maximum cooking time to
equal 1799 seconds, i.e. 30 minutes. The solution should also take into account the possibility
that the push button Run could get blocked continuously in the active Position (which is easy to
demonstrate if testing the system in SWLab, which has only the two-positions buttons): in such a
case cooking must not start again until it is deactivated when the cooking is terminated
(otherwise our meal which we wanted to heat for instance for 5 minutes could be burned until we
discover that the button has got stuck in the active position). In other words, each cooking
requires intentional activation of the Run button.
The control system has the following inputs: Run momentary-action push button - when
activated starts cooking, Timer - while this runs keep on cooking, Door sensor - can be true (door
closed) or false (door open). And the following outputs: Power - can be true (power on) or false
(power off), Lamp - can be true (lamp on) or false (lamp off).
Moore model :Using Moore model we get a state machine whose state transition diagram is
shown in Figure 1.
This solution requires 7 states. Figure 2, Figure 3 and Figure 4 show state transition tables for
three of those states: Init, Cooking and CookingInterrupted. The state machine uses only Entry
actions.
Other states can be studied in the provided file MWaveOven_Moore.fsm.
While specifying that state machine the states dominate. We think in the following manner: if the
input condition changes the state machine changes its state (if a specific transition condition is
valid). Entering the new state, the state machine does some actions and waits for the reaction of
thecontrolled system. In a Moore model the entry actions define effectively the state. For
instance, we would think about the state Cooking: it is a state where the Timer runs and the state
machines waits for the Timer OVER signal.

BAVUSAHEB.B.KUNCHANUR, Assistant Professor, Dept of ECE

 Digital System Design (EC303PC)

Mealy model
The Mealy model is shown in Figure 5. It requires only 5 states. The states: Idle, Cooking and
Cooking Interrupted for that model (see Figure 6, Figure 7 and Figure 8) illustrate its features.
Other states can be studied in the provided file MWaveOven_Mealy.fsm. All activities are done
as Input actions, which means that actions essential for a state must be performed in all states
which have a transition to that state. The Timer must be now started in both states: Idle and
Cooking Interrupted.
This may be considered as a disadvantage: the functioning becomes a bit confusing.

Bits

1.The Programmable Array Logic consists of [ d]

a) fixed OR and AND gates b) Programmable OR , fixed AND gates
c) Programmable OR and AND gates d) Programmable AND , fixed OR gates

BAVUSAHEB.B.KUNCHANUR, Assistant Professor, Dept of ECE

 Digital System Design (EC303PC)

2. A ring counter is useful in generating————- . [c ]

a) Frequency scaling b ) Pseud or and on pattern generation
c) Timing signals d ) Refresh address of DRAM

3. An ASM chart can be [ a]

a) converted to a state diagram & table and implemented as a Flip-Flop
b) converted into a state table
c) converted into astate diagram
d) implemented using gates & flip – flops

4. Four RAM chips of 16×4 size have their busses connected together. This system will be of
size[c ]
a) 16×4 b) 256×1 c) 16×16 d) 32×8

5. The parameters of a threshold element are [ a]

a) weights assigned to input variable s and T b) output variables
c) weights assigned to input variables d) value of T

6. The table containing present state of output, next state of the output and the inputs is called[a ]
( a) Excitationtable ( b ) State table ( c ) Transition table e ( d ) Truth table

7. A finite state machine [a]

(a) same as clocked sequential circuits
(b) Neither Electrical motors nor clocked sequential circuits
(c) consists of electrical motors
(d) Electrical motors and clocked sequential circuits

8. The address bus with a ROM of size 1024*8 bits is [ b]

a)8 bits b) 10 bits c) 12 bits d) 16 bits

9. Which of the following flip flop is used as a latch – [b ]

a) JK flip flop b) D flip flop c)Master Slave flip d) T flip flop

10. Master slave configuration is used in flip flop to [c ]

a) Increase its clocking b) reduce power dissipation
c) Eliminate race around condition d) improve its reliability

11.The ROM programmed during manufacturing process itself is called [ a]

a)MROM (b) PROM (c) EPROM (d) EEPROM

BAVUSAHEB.B.KUNCHANUR, Assistant Professor, Dept of ECE

 Digital System Design (EC303PC)

12. A memory in which the contents get erased when power failure occurs is [ d]
a)EAROM (b) PROM (c) ROM (d) RAM

13. A single literal term in SOP expression [ b]

a)Requires an inverter for PLA implementation
b)Requires an AND gate for PLA implementation
c)Doesn’t requires an AND gate for PLA implementation
d) Doesn’t requires an inverter for PLA implementation

14. When an inverter is placed between the inputs of an S – R flip – flop, the resulting flip – flop
is a [ d]
a)J - K flip - flop (b) Master – slave flip - flop c)T flip - flop (d) D flip - flop

15. Flip – flops can be used to make [c ]

a)Latches (b) Bounce – elimination switches c) Registers (d) All of the above

16. The output of a clocked sequential circuit is independent of the input. The circuit can be
represented by [b ]
a)Mealy model (b) Moore model
c)Either Mealy or Moore model (d) Neither Mealy or Moore model

17. For designing a finite state machine k – maps can be used for minimizing the
[ d]
a)Excitation expressions of flip - flops (b) Number of flip – flops
c)Output logic expressions (d) Excitation and output logic expressions

18. While constructing a state diagram of sequential circuit from the set of given statements [b ]
a)A minimum number of states must only be used b)Redundant states may be used
c) Redundant states must be avoided d)None of the above

19. An ASM chart consists of [ d]

a)Only state boxes (b) only decision boxes c)Only decision and conditional output boxes (d) All
the above.

20. Moore type outputs are [a ]

a)Independent of the inputs b)Dependent only on the inputs
c)Dependent on present state and inputs d)Any one of the above

BAVUSAHEB.B.KUNCHANUR, Assistant Professor, Dept of ECE

 Digital System Design (EC303PC)

21. An n-stage ripple counter can count up to [b ]

(a) 2n (b) 2n-1 (c) n (d) 2n-1

22. A mod-13 counter must have [ c]

(a) 13 flip flops (b) 3 flip flops (c) 4 flip flops (d) synchronous clocking

23. In programmable logic array [ c]

(a) AND –array is fixed &OR- array is programmable
(b) AND-array is programmable & OR-array is fixed
(c) both AND &OR array are programmable
(d) both AND &OR array are fixed

24. Total no.of programmable fuses in ‘n’ input ‘m’ output PROM is [ c]
(a) n (b) nXm (c) 2nXm (d) 2mXn

25. A decision box in an ASM chart [ c]

(a) does not have exit paths (b) have only one exit path
(c) has two exit paths (d) has one entry and has one exit path

26. The functional difference between an SR flip-flop and J-K flip-flop is that [ c]
(a) J-K flip-flop is faster (b) J-K flip-flop has feedback
(c) J-K flip-flop accepts both inputs 1 (d) J-K flip-flop does not require clock

27. An Asynchronous counter differs from synchronous counter in [b ]

(a) Mod number (b) Method of clocking
(c) the type of flip-flops used (d) the numberof states in a sequence

28. To serially shift a byte of data in to shift register there must be [c ]

(a)1 clock pulse (b)one load pulse (c)eight clock pulses d)one clock pulse in each 1 in the data

29. Programming a PLD device means [b ]

(a) writing software program (b) blowing electronic fuses
(c) writing assembly language program (d) writing C program

30. When power supply of ROM is switched off, its contents [ c]

(a) becomes zero (b) becomes all ones (c) remains same (d) are unpredictable

Fill up the blanks

1.A PLA consists of AND, OR and invert / non invert matrix

BAVUSAHEB.B.KUNCHANUR, Assistant Professor, Dept of ECE

 Digital System Design (EC303PC)

2. A ROM has 32K×8 organization. Its capacity in bits is 256 Kbits

3. The number of outputs of a threshold element is 1

4. A shift register using flip flop is called Static shift register

5. The minimum number of flip flops required for a mod-12 ripple counter is 4

6. A Johnson counter is also called as inverse feedback amplifier

7. If the outputs of two states are different after P-state transitions they are said to be
P- Distinguishable

8. Unspecified outputs provide additional flexibility on state reduction.

9. The Programmable Array Logic consists of Programmable AND, fixed OR gates

10. The Moore type of output are represented inside the State box in an ASM chart

11.In a positive unite function all the variables are only in Un complemented form.

12. Non threshold functions cannot be realized using a single threshold gate.

13. Master – slave configuration is used in J-K flip – flops to eliminate Race around condition

14. A Basic ring counter requires no decoding circuitry.

15. The process of assigning the states of a physical device to the states of a sequential machine
is
known as State assignment

16. The merger table method of state reduction is also called pull unger method orimplication
chart method.

17. A table which consists of the states of a minimal state machine is called a minimal cover
table

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 Digital System Design (EC303PC)

18. The data processing path is commonly referred to as the data paths.

19. Moore type of outputs are referred to as unconditional outputs.

20. A path through an ASM block from entry to exit is referred to as a path
21. The sequential circuit is a combination of combinational circuit and memory elements.
22. The characteristic equation of J-K flip flop is JQI+KIQ
23. If the binary word 1101 is entered serially into the 4-bit serial in parallel out shift register
(initially clear), the Q outputs after two clock pulses are 0100
24. A combinational PLD with programmable AND array and programmable OR array is called
as PLA
25. Next state variables in asynchronous sequential circuits are called excitation variables.
26. A counter that triggers all the flip-flops together is called synchronous counter.
27. In synchronous circuit output depends only on the present state of flip-flop is called
Moore machine
28. The full form of PROM is programmable read only memory.
29. State diagram is a pictorial representation of behavior of a sequential circuit.
30. A Jhonson counter uses D flip flops.

BAVUSAHEB.B.KUNCHANUR, Assistant Professor, Dept of ECE