R22 B.Tech.

ECE Syllabus JNTU HYDERABAD

EC304PC: DIGITAL LOGIC DESIGN

B.Tech. II Year I Sem. L T P C
3 0 0 3
Course Objectives:
1. To understand common forms of number representation in logic circuits.
2. To learn basic techniques for the design of digital circuits and fundamental concepts used in
the design of digital systems.
3. To understand the concepts of combinational logic circuits and sequential circuits.
4. To understand the Realization of Logic Gates Using Diodes & Transistors.

Course Outcomes: Upon completing this course, the students will be able to
1. Acquire the knowledge on numerical information in different forms and Boolean Algebra
theorems.
2. Define Postulates of Boolean algebra and to minimize combinational functions, and design the
combinational circuits.
3. Design and analyse sequential circuits for various cyclic functions.
4. Characterize logic families and analyze them for the purpose of AC and DC parameters.

Course PO1 PO2 PO3 PO4 PO5 PO6 PO7 PO8 PO9 PO10 PO11 PO12
CO1 3 2 3 1 2 1 - - - - - 2
CO2 3 2 2 1 2 1 - - - - - 2
CO3 2 3 3 2 2 1 - - - - - 1
CO4 3 2 1 1 1 - - - - - - -

UNIT - I
Number Systems: Number systems, Complements of Numbers, Codes- Weighted and Non-weighted
codes and its Properties, Parity check code and Hamming code.
Boolean algebra: Basic Theorems and Properties, Switching Functions- Canonical and Standard
Form, Algebraic Simplification, Digital Logic Gates, EX-OR gates, Universal Gates, Multilevel
NAND/NOR realizations.

UNIT - II
Minimization of Boolean functions: Karnaugh Map Method - Up to five Variables, Don’t Care Map
Entries, Tabular Method
Realization of Logic Gates Using Diodes & Transistors: AND, OR and NOT Gates using Diodes
and Transistors, DCTL, RTL, DTL, TTL, CML and CMOS Logic Families and its Comparison, standard
TTL NAND Gate-Analysis & characteristics, TTL open collector O/Ps, Tristate TTL, MOS & CMOS open
drain and tri-state outputs,IC interfacing- TTL driving CMOS & CMOS driving TTL.

UNIT – III
Combinational Logic Circuits: Adders, Subtractors, Comparators, Multiplexers, Demultiplexers,
Encoders, Decoders and Code converters, Hazards and Hazard Free Relations.
Sequential Circuits Fundamentals: Basic Architectural Distinctions between Combinational and
Sequential circuits, SR Latch, Flip Flops: SR, JK, JK Master Slave, D and T Type Flip Flops, Excitation
Table of all Flip Flops, Timing and Triggering Consideration, Conversion from one type of Flip-Flop to
another.

UNIT - IV
Registers and Counters: Shift Registers – Left, Right and Bidirectional Shift Registers, Applications
of Shift Registers - Design and Operation of Ring and Twisted Ring Counter, Operation of
Asynchronous and Synchronous Counters.

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R22 B.Tech. ECE Syllabus JNTU HYDERABAD

Sequential Machines: Finite State Machines, Synthesis of Synchronous Sequential Circuits- Serial
Binary Adder, Sequence Detector, Parity-bit Generator, Synchronous Modulo N –Counters.

UNIT – V
Finite state machine: capabilities and limitations, Mealy and Moore models, State equivalence and
machine minimization, simplification of incompletely specified machines, Merger graphs. Asynchronous
design-modes of operation, Hazards, synthesis of SIC fundamental mode circuits, synthesis of burst
mode circuits. Introduction to ASM Charts

TEXT BOOKS
1. Zvi Kohavi &Niraj K. Jha, - Switching and Finite Automata Theory, 3rd Ed., Cambridge, 2010.
2. R. P. Jain - Modern Digital Electronics, 3rd Edition, 2007- Tata McGraw-Hill

REFERENCE BOOKS
1. Morris Mano, Fredriac J. Hill, Gerald R. Peterson - Introduction to Switching Theory and Logic
Design –3rd Ed., John Wiley & Sons Inc.
2. Charles H. Roth - Fundamentals of Logic Design, 5th ED., Cengage Learning, 2004.

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R22 B.Tech. ECE Syllabus JNTU HYDERABAD

EC307PC: DIGITAL LOGIC DESIGN LABORATORY

B.Tech. II Year I Sem. L T P C

0 0 2 1
Course Outcomes: Upon completing this course, the students will be able to
1. Acquire the knowledge on numerical information in different forms and Boolean Algebra
theorems.
2. Define Postulates of Boolean algebra and to minimize combinational functions, and design
the combinational circuits.
3. Design and analyze sequential circuits for various cyclic functions.
4. Characterize logic families and analyze them for the purpose of AC and DC parameters.

Course PO1 PO2 PO3 PO4 PO5 PO6 PO7 PO8 PO9 PO10 PO11 PO12
CO1 3 2 3 1 2 1 - - 1 - - 2
CO2 3 2 2 1 2 1 - - 1 - - 2
CO3 2 3 3 2 2 1 - - 1 - - 1
CO4 3 2 1 1 1 - - - - - - -

List of Experiments
1. Realization of Logic circuit to generate r’s Compliment using Logic Gates.
2. Realization of given Boolean function using universal gates and minimizing the same.Compare the
gate count before and after minimization.
3. Design and realize Full Adder circuit using gates/universal gates. Implement Full Subtractor using
full adder.
4. Designing a 2 – bit Comparator using AND, OR and NOT gates. Realize 4 – bit Comparator using 2
– bit Comparators.
5. Realize 2:1 MUX using the given gates and Design 8:1 using 2:1 MUX.
6. Implement the given Boolean function using the given MUX(ex: code converters).
7. Realize a 2x4 Decoder using logic gates and implement 3x8 Decoder using 2x4 Decoder.
8. Implement the given Boolean function using given Decoders.
9. Convert Demultiplexer to Decoder and vise versa.
10. Verification of truth tables of flipflops using different clocks (level triggering, positive and negative
edge triggering) also converts the given flipflop from one type to other.
11. Designing of Universal n-bit shift register using flipflops and Multiplexers. Draw the timing diagram
of the Shift Register.
12. Design a Synchronous binary counter using D-flipflop/given flipflop.
13. Design a asynchronous counter for the given sequence using given flipflops.
14. Designing of MOD 8 Counter using JK flipflops.
15. Designing of sequence detecting State Machine with minimal states using the given flipflops.
16. Designing of Parity Bit(even/odd) generator using the given flipflops.
17. Realize all logic gates with TTL logic.
18. Realize all logic gates with DTL logic.
*Design a sequence detector to detect a given sequence and verify practically
*Design a serial subtractor for 4 bit binary numbers

Major Equipment required for Laboratories:

1. 5 V Fixed Regulated Power Supply/ 0-5V or more Regulated Power Supply.
2. 20 MHz Oscilloscope with Dual Channel.
3. Bread board and components/ Trainer Kit.
4. Multimeter.

Page 48 of 138