VLSI DESIGN-21EC63

MODULE : 4

FAULTS IN DIGITAL CIRCUITS &

TEST GENERATION FOR COMBINATIONAL LOGIC CIRCUITS:

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Topics Covered from Text 3

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Section: 1.1 to 1.3 and

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2.1 to 2.3

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PREPARED BY
PRADEEPKUMAR S K
ASSISTANT PROFESSOR, DEPARTMENT OF ECE
K I T , TIPTUR 572201
 WHY TESTING
To determine the presence of fault(s), not the absence of fault(s), in a given Circuit.
• The amount of testing can guarantee that a circuit chip, board or system is fault-free.
• To carry out testing to increase our confidence in proper working of the circuit.
Verification is an alternative to testing, used to verify the correctness of a Design.
• Simulation based approach
• Formal methods

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Tests fall into three main categories

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The first set of tests verifies that the chip performs its intended function. These tests, called functionality tests or

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logic verification, are run before tape out to verify the functionality of the circuit.
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The second set of tests are run on the first batch of chips that return from fabrication. These tests confirm that

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the chip operates as it was intended and help debug any discrepancies.
For example, a new microprocessor can be placed in a prototype motherboard to try to boot the operating
system.
• The third set of tests verify that every transistor, gate, and storage element in the chip functions correctly. These
tests are conducted on each manufactured chip before shipping to the customer to verify that the silicon is
completely intact. These are called manufacturing tests
• Testing a die (chip) can occur at the following levels:
Wafer level, Packaged chip level, Board level, System level, Field level
Testing During VLSI Development
• Design verification targets design errors Role of Testing:
• Corrections made prior to • If you design a product, fabricate, test it and it fails the test,
fabrication then there must be a cause for the Failure.
• Remaining tests target manufacturing • Test was wrong
• The fabrication process was faulty
defects
• The design was incorrect
• A defect is a flaw or physical
• The specification problem
imperfection that can lead to a fault
• The Role of testing is to detect whether something went

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wrong and the role of diagnosis is to determine exactly what

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went wrong

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• Correctness and effectiveness of testing is most important

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Testing

Verification
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 FAILURES AND FAULTS
Failure: A failure is said to have occurred in a circuit if it deviates from its specified behaviour.
Defect: A defect is the unintended difference between the implemented hardware and its intended
design. Defect occur either during manufacture or during the use of devices.
Error: A wrong output signal produced by a defective system is called an error. An error is an “effect”
whose cause is some “defect.”
Fault: A Fault is a physical defect that may or may not cause a failure. It is characterised by its nature,

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value, extent and duration.

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• A logical fault causes the logic value at a point in a circuit to become opposite to the specified
value.
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• Non logical faults include the rest of the faults, such as the malfunction of clock signal, power
failure and so forth.

Defects occur either during manufacture or during the use of devices. Repeated occurrence of the
same defect indicates the need for improvements in the manufacturing process or the design of
the device. Procedures for diagnosing defects and finding their causes are known as failure mode
analyses (FMA).
 THE PROBLEM IN FAULT ENUMERATION FAULT COVERAGE

• The number of possible physical defects can be too huge. Fault coverage : Percentage of the total
• Not possible to enumerate number of logical faults that can be tested
• So how do we judge the quality of a test? using a Given test set T. It is often
• Solution: abstract physical defects and define some logical expressed in percentage.
fault models.
𝑵𝒖𝒎𝒃𝒆𝒓 𝒐𝒇 𝒅𝒆𝒕𝒆𝒄𝒕𝒆𝒅 𝑭𝒂𝒖𝒍𝒕𝒔
• Easy to analyse and quantify 𝑭𝑪 =
𝑻𝒐𝒕𝒂𝒍 𝒏𝒖𝒎𝒃𝒆𝒓 𝒐𝒇 𝑭𝒂𝒖𝒍𝒕𝒔
• Possible to judge the quality of a set of test vectors
• How many faults are getting tested?

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VARIOUS PROCESS DURING TESTING

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• Fault Modelling:
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• Abstract the physical defects and define a suitable logical fault model
• Limits / simplifies the scope of test generation
• Test Generation
• Given a circuit and a set of faults F, determine a set of test vectors T that detects all faults F.
• Fault simulation
• Given a circuit, a set of faults F and set of test vectors T, determine the faults F that are tested by the vectors in T
 WHAT IS FAULT MODELING?
A fault model is a simplified representation of the possible defects or faults that may occur in a digital circuit. Fault
models are used to analyze the behavior of digital circuits under various fault conditions and to develop testing
strategies to detect and diagnose these faults.
WHY FAULT MODEL?
The number of physical defects in a chip can be too many. A modern VLSI chip can contain millions of transistors. It
is very challenging (next to impossible) to count and analyze all possible faults. Hence, we abstract physical defects and
define some logical fault models.
Advantages of fault models:

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•Drastically reduces the number of faults to be considered. 1. Stuck-at Faults

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2. Bridging Faults

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•Makes test generation and fault simulation possible.

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3. Transistor stuck-on/Open Faults
•We can evaluate fault coverage and compare test sets.

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4. Delay Faults
5. Temporary faults.
LEVELS OF ABSTRACTION
 System/Behaviour Level Gate/Structural Level
• Circuit is specified as netlist, typically at gates and flipflops.
• Circuit specification in High level HDL like Verilog or • The Assumption:
VHDL. • The Blocks (eg. Gates) are fault free.
• Faults defined w.r.t constructs of HDL
• The interconnections b/w blocks can be faulty.
• A variable is permanently in “0” or “1”. • Idea is to ensure that interconnections are fault free, and are
• An Assign x=y doesn’t work. able to carry both logic 0 and logic 1 signals.
• For controlled loop, either loop is “always” executed or • Popular structural level models are
“never” executed. • Stuck-at Fault
• Not Very accurate but used due to lower complexity. • Bridging Fault

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RTL/Functional Level

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Switch/Transistor Level

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• Circuit specification at Register Transfer Level (RTL)

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• Netlist of functional blocks like Registers, adders, mux etc.. Circuit specified at the transistor level.

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• Fault models are block specific and not general. • Ex. A netlist of CMOS gates.

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• Ex. Mux, Decoder, Memory etc.. • MOSFETs considered as ideal switches in this model.
• Test generated with very less effort. • Two Types switch level models are common.
• We take 4:1 Multiplexer. • Stuck-open Fault: A transistor never turns ON
• 4 inputs ,2 controls, one output. Test can be generated • Stuck-short Fault: A Transistor always ON
directly from functional behaviour of MUX
Physical/Layout Level
• Circuit specified at the Layout level. • This Fault model is somewhat Adhoc, • Some Models rely on geometric information
• As a collection of Rectangular can be derived directly from layout. • PLA Fault model, Memory Fault
shapes on different layers. • Ex. Bridging b/w pair of lines model etc..
running in parallel.
STUCK-AT-FAULTS
The most fundamental and widely used fault model is the stuck-at fault. This model assumes a single fault in a circuit
that forces a particular net (wire) to be stuck at either a logic 0 or a logic 1, regardless of the intended signal. Imagine a
broken wire stuck in the ground (logic 0) or a faulty transistor permanently turned on (stuck-at-1). Stuck-at faults can be
further categorized as:

• Stuck-at-0 (SA0): The net is permanently stuck at logic 0.

• Stuck-at-1 (SA1): The net is permanently stuck at logic 1.

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Stuck-at faults are popular because they are relatively simple to model and test for. By applying specific test vectors

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(combinations of input signals) engineers can isolate stuck-at faults and identify faulty circuits.

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A fault in a logic gate results in one of its inputs or output being fixed to either a logic 0
(Stuck-at-0 / s-a-0) or a logic 1 (Stuck-at-1 / s-a-1).

Example of NAND with ‘A’ input @ s-a-1:

• NAND gate perceives the input A as a ‘1’ irrespective of the logic value placed on the input.
Output is ‘0’ for input shown in figure.
• Since the output is wrong for this applied input it’s a “Faulty output". "Fault free output” is logic ‘1’.
• Therefore Pattern shown can be used to test for the A input s-a-1, because there is a difference
between the output of the Fault free and faulty gate.
 SINGLE STUCK-AT FAULTS MULTIPLE STUCK-AT FAULTS
• A stuck-at fault is assumed to affect only the • Any number of circuit lines can have
interconnection between gates. Each stuck-at faults at any given time.
connecting line can have two types of faults:
stuck-at-1 and stuck-at-0 (commonly written as • For a circuit with “K” line, total number
of multiple stuck-at faults is 𝟑𝒌 − 𝟏.
s-a-1 and s-a-0.)
• This is because each line can be in one
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Only one line of the circuit has a stuck-at fault of the three states: s-a-1, s-a-0, or fault-

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at any given time.

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free.

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Most widely used fault model in the industry. • All combinations except one having all

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lines in fault-free states are counted as
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For a circuit with “K” lines, total number of faults
single stuck-at faults is “2K”
SINGLE STUCK-AT FAULTS TESTING EXAMPLE

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 BRIDGING FAULTS
• A bridging fault is said to have occurred when two or more
signal lines in a circuit are accidentally connected together. It is
quite possible due to imperfection during layout fabrication.
• If an element is short to power (VDD) or ground (VSS), it is
equivalent to the stuck-at fault model that we just studied.
• Bridging faults at the gate level have been classified into two

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types: input bridging and feedback bridging.
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An input bridging fault corresponds to the shorting of a

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certain number of primary input lines. A feedback bridging

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fault results if there is a short between an output and an
input line.
• A feedback bridging fault may cause a circuit to oscillate,
or it may convert it into a sequential circuit.
• Bridging faults in a transistor-level circuit may occur between
the terminals of a transistor or between two or more signal lines.
These can be further classified into two types: wired-AND
bridging and wired-OR bridging.
 BELOW IS A SIMPLE GATE-LEVEL REPRESENTATION OF 2:1 MULTIPLEXER
Non-Faulty Faulty

Y= ??

How will the output Y change? Well, this can be modeled by bridging faults, as discussed, there are two different ways to model

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this. These modeling techniques depend on the technology (e.g., TTL, CMOS) in which the logic is implemented.

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Faulty “AND” Bridging Faulty “OR” Bridging

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𝐴𝐶 𝐴𝐶

C K ҧ C
𝐴+

C C

ҧ
Y=𝐶+B ҧ
Y=𝐶𝐴+B

Note that Y (faulty) can be different for both these models.

BREAKS & TRANSISTOR LEVEL STUCK-ON STUCK-OFF FAULTS
Breaks caused by either missing conducting material or extra
insulating material. Two types
(i) Intragate Breaks : Occurs Internal to gate; Disconnect
source,drain or gate from transistor defined by b1,b2,b3 in figure
(ii) Signal Line breaks: occurs at the signal lines and can force the
gates of transistors in static CMOS to Float.

Switch/Transistor Level Fault Model

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Here, the circuit is specified at the transistor level. For example, a netlist of CMOS gates. MOS
transistors are considered as ideal switches in this model. Two types of switch level fault models are

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common:
•Stuck-Open Fault
•Stuck-Short Fault

Stuck-Open Fault Model

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In this fault type, a transistor becomes permanently non-conducting due to some defect.
The gate output may depend on its previous state. We can say that the circuit exhibits
sequential behavior. It would typically require two test vectors that are to be applied in
sequence.
 EXAMPLE: 2-INPUT NOR GATE IN CMOS.
• MOS M1 is stuck open which means Vdd is
disconnected from the CMOS logic.
• Due to the fault, no current flow is allowed in pull-
up logic. Hence, we must apply a test vector that
must result in the flow of current in pull-up logic (in
the non-faulty circuit).
• The only test vector possible is AB = 00. This input

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makes both M1 and M2 conducting, and Vdd is

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connected to the output.

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• If Fault free F= ‘1’ ;
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If Faulty F= ‘Floating’ or high impedance. But since

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it is defective, it will not be connected to Vdd.
• It may show logic-0 or logic-1, depending upon its
previous value. Our simple combinational logic is
now showing dynamic sequential behavior.

• To counter this problem, we additionally apply an initial test vector AB = 10 to first

discharge the load into a known state logic-0. So, we need to apply a pair of vectors in
a particular sequence. In this case, the test pattern is AB = {10, 00}. This experiment
is also known as the Two-pattern test.
Stuck-Short Fault Model
Here a transistor is permanently conducting (i.e., source-drain shorted) in the presence of a fault.
In this case, checking the logic value at the output may not be sufficient. Both pull-up (pMOS) and
pull-down (nMOS) networks may become conducting. This condition behaves like a voltage divider
(depending on ON-resistance of pull-up and pull-down network), thereby causing the output to reach
some indeterminate level.

• Due to this, high current will be flowing from Vdd to

GND. It will eventually increase the static power

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dissipation.

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• Ideally, CMOS logic considerably consumes zero static
power. Hence, we can detect this type of fault by

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measuring static power dissipation.
• Test vector will be such that it causes a conducting

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path from Vdd to GND in the presence of a fault.

We apply test vector AB = 10. In a non-faulty circuit,

this should turn off the pull-up logic. But the fault will
cause the pull-up logic to turn on, resulting in a heavy
static current.
DELAY FAULTS
A defect in the manufacturing process causes a signal to propagate through the
circuit slower than expected. This delay can lead to malfunctions if the delayed
signal arrives at a subsequent stage after a critical timing window has closed. Delay
faults are particularly tricky because they may only manifest under specific
operating conditions, making them more difficult to detect.

Logic level models of excessive propagation delay

„ Path delay fault
„ Gate delay fault

TEMPORARY FAULTS
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A major portion of digital system malfunctions are caused by temporary faults. Two

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types:

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• Transient Faults:
• Non recurring temporary faults.
• Caused by power malfunction or particle radiation.
• Not repairable
• Intermittent Faults:
• Recurring faults that appear on regular basis.
• Occur due to loose connections, partially defective components or poor
designs.
• Also may occur due to environment conditions like temperature, humidity,
vibration etc.
 TEST GENERATION FOR COMBINATIONAL LOGIC
Fault Diagnosis of Digital Circuits:
• Fault Diagnosis includes both fault detection and fault location.
• Fault Detection means the discovery of something wrong in a digital system or circuit.
• Fault Location means the identification of the faults with components, functional modules, or
subsystems, depending on the requirements.

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Fault Detection

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• It is carried out by applying a sequence of test inputs and observing the resulting outputs.

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Test sequence are to be kept minimal since simulation time increases exponentially for all set of

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•
inputs.
• Apply only minimum set of test vectors which can detect maximum number of faults.
• A FAULT SIMULATION evaluates how a digital circuit will behave in the presence of
manufacturing defects.
• FAULT COVERAGE (Fc) is the ratio between the number of faults(F) that can be uncovered and the
number of faults that could exist (X). Fc=F/X.
 PATH SENSITIZATION METHOD
• The basic principle of the path sensitization method is to choose some path from the origin of
the fault to the circuit output.
• A path is sensitized if inputs to the gates along the path are assigned values such that the effect
of the fault can be propagated to the output.
• Sensitization is a part of the test generation process in which appropriate stimulus is applied at
the primary inputs so that the effect of the fault is observable at the primary outputs.

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To illustrate, let us consider the s-a-1 faulty
condition of the circuit. In the example, the effect

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of the stuck-at-1 fault can only be observed at

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output ‘Z’ if input ‘a’ is set logic-0. If ‘a’ is set

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to logic-1, there will be no difference in
a faulty and good circuit; hence the effect of the
fault will be masked. The path sensitization method
is done in three steps:
1.Fault excitation/activation
2.Forward propagation or sensitization
3.Backward propagation or justification
 Fault excitation
• Create a discrepancy at the wire
‘X.’ This is done by forcing the net
by an opposite value signal to which
it is stuck-at.
• Since ‘X’ is stuck-at-1, we need to
force logic-0 to this net, which
simply translates to setting ‘a’ as
logic-0.
• This process is also known as fault

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excitation or activation.

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Note that the net will still be stuck-

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at-1, but it will not match with our

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output ‘Z’ corresponding to logic-0
value at ‘a,’ as the circuit will
operate thinking that the net ‘X’ is
assigned logic-1.
After the fault is excited, we assign the net to a variable ‘D’ (stands for discrepancy).
This is just an annotation to simplify the next steps. The effect of this discrepancy may
or may not be observable at the output, as the other inputs (b and c) may mask the
fault in later stages. We don’t want that. So, our next step is to propagate ‘D’ to the
primary output.
 Forward Propagation

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1. In fault propagation, we observe the input 3. In the first step, to pass ‘D’ through

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of each forthcoming gate in the path of ‘D’ the AND-gate, the other input ‘c’ must
and assign desired values to the other be set to logic-1.
secondary inputs, which will propagate 4. If it is made logic-0, the output of AND
discrepancy to the primary output. gate will always be logic-0 and
2. The orange line is the forward path for independent of ‘D.’ Hence, the input is
‘D.’ Since this is a 2-level combinational ‘c’ is set to logic-1.
circuit, we need to do propagation two 5. Similarly, in the second step, the OR
times. This process is also known gate requires all the inputs to be set
as forward propagation or sensitization. zero.
 Backward Propagation

• Now, the path has been

sensitized successfully.
• But we still didn’t get the test
pattern as the value of ‘b’ is
unknown.
• To find the value of ‘b,’ we
just need to traverse behind
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every gate and assign the

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desired value to the net until

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we reach the primary inputs.
• This process is shown in
green lines. This is known
as backward
propagation or justification.
• We can now read the test
vector obtained at primary
inputs i.e. (a, b, c) = (0, 0, 1).
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Advantages:
• Test for a primary input is also a test for all the sensitized path.
Disadvantages:
• Fan out and reconvergence may cause conflicts during back trace.
• Reconverge fanouts with unequal inversion parity is a problem, which may

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require sensitization of more than one paths simultaneously
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• To detect a fault Several sophisticated extensions exist that are used in practice

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(D-Algorithm, PODEM,FAN and extensions)

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 BOOLEAN DIFFERENCE METHOD
• Basic Principle is to derive two Boolean expression
• One which represent FAULT FREE behaviour.
• Another represents FAULTS (s-a-1 or s-a-1)
• Two expressions are “OR”ed , If Result =‘1’ fault is
indicated.

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Shannon’s Expansion Theorem to characterize Boolean circuits
An arbitrary Boolean function
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can be expanded about any variable say, as

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For Solving problems lets stick to below notations
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•
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In this method, an equation describes the set of tests for a given fault.
The equation is usually quite complex, and a large part of the work involves reducing the
equation to a manageable size.
• Given a function 𝑭 that describes the behavior of a digital circuit, if a fault occurs that
∗
transforms the circuit into another circuit whose behavior is expressed by 𝑭 , then the 1-
points of the function 𝑻,

ഥ 𝑭∗ + 𝑭 𝑭∗
𝑻 = 𝑭 ⊕ 𝑭∗ = 𝑭
 Example A - Dealing with faulty primary input
Using Boolean Difference, create a test for the circuit shown below with a fault Y is S-A-0

❑Output of fault-free circuit, f, is given by

𝒇 = 𝒙. 𝒚 + 𝒚ഥ. 𝒛
❑Output of the faulted circuit (y SA0. i.e. put y =
0) is given as 𝒈 = 𝒙. 𝒚 + 𝒚
ഥ. 𝒛 = 𝒛

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❑Next, we compute T as

e 𝑦e
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ത + 𝒇ഥ
𝑻 = 𝒇⨁𝒈 = 𝒇𝒈
➔: 𝑇 =d𝑥.
𝒈, where T = Test

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ത 𝑧 𝑧 + 𝑥. 𝑦 + 𝑦.
ത 𝑧 𝑧ҧ

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➔:𝑇
= 𝑥. 𝑦 𝑦.
ത 𝑧 𝑧 + 𝑥. 𝑦. 𝑧ҧ
= 𝑥ҧ + 𝑦ത 𝑦ധ + 𝑧ҧ 𝑧 + 𝑥. 𝑦. 𝑧ҧ
❑But T must be a 1 for the required test vectors ➔:𝑇 = 𝑥ҧ + 𝑦ത 𝑦 + 𝑧ҧ 𝑧 + 𝑥. 𝑦. 𝑧ҧ
distinguishing between the two circuits: ➔ ➔:𝑇 = 𝑥ҧ + 𝑦ത 𝑦𝑧 + 𝑥. 𝑦. 𝑧ҧ
𝑇 = 𝑥𝑦𝑧
ҧ + 𝑥𝑦𝑧ҧ = 1 ➔:𝑇 = 𝑥𝑦𝑧
ҧ + 𝑥𝑦𝑧ҧ
Thus a test has been successfully created to test the circuit at SA0 at node y. Meaning that
applying the test vectors identified, (011 and 110).
We Use Several Properties to minimize reduction steps described in next slide
 PROPERTIES

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Now,

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