VLSI DESIGN-21EC63

MODULE : 3

SEMICONDUCTOR S K
d e e p
MEMORIES
T:P r a
KI

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Topics Covered from Text 2
Section: 10.1 to 10.6

PREPARED BY
PRADEEPKUMAR S K
ASSISTANT PROFESSOR, DEPARTMENT OF ECE
K I T , TIPTUR 572201
 e p S K
r a d e
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 e p S K
r a d e
: P
(a) DRAM

KI T

. (b) SRAM
 (c) Mask ROM

e p S K
r a d e
KI T : P (d) EPROM

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(e) FRAM
 • To access a particular cell (data
bit) respective Bitline and
Wordline must be activated.
• This is accomplished by row and

K
column decoders.

p S
• Row Decoder selects one of

e e
𝟐𝑵 wordlines with N bit row

r a d
address.

T : P
• Column Decoder selects one of

KI
𝟐𝑴 wordlines with M bit column
address.

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Once a memory cell or a group of memory cells are selected in this fashion, a
data read and/or a data write operation may be performed on the selected
single bit or multiple bits on a particular row.
Thus, the array organization examined here is called a Random Access Memory
(RAM) structure.
DYNAMIC RANDOM ACCESS MEMORY

e p S K
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Typical configuration of DRAM chip
(1.6Gbps 4Gb 30nm LPDDR3 w/ 8 banks)
chip size performance
The number of cells per word and bit lines
DEFINITION AND FUNCTION OF DRAM PINS

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HISTORICAL EVOLUTION OF DRAM CELL(1)
◆ Four-transistor DRAM cell

▪ Operations are similar to SRAM cell

▪

p S K
Two storage nodes

e
d e
▪ Periodically refresh is required

T : P r a ▪ Non-destructive read operation

KI

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◆ Three-transistor DRAM cell

▪ One storage node

▪ One Tr. each for “read” and “write”
▪ Non-destructive read operation
▪ Two bit lines and two word lines
(additional contacts increase area)
HISTORICAL EVOLUTION OF DRAM CELL(2)
Two-transistor DRAM cell

K
• Explicit storage cap.

p S
• Destructive read operation

a d e e
(share with the bit line)

: P r
• Two bit lines and one word line

KI T

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One-transistor DRAM cell
• Industry-standard DRAM cell
• Destructive read operation
(share with the bit line)
▪ Charge restoring operation required
 1. In a dynamic RAM cell, binary
data is stored simply as charge in
a capacitor.

K
2. Presence or absence of stored

e p S
charge determines the value of the

d e
stored bit.

r a
3. Data stored as charge in a

KI T : P
capacitor cannot be retained
indefinitely, because the currents
eventually remove or modify the

.
stored charge.
4. Thus, all dynamic memory require
a periodic refreshing of the stored
data

5. Smaller silicon area compared to the typical SRAM cell.

6. No static Power is dissipated for storing charge on the capacitance.
7. Dynamic RAM can achieve higher integration densities than SRAM arrays
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Two Transistor DRAM Cell
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2T DRAM CELL &
2T have explicit Capacitors for storage.
Write ‘1’: BL=1, BL’=0, WL=1 (M1,M2 on)➔ C1 charges to 1 ,C2=0

K
Write ‘0’: BL=0, BL’=1, WL=1 (M1,M2 on)➔ C2 charges to 1 ,C1=0

p S
Read operation is destructive, refresh is needed.

a d e e
T : P r
KI

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 1-T DRAM STRUCTURE

e p S K
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• DRAM cell array with control circuits
• Latch amplifier to sense the small signal difference
• Bit lines and sensing nodes set to half-VDD through equalizer
 DRAM READ OPERATION
➢ CS shared with CBL(=initially half VDD)

p S K
VDD

e
PEQ/PSAEQ

d e
PISOi

a
VPP

r
VDD

P
PISOi/PISOj

:
CS VDD
PISOj
V =

KI T
VPP CBL + CS 2
Word Line
charge sharing between the cell and bit line capacitances

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S cell data restoring BL
VDD
BL/BLB 1/2VDD
BLB
activation of
VDD bit line sense amplifier
PSA
➢ CS : VDD➔ ½VDD+ΔV (destructive)
PSAB
VDD
➢ BL and BLB voltage difference amplified
➢ BLB➔GND, BL➔ VDD storage node is recovered (restoring)
Column Select
VDD
➢ Column switch is enabled by column decoder (BL➔ BL_IO,
BL_IO
BLB➔ BL_IOB)
BL_IO/BL_IOB VDD
BL_IOB
➢ Read Amp. amplifies the voltage difference
Dout_IO • VPP=VDD+Vth for full charge restoration
Dout_IO/
VDD
• PSA and PSAB are sequentially activated to
reduce charge injection and short circuit
Dout_IOB

(a)
current
ASYNCHRONOUS DRAM MODE

e p S K
r a d
◆ Single bit access (different row and column
e
T : P
addresses)

KI
◆ Operation uses address multiplexing scheme
(RAS and CAS).➔Reduce the chip package size

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◆ RAS pull down ➔ operation start
◆ Falling edge of CAS ➔ data (from same word
line) selected
◆ RAS, CAS precharge before new data access
◆ tRAC : memory read latency, time to read data
from falling of RAS
◆ Length of word line is determined by refresh
cycle constraint.
SYNCHRONOUS DRAM MODE

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LEAKAGE CURRENTS IN DRAM CELLS

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REFRESH OPERATION

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DRAM INPUT/OUTPUT CIRCUITS CHARACTERISTIC COMPARISON OF INPUT
◆ Logic level of system board and memory chip are different BUFFERS
➔required to convert logic levels ➔ input/output buffers

Input buffers Buffer type

e p S K Inverter Latch Differential

a d e
Logic

r
threshold By WP/WN

: P
By Vref By Vref

T
determination ratio

KI
(VIH and VIL)

Speed Slow Fastest Fast

.
Inverter type
Standby
Small Smallest Large
current
Sensitivity to
VDD and Large Small Small
temperature
Noise
Differential amp type immunity
Bad Good Good

Precharge
and activation
Constraint None None
signals
Latch type needed
 DRAM INPUT/OUTPUT CIRCUITS DRAM DECODER
◆ Memory output buffers ◆ To select cell from 22M memory array, M
▪ Need to drive large cap. address bits are needed
▪ Keep a high-impedance when chip is not selected ◆ Practically, M transistors in series is
➔ to prevent interference of output
impossible

p S K
➔ decoding scheme is composed of pre

e e
and main decoder

: P r a d
KI T

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PMOS pull-up structure

NMOS pull-up structure

DRAM DECODER (CONT…)

e p S K
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CMN 2
VC = VPP + V = VDD − VTN + VPP
CMN 2 + CCparasitic
VOLTAGE SENSE AMPLIFIERS
To detect signal difference on data lines
• Current-mirror differential
• Popular and good common-

K
mode rejection ratio

p S
• Large area and large power

e e
consumption

: P r a d
T
• Full CMOS latch type

KI
• High speed, small area and low
power

.
• Precharge signal required
• operation cannot be reversed

• Semilatch type
• Between current-mirror type and
full CMOS latch type
 INTERNAL VOLTAGE HALF VDD VOLTAGE GENERATOR
REGULATOR CIRCUIT
◆ Lowering voltage to reduce power consumption
◆ VINT(internal voltage generator)

S K
➔ reduce operating current

d e e p
T : P r a
KI

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Bias ckt Driver Simulated output waveforms

◆ Folded bit line structure with half VDD sensing

scheme
▪ Improve noise immunity and low power consumption
▪ Reduce electric field across thin dielectric
 • Stored data can be retained indefinitely

K
• Simple latch with two stable operating

p S
points

d e e
• Two access switches to connect 1-bit

:P r a
SRAM

I T
• Poly resistor load inverter structure is

K
more compact cell size (resistor stack on

.
top of cell)
• Load R trade off : low power ,wider noise
margin, high speed
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 MEMORY STRUCTURE OF SRAM

◆ Word line selected by row address

K
◆ Cell data kept during read

p S
operation

a d e e
◆ Boosted voltage not required

T : P r
◆ Address multiplexing scheme is not

KI
used (fast access time than DRAM)

.
◆ Depend on applications
▪ ultra low power : load transistor
turns off during read operation
▪ high speed : remains on
OPERATION OF SRAM
Read operation
• Word line enable
• One bit line discharge

p S K
(voltage change of bit line is very

e e
small)

r a d
• Sense amp. detect the voltage

T : P
difference on bit line

KI
• Multi-stage amp. is used to improve

.
read speed
Write operation
• Word line selected by row address
• Write buffer write data into cell
• Write buffer has larger current
driving capability than cell
• Write is faster than read
 LEAKAGE CURRENTS IN SRAM CELLS
◆ Major portion of standby current.
◆ Standby power is key parameter for low power design.
◆ High threshold.
Reduction of leakage

e p S K
degradation of performance

r a d e
KI T : P

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Ij : Junction Current
Data “1” To Substrate
Insub And Ipsub : Subthreshold Leakage
Turn off NMOS and PMOS
Itunneling : Tunneling Current
Cross Thin Gate Oxide
 e p S K
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 SRAM READ CIRCUIT : CURRENT
MODE SENSE AMPLIFIER
• Current-mode sense amp widely
used in SRAM.

S K
• Improve signal sensing speed.

e p
• Independent of bit line cap.

a d e
• Signal line connect to source of

: P r
latch transistor

KI T
• Current difference appears on DL
and DL’

.
• Open-loop gain
g m (m3)  g m (m4)
Gainopen −loop =
g m (m1)  g m (m2)
• Current-mode sense amp:
Drawback- larger power
consumption
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 ◆ Every two rows share a common ground

S K
connection

e p
◆ Every metal to diffusion contact shared by two

d e
adjacent devices

T : P r a
KI

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◆ Based on implant-mask programming
◆ Raised threshold voltage >VOH ➔ “1”-bit
◆ Non-implanted ➔“0”-bit
◆ higher core density (smaller silicon area per
stored bit)
 e p S K
r a d e
◆ Select a particular

: P
memory location in

KI T
array
◆ Row address decoder

.
example
 COLUMN DECODER
NOR ADDRESS DECODER AND PASS
TRANSISTORS

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 COLUMN DECODER
BINARY TREE DECODER

K
• Binary Tree Decoder: A

e p S
binary selection tree with

d e
consecutive stages

: P r a
» The pass transistor network is

KI T
used to select one out of every
two bit lines at each stages.

.
The NOR address decoder is
not needed.
» Advantage: Reduce the
transistor count (2M+1-2+2M)
» Disadvantage: Large number
of series connected nMOS
pass transistors  long data
access time
 FLASH MEMORY
• Flash memory is a non-volatile computer storage
technology that can be electrically erased and
reprogrammed.
• Flash memory has fast read access times.

K
• Flash uses floating-gate transistors.

S
• One limitation of flash memory is that although it can be

e p
read or programmed a byte or a word at a time in a

d e
random access fashion, it must be erased a "block" at a

r a
time.

: P
• Another limitation is that flash memory has a finite

KI T
number of erase-write cycles.
• Flash cell has a charge storage layer such that

.
Vth of a cell can be changed ➔ memorize
information.
• Cell Vth changes depending on the amount of F/G
charge.
• Electrons can be injected(ejected) into(out of) the
F/G through Tox with electric field across Tox

• Write & read binary data to a flash cell

• data ‘0’ ‘OFF’ state (program)
• data ‘1’ ‘ON’ state (erase)
 FLASH MEMORY
◆ The Flash Memory cell has one transistor with floating gate, whose Vt can be
changed(Programmed) by applying electric field to its gate.
◆ The memory cell (transistor) can have two threshold voltages (2 states)
corresponding to the existence of charges (electrons)at the floating gate.

K
◆ Electron injected at the floating gate ➔ higher threshold ➔ “1” state ➔

p S
Transistor OFF.

e e
[Since Memory cell is not turned on by read signal (eg.5V) applied at the

a d
control gate, Bitline stays at Precharge level VDD]

P r
◆ Electron removed from the floating gate ➔ lower threshold ➔ “0” state ➔

T :
Transistor ON.

KI
[Since Memory cell is turned on by read signal (eg.5V) applied at the
control gate, Bitline Precharge level VDD is discharged to GND]

.
Data programming & Data erasing Mechanism
Hot electron injection mechanism
• Apply high Voltage (eg. 12V) to Gate and across drain
to source (eg 6V), Electrons are heated by the High
lateral electric field creating HOT electrons.
• Avalanche breakdown occurs near drain creating
electron hole pairs due to impact ionization.
• High voltage at the gate attracts and injects electrons
into the floating gate through oxide.

Hot electron injection mechanism

 Fowler-Nordheim tunneling mechanism
• The floating gate is programmed/erased by
tunnelling current of the oxide by high field of
10MV/cm.
• When 0V is applied to gate and source, electrons

S K
at floating gate are ejected to the source by

e p
tunnelling effect.

d e
Fowler-Nordheim tunneling mechanism

:P r a
▪ VFG by capacitive coupling after VCG & VD applied
Equivalent Capacitive-Coupling Circuit

I T
QFG CFC C

K
VFG = + VCG + FD VD Ctotal = CFC + CFS + CFB + CFD
Ctotal Ctotal Ctotal

.
▪ min. VCG to turn on the control gate transistor
VT (CG) =
Ctotal Q C
VT ( FG) − FG − FD VD QFG
VT (CG ) = −
CFC CFC CFC CFC

CFS, CFB and CFD : cap. between floating gate and source, bulk and drain
VCG and VD : voltage at control gate and drain
VT(FG) : threshold voltage to turn on the floating gate transistor
QFC : charge stored at floating gate
Ctotal : total cap.
CFC : cap. between floating and control gate
 NOR FLASH MEMORY CELL
ERASE Operation:
• Control gates (word lines) = 0V
• Source Line = high (12V)

S K
• Electrons eject from FG through Tunnelling.

e p
• This makes Low Vt ( State ‘0’)

r a d e
: P
WRITE Operation: [programming]

KI T
• Control gate (selected cell) = High (12V)
• Drain of (selected cell) = Moderate (6V)
Bias conditions and configuration of NOR Cells

.
• Electrons injects due to hot electron effect.
• This makes high Vt (State ‘1’)

READ Operation:
• Control Gate (Selected Cell) = moderate (6V)
• Drain (Selected Cell) = Low (1V)
• If ‘0’ stored , transistor is on and current flows.
• If ‘1’ stored, transistor is off and no current flows.
• Sense amplifier detects current and reads data.
NAND FLASH MEMORY CELL
ERASE Operation
• Source line, P-well2, N-sub = high (20V)
• Wordline = 0V
• This ejects electrons through tunnelling.

K
• Makes Low Vt (State ‘0’)

e e p S
WRITE Operation (Programming):

a d
• Source line, P-well2, N-sub = high (0V)

: P r
• word line (Selected) = high (20V)

KI T
• word line (un-Selected) = moderate (10V)
• Select Line 1= 5V; Select Line 2= 0V;
• Selected Word line high voltage injects

.
electrons
• To floating gate through tunnelling
making high Vt (state ‘1’).

READ Operation
• word line (Selected) = 0V
• word line (un-Selected) = 5V
• Select Line 1= 5V; Select Line 2= 5V;
• If ‘1’ stored, Transistor off, prcharged
bitline stays at VDD(1V).
• If ‘0’ stored , transistor on, bitline will
be grounded.
COMPARISON BETWEEN NOR AND NAND FLASH MEMORY

e p S K
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MULTILEVEL CELL CONCEPT
• To increase memory density,
reducing cell size has been the
primary technique.
• By accurate control of Vt flash
memory can be made to store 4
states or 2 states per cell.
• Figure shows the Vt distribution
of 2bits/cell storage.
FLASH MEMORY CIRCUIT
• High voltage (VPP) is required to
program the cell.
• This is provided by charge pump

K
circuit.

S
Figure shows charge pump circuit

p
•

e e
and its operation.

a d
• CLK=0➔C1,C3…Cn-1 discharges.

:P r
➔V1,V3…Vn-1➔Pulled down.

I T
• Later these nodes charged to their

K
preceding node minus Vt.
• Ex: V1=Vin-Vt & V3=V2-Vt etc.

.
• CLK=1➔C2,C4…Cn discharges.
➔V2,V4…Vn ➔ Pulled Down.
• Charges connected to nodes “CLK” are
transferred to the nodes connected to
“𝐂𝐋𝐊”.

Vout = Vin + ( VDD − VT ( MN1)) + + ( VDD − VT ( MNn))

 FERROELECTRIC RANDOM ACCESS MEMORY
Introduction Ferro-electric Materials
• The content of an FRAM cell is • Ferroelectric materials are an electrical analogy
not stored in the form of charge to ferromagnets, they can carry a permanent

K
carriers in a ‘floating gate’ as we electric dipole moment.

p S
see in FLASH and EEPROM. • Ferroelectrics are non-polar above the Curie

e e
temperature (TC) but are spontaneously

d
• The information – logically 0 or 1

a
polarized with a spontaneous lattice distortion

r
– is contained in the polarization

: P
of the ferroelectric material lead below the Curie temperature.

KI T
zirconate titanate, PZT (Pb • From this it follows that at a temperature T >
(ZrTi)O3). TC the crystal does not exhibit ferroelectricity,
while for T < TC it is ferroelectric.

.
• This material is placed between
two electrodes in the form of a
thin film, in a similar way to the
structure of a capacitor.
• An FRAM memory cell has the
same structure as a DRAM cell
and consists of a transistor and a
capacitor, but in this case the
FRAM cell contains a capacitor
with a ferroelectric dielectric.
 CONTD..
• It is possible to change the polarization and distortion through applied electric field.
• The structure and the size of domains are dependent on the type and magnitude of
distortion present in crystal structure.
• Different states can coexist as domains, these domains can be switched and therefore the

K
domain patterns can be manipulated by application of the electric field.

p S
• The polarization reversal can be observed by measuring the ferroelectric hysteresis.

e
• A very strong field could lead to the reversal of the polarization within a domain, known as

d e
domain switching.

T : P r a
KI

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 HYSTERESIS CHARACTERISTIC OF A FERROELECTRIC CAPACITOR
QR and -QR : Remnant Charge Co: Linear capacitance for data “0”
QS and -QS : Saturation Charge C1: Linear capacitance for data “1”
VC : Coercive Voltage
VS : Saturation Voltage There are three important points on a

K
ferroelectric hysteresis loop:

e p S
• Voltage coercivity (VC): This is the electric

d e
field (voltage) required to switch the

r a
polarization between positive and negative

T : P
values.

KI
• Remnant polarization (QR): The amount of

.
polarization that remains in the material
after the electric field (Voltage) is removed.

• Saturation polarization (VS): This is the

maximum amount of polarization that can
be induced in the material at high electric
field strength.
 Similar to DRAM except plate line
STRUCTURE AND OPERATION OF FRAM
• Timing diagram shows read cell
data “1”.Reference cells with “0”
stored are placed per column.

K
• PPRE ➔ High➔ BL &BLB➔VSS.

S
• Activate Wordline (WL0)➔boost

e p
to Vpp to restore Data.

d e
Reference Wordline (RWL1)

a
•

P r
activated at same time.

KI T : • PL and RPL➔ apply Step signal ➔ Charge change

Qs to –Qs, Positive charge appears at BL.

.
• When wordline enabled, capacitor dividers is
formed, resulting in voltages diffrence as follows:
Step-sensing scheme
C1
Voltage difference for data ‘1’ is V1 = VDD
C1 + CBL
C0
Voltage difference for data ‘0’ is V0 = VDD
C0 + CBL
C1 and C0 : linearly modeled ferroelectric cap
PROBLEMS OF FRAM
◆ Step-sensing scheme cause reliability issues
▪ Pulse sensing scheme also used with read speed penalty

S K
◆ Fatigue

e e p
▪ Capacitance charge gradually degraded with repeated use
◆ Imprint

: P r a d
KI T
▪ Ferroelectric cap tends to stay at one state preferably when state
maintained for a long time