Asus K93SV X93SV PBL80 LA-7441P Rev0.3 Schematic
Uploaded by
Nyobe VasquezAsus K93SV X93SV PBL80 LA-7441P Rev0.3 Schematic
Uploaded by
Nyobe Vasquez5 4 3 2 1
D D
Compal Confidential
C
PBL80 Project C
LA-7441P REV 0.3 Schematic
B B
Intel Sandy Bridge/Cougar Point
N12P-GS/Co lay GV - Optimus Only
2011-04-07 Rev. 0.3
A A
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2010/12/03 Deciphered Date 2011/12/03 Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Cover Page
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
0.3
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
PBL80 LA-7441P M/B
Date: Monday, April 11, 2011 Sheet 1 of 59
5 4 3 2 1
5 4 3 2 1
Compal Confidential
Model Name : PBL80 File
Name : LA-7441P
D
Fan Control D
page 5
PEG(DIS) 100MHz PCI-E 2.0x16 5GT/s PER LANE Mobile Sandy Bridge
133MHz
CPU
Dual Core/Quad Core
Memory BUS(DDRIII) 204pin DDRIII-SO-DIMM X4
BANK 0, 1, 2, 3 page 12,13
N12P GV/N12P GS Optimus Only Socket-rPGA989 Dual Channel
128*16 1GB/2GB 1.5V DDRIII 1066/1333
37.5mm*37.5mm page 5,6,7,8,9,10,11
64*16 512MB/1GB page 14~25
CRT DMI X4 FDI X8 USB Left X 1 (Co lay with USB3.0 Conn)
page 26
USB port 4
page 39
LVDS Conn.
page 27
USB
Intel Cougar Point USB/B Right X 3 Int. Camera 0.3M RTS5129 3IN1
5V 480Mbps USB port 0,1,2 USB port 10 USB port 11
page 39 page 27 page 39
C
HDMI Conn. PCBGA989 C
page 28 25mm*25mm
SATA port 0 SATA HDD/ 3.5"
5V 1.5GHz(150MB/s) page 38
PCI-Express x 8 (PCIE2.0 2.5GT/s) 100MHz
port 4 port 2 port 1 SATA port 1 SATA HDD/ 2.5"
5V 1.5GHz(150MB/s) page 38
USB 3.0 conn x1 PCIeMini Card RTL8105E 10/100M
SATA port 2 SATA ODD
WLAN & BT Combo RTL8111E 1G 5V 1.5GHz(150MB/s) page 38
PCIe port 4
PCIe port 1 page 29,30,31,32,33
page 45 ,34,35,36,37
USB port 13 page 40 HD Audio 3.3V 24.576MHz/48Mhz
PCIe port 2
page 39 LPC BUS
RJ45 33MHz
Bus switch HDA Codec
page 41 ALC269
page 40 page 42
ODD/B ENE KB930
page 38 BIOS ROM
B
page 43 page 41 B
USB & LID/B
page 39
MIC CONN HP CONN SPK CONN
Touch Pad Int.KBD page 42 page 42 page 42
page 39 page 44
TouchPad & Card Reader
& LED/B
page 39
EC ROM
Power/B page 44
page 44
RTC CKT.
page 29
CPU XDP
A
DC/DC Interface CKT. page 5 A
page 46
Power Circuit DC/DC PCH XDP
page 47~58 page 29
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2010/12/03 Deciphered Date 2011/12/03 Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Block Diagrams
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
WWW.AliSaler.Com
0.3
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
PBL80 LA-7441P M/B
Date: Monday, April 11, 2011 Sheet 2 of 59
5 4 3 2 1
5 4 3 2 1
(ipeak=10A imax=7A DESIGN CURRENT 10A +5VALWP +5VALW(PJP305,PJP306)
+5VALW_PCH(PJ334)
B+
SUSP
+5VALW DESIGN CURRENT 6A +5VS
AP4800BGM
D
SUSP# D
+5VALW DESIGN CURRENT 2A +1.8VSP +1.8VS(PJP401)
SY8033BDBC
SUSP#
RT8205EGQW +5VALW DESIGN CURRENT 6A +VCCSAP +VCCSA(PJP801)
SY8035DBC
ipeak=6A imax=4.2A +3VALWP +3VALW(PJP303) +3V_EC(R715)
+3VALW_PCH(J1)
WOL_EN#
+3VALW P-CHANNEL DESIGN CURRENT 170mA +3V_LAN
AO3413
SUSP
+3VALW DESIGN CURRENT 1.6A +3VS
AP4800BGM
DGPU_PWR_EN#
P-CHANNEL DESIGN CURRENT 700mA +3VS_DGPU
C
AO-3413 C
VGA_ENVDD
P-CHANNEL DESIGN CURRENT 3A +LCD_VDD
AO-3413
DRVON
Ipeak=94A, Imax(TDP)=56A +CPU_CORE
NCP5911MNTBG SUSP#
DESIGN CURRENT 2A +12VS
SUSP# TPS40210DRCR
TPS51218DSCR DESIGN CURRENT 35A +VGA_CORE
SUSP#
DESIGN CURRENT 18A +1.05VS_VCCP
RT8209BGQW +1.05VS_PCH(JP2)
B
DGPU_PWR_EN# B
N-CHANNEL DESIGN CURRENT 3.66A +1.05VS_DGPU
+1.05VS_VCCP AO3416
SYSON
Ipeak = 30A Imax= 21A +1.5VP +1.5V(PJP501,PJP502.PJP503)
SUSP
RT8209BGQW N-CHANNEL DESIGN CURRENT 600mA +1.5VS
+1.5V SI4856ADY
RUN_ON_CPU1.5VS3
N-CHANNEL DESIGN CURRENT 10A +1.5V_CPU
+1.5V SI4856ADY
SUSP
DESIGN CURRENT 2A +0.75VSP +0.75VS(PJP601)
+1.5V APL5336KAI-TRL
A
VGA_PWROK# A
DESIGN CURRENT 11A +VRAM_1.5VS
+1.5V TPCA8059
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2010/12/03 Deciphered Date 2011/12/03 Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Power Map
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
0.3
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
PBL80 LA-7441P M/B
Date: Monday, April 11, 2011 Sheet 3 of 59
5 4 3 2 1
5 4 3 2 1
( O MEANS ON X MEANS OFF )
Voltage Rails
SIGNAL
+5VS STATE SLP_S3# SLP_S4# SLP_S5#
+RTCVCC B+ +5VL +5VALW +1.5V
+3VS
+3VL +3VALW Full ON HIGH HIGH HIGH
+1.8VS
+5VALW_PCH
power +1.5VS S1(Power On Suspend) HIGH HIGH HIGH
plane +3VALW_PCH
+1.05VS_VCCP
D
+3V_LAN S3 (Suspend to RAM) LOW HIGH HIGH D
+0.75VS
+3V_EC
+CPU_CORE S4 (Suspend to Disk) LOW LOW HIGH
+VSB
+VGA_CORE
S5 (Soft OFF) LOW LOW LOW
+GFX_CORE
+VCCSA G3 LOW LOW LOW
State
+VRAM_1.5VS
+3VS_DGPU
+1.05VS_DGPU
Function VRAM GPU Board ID
+12VS
Samsung Hynix Samsung Hynix
description VRAM 64bits 64bits 128bits 128bits N12P-GS N12P-GV Adaptor
S0 explain VRAM Strap pin Strap pin Strap pin Strap pin Strap pin Strap pin Adaptor
O O O O O O
BTO 8PCS@ PD 20K PD 15K PD 45.3K PD 34.8K N12PGS@ N12PGV@ 90W@, 120W@
S1
O O O O O O
Function Crisis recovery HDMI WLAN+BT LAN
S3
O O O O O X
C description BUS SWITCH HDMI WLAN+BT(BT pin 51) WLAN+BT(BT pin 5) Giga LAN 10/100M LAN C
S5 S4/AC
O O O O X X explain BUS SWITCH HDMI WLAN+BT(BT pin 51) WLAN+BT(BT pin 5) Strap pin Strap pin
S5 S4/ Battery only BTO Debug@ HDMI@ BT@ COMBO@ 8111E@ 8105E@
O O O X X X
S5 S4/AC & Battery
don't exist
O X X X X X Function USB3.0/2.0 Colay SATA3.0 Repeater Chip SATA Preemphasis SATA Equalization
description USB3.0 USB2.0 MAXIM TI Preemphasis Equalization
explain USB3.0 USB2.0 MAX4951 SN75LVCP601 Enable Disable Maximum Normal
BTO USB3@ USB2@ MAXIM@ TI@ DEN@ NDEN@ EQ@ NEQ@
PCH SM Bus Address
Function SATA path
Power Device HEX Address PCH Repeater
description
+3VS DDR SO-DIMMA1 A0 H 1010 0000 b
explain PCH Repeater
+3VS DDR SO-DIMMA2 A0 H 1010 0010 b
B B
+3VS DDR SO-DIMMB1 A4 H 1010 0100 b BTO SATA@ SATARP@
+3VS DDR SO-DIMMB2 A0 H 1010 0110 b
+3VS WLAN
EC SM Bus1 Address EC SM Bus2 Address
Power Device HEX Address Power Device HEX Address
+3VL Smart Battery 16 H 0001 0110 b +3VS PCH 96 H 1001 0110 b
+3VL Smart Charger 12 H 0001 0010 b +3VS VGA Thermal Sensor 9E H 1001 1010 b
(Internal)
A A
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2010/12/03 Deciphered Date 2011/12/03 Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Notes List
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
WWW.AliSaler.Com
Custom 0.3
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
PBL80 LA-7441P M/B
Date: Monday, April 11, 2011 Sheet 4 of 59
5 4 3 2 1
5 4 3 2 1
C1 Support Dual Core/ Quad Core
2 1 H_PWRGOOD JCPUB
0.1U_0402_16V4Z
BCLK A28 CLK_CPU_DMI <30>
MISC
CLOCKS
<33> H_SNB_IVB# C26 SNB_IVB# BCLK# A27 CLK_CPU_DMI# <30>
C2
2 1 H_PROCHOT# T1 PAD TP_SKTOCC# AN34
@ SKTOCC#
A16 1 R3 2
DPLL_REF_SSCLK If motherboard only supports external
DPLL_REF_SSCLK#
A15 1 R4 2 1K_0402_5% +1.05VS_VCCP eDP
0.1U_0402_16V4Z 1K_0402_5% graphics:
D D
Connect DPLL_REF_SSCLK on Processor to
T2 PAD H_CATERR# AL33
@ CATERR# GND through 1K +/- 5% resistor.
C55 Connect DPLL_REF_SSCLK# on Processor
THERMAL
2 1 PM_SYS_PWRGD_BUF to VCCP through 1K +/- 5% resistor
H_PECI AN33 R8 H_DRAMRST#
<34,43> H_PECI PECI SM_DRAMRST# H_DRAMRST# <7>
DDR3
MISC
0.1U_0402_16V4Z
<43> H_PROCHOT# 1 2 H_PROCHOT#_R AL32
PROCHOT# SM_RCOMP[0]
AK1 SM_RCOMP_0 R7 2 1 140_0402_1% DDR3 Compensation Signals
R6 56_0402_5%
SM_RCOMP[1]
A5 SM_RCOMP_1 R8 2 1 25.5_0402_1% Layout Note:Please these
A4 SM_RCOMP_2 R9 2 1 200_0402_1% resistors near Processor
SM_RCOMP[2]
<34> H_THERMTRIP# 1 2 H_THERMTRIP#_R AN32 THERMTRIP#
from DDR
R10 0_0402_5%
AP29 XDP_PRDY#_R R11 1 @ 2 0_0402_5% XDP_PRDY#
PRDY# XDP_PREQ#_R R12 @ XDP_PREQ#
AP27 1 2 0_0402_5%
PREQ#
AR26 XDP_TCK_R R13 1 @ 2 0_0402_5% XDP_TCK
+1.05VS_VCCP TCK
PWR MANAGEMENT
AR27 XDP_TMS_R R14 1 @ 2 0_0402_5% XDP_TMS
JTAG & BPM
TMS XDP_TRST#_R XDP_TRST# Routed as a single daisy chain
Processor Pullups <31> H_PM_SYNC AM34 PM_SYNC TRST# AP30 R15 1 @ 2 0_0402_5%
AR28 XDP_TDI_R R16 1 @ 2 0_0402_5% XDP_TDI
R17 H_PROCHOT# TDI XDP_TDO_R XDP_TDO
2 1 62_0402_5% AP26 R18 1 @ 2 0_0402_5%
H_PWRGOOD TDO R20
<34> H_PWRGOOD AP33 UNCOREPWRGOOD
1 2 +3VS
1K_0402_5%
AL35 XDP_DBRESET#_R R21 1 @ 2 0_0402_5% XDP_DBRESET#
PM_SYS_PWRGD_BUF 1 DBR# XDP_DBRESET# <29,31>
2 PM_DRAM_PWRGD_R V8 SM_DRAMPWROK
C R22 130_0402_5% C
R23 2 1 10K_0402_5% H_PWRGOOD AT28 XDP_BPM#0_R R24 1 @ 2 0_0402_5% XDP_BPM#0
BPM#[0] XDP_BPM#1_R R25 @ 0_0402_5% XDP_BPM#1
BPM#[1] AR29 1 2
AR30 XDP_BPM#2_R R26 1 @ 2 0_0402_5% XDP_BPM#2
BUF_CPU_RST# BPM#[2] XDP_BPM#3_R R27 @ 0_0402_5% XDP_BPM#3
AR33 RESET# BPM#[3] AT30 1 2
AP32 XDP_BPM#4_R R28 1 @ 2 0_0402_5%
BPM#[4] CFG12 <10>
AR31 XDP_BPM#5_R R30 1 @ 2 0_0402_5%
BPM#[5] CFG13 <10>
AT31 XDP_BPM#6_R R32 1 @ 2 0_0402_5%
+3VALW FIT 1.5V POWER PLANE OF CPU BPM#[6] XDP_BPM#7_R CFG14 <10>
Follow DG 0.71 AR32 R34 1 @ 2 0_0402_5%
BPM#[7] CFG15 <10>
+1.5V_CPU
Close to CPU side
1
C3
Sandy Bridge_rPGA_Rev0p61
1
0.1U_0402_16V4Z CONN@
2
U1 R36
74AHC1G09GW_TSSOP5 200_0402_5%
5
1 2 1
P
<31> PWROK
R37 0_0402_5% B 4 PM_SYS_PWRGD_BUF
O
<31> DRAMPWROK 2 A PU/PD for JTAG signals
G
+1.05VS_VCCP
1
3
@ XDP_TMS_R R39 2 1 51_0402_5%
R38
39_0402_5% XDP_TDI_R R40 2 1 51_0402_5%
1 2
XDP_TDO_R R41 2 1 51_0402_5%
D @
SUSP 2 Q1 XDP_TCK_R R42 2 1 51_0402_5%
<46,53> SUSP
G 2N7002_SOT23
B XDP_TRST#_R R43 B
S 2 1 51_0402_5%
3
CHANGE U5 TO OPEN DRAIN MOS,OUTPUT=1.5V
JXDP1 @
XDP Connector XDP_PREQ# 1 +5VS
FAN Control Circuit
XDP_PRDY# 2
Buffered reset to CPU 3 1A
XDP_BPM#0 4
XDP_BPM#1 5
6
XDP_BPM#2 7
XDP_BPM#3 8 2
C56
9
2 1 PLT_RST# H_PWRGOOD R44 1 @ 2 1K_0402_5%XDP_CPU_HOOK0 10 C4 20mil JFAN
PBTN_OUT# R45 1 @ 2 0_0402_5% XDP_CPU_HOOK1 11 10U_0805_10V4Z +FAN_VCC 1
<29,31,43> PBTN_OUT# 1 1
1000P_0402_50V7K
+3VS CFG0 R46 1 @ 2 1K_0402_5%XDP_CPU_HOOK2 12 2
<10> CFG0 VGATE 2
0.1U_0402_16V4Z <31,43,55> VGATE R47 1 @ 2 0_0402_5% XDP_CPU_HOOK3 13 2 3
U2 3
C57 <10,30> CLK_RES_ITP 14
15 1 8 C5 4
PLT_RST# +1.05VS_VCCP <10,30> CLK_RES_ITP# EN GND GND
2 1 1 +1.05VS_VCCP 16 2 7 @ 5
C6 PLT_RST# @ XDP_CPU_HOOK6 +FAN_VCC VIN GND 1 GND
1 2 17 3
VOUT GND
6
0.1U_0402_16V4Z R48 1K_0402_5% XDP_DBRESET# 18 1 2 4 5 CVILU_CI4403M1HRT-NH
<43> EN_DFAN1 VSET GND
1
0.1U_0402_16V4Z 19 R49 @
2 R50 XDP_TDO 330_0402_5% G996P11U SOP 8P
20
1
For ESD request 75_0402_5% XDP_TRST# 21
0.1U_0402_10V6K
C8
1 1 XDP_TDI 22 C7 R51 10K_0402_5%
5
1U_0603_10V6K
C327
U3 R52 XDP_TMS 23 0.047U_0402_16V7K 2 1 +3VS
2
2
1 43_0402_1% 24
P
R55 NC BUFO_CPU_RST# BUF_CPU_RST#
Y 4 1 2 25 FAN_SPEED1 <43>
A
1 2 2 2 2 XDP_TCK 26 A
<33,39> PLT_RST# A 1
G
0_0402_5% SN74LVC1G07DCKR_SC70-5 27
@ 28 C9 @
3
R53 0.01U_0402_25V7K
0_0402_5% 2
ACES_87152-26051
2
Security Classification Compal Secret Data Compal Electronics, Inc.
For ESD request. Issued Date 2010/12/03 Deciphered Date 2011/12/03 Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Sandy Bridge(1/6)-CLK/MISC/JTAG/XDP/FAN
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom 0.3
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
PBL80 LA-7441P M/B
Date: Monday, April 11, 2011 Sheet 5 of 59
5 4 3 2 1
5 4 3 2 1
PEG_ICOMPI and RCOMPO signals should be
+1.05VS_VCCP shorted and routed
with - max length = 500 mils - typical
1
D impedance = 43 mohms D
R54
24.9_0402_1%
PEG_ICOMPO signals should be routed with -
max length = 500 mils
JCPUA
- typical impedance = 14.5 mohms
2
J22 PEG_COMP
PEG_ICOMPI
J21
PEG_ICOMPO
<31> DMI_PTX_CRX_N0 B27 H22
DMI_RX#[0] PEG_RCOMPO
<31> DMI_PTX_CRX_N1 B25
DMI_RX#[1]
<31> DMI_PTX_CRX_N2 A25 PCIE_GTX_C_CRX_N[0..15] <14>
DMI_RX#[2] PCIE_GTX_C_CRX_N15
<31> DMI_PTX_CRX_N3 B24 K33
DMI_RX#[3] PEG_RX#[0] PCIE_GTX_C_CRX_N14
PEG_RX#[1] M35
B28 L34 PCIE_GTX_C_CRX_N13
<31> DMI_PTX_CRX_P0 DMI_RX[0] PEG_RX#[2]
<31> DMI_PTX_CRX_P1 B26 J35 PCIE_GTX_C_CRX_N12
DMI_RX[1] PEG_RX#[3]
DMI
A24 J32 PCIE_GTX_C_CRX_N11
<31> DMI_PTX_CRX_P2 DMI_RX[2] PEG_RX#[4]
<31> DMI_PTX_CRX_P3 B23 H34 PCIE_GTX_C_CRX_N10
DMI_RX[3] PEG_RX#[5] PCIE_GTX_C_CRX_N9
PEG_RX#[6] H31
G21 G33 PCIE_GTX_C_CRX_N8
<31> DMI_CTX_PRX_N0 DMI_TX#[0] PEG_RX#[7] PCIE_GTX_C_CRX_N7
<31> DMI_CTX_PRX_N1 E22 DMI_TX#[1] PEG_RX#[8] G30
F21 F35 PCIE_GTX_C_CRX_N6
<31> DMI_CTX_PRX_N2 DMI_TX#[2] PEG_RX#[9]
D21 E34 PCIE_GTX_C_CRX_N5
<31> DMI_CTX_PRX_N3 DMI_TX#[3] PEG_RX#[10] PCIE_GTX_C_CRX_N4
PEG_RX#[11] E32
G22 D33 PCIE_GTX_C_CRX_N3
<31> DMI_CTX_PRX_P0 DMI_TX[0] PEG_RX#[12] PCIE_GTX_C_CRX_N2
<31> DMI_CTX_PRX_P1 D22 DMI_TX[1] PEG_RX#[13] D31
PCI EXPRESS* - GRAPHICS
F20 B33 PCIE_GTX_C_CRX_N1
<31> DMI_CTX_PRX_P2 DMI_TX[2] PEG_RX#[14] PCIE_GTX_C_CRX_N0
<31> DMI_CTX_PRX_P3 C21 DMI_TX[3] PEG_RX#[15] C32
PCIE_GTX_C_CRX_P15 PCIE_GTX_C_CRX_P[0..15] <14>
PEG_RX[0] J33
L35 PCIE_GTX_C_CRX_P14
PEG_RX[1] PCIE_GTX_C_CRX_P13
PEG_RX[2] K34
FDI_CTX_PRX_N0 A21 H35 PCIE_GTX_C_CRX_P12 PAY ATTENTION ON PCIE SWAP WHEN REVIEW
<31> FDI_CTX_PRX_N0 FDI_CTX_PRX_N1 FDI0_TX#[0] PEG_RX[3] PCIE_GTX_C_CRX_P11
<31> FDI_CTX_PRX_N1 H19 FDI0_TX#[1] PEG_RX[4] H32
C FDI_CTX_PRX_N2 PCIE_GTX_C_CRX_P10 C
<31> FDI_CTX_PRX_N2 E19 FDI0_TX#[2] PEG_RX[5] G34
FDI_CTX_PRX_N3 F18 G31 PCIE_GTX_C_CRX_P9
Intel(R) FDI
<31> FDI_CTX_PRX_N3 FDI_CTX_PRX_N4 FDI0_TX#[3] PEG_RX[6] PCIE_GTX_C_CRX_P8
<31> FDI_CTX_PRX_N4 B21 FDI1_TX#[0] PEG_RX[7] F33
FDI_CTX_PRX_N5 C20 F30 PCIE_GTX_C_CRX_P7
<31> FDI_CTX_PRX_N5 FDI_CTX_PRX_N6 FDI1_TX#[1] PEG_RX[8] PCIE_GTX_C_CRX_P6
<31> FDI_CTX_PRX_N6 D18 FDI1_TX#[2] PEG_RX[9] E35
FDI_CTX_PRX_N7 E17 E33 PCIE_GTX_C_CRX_P5
<31> FDI_CTX_PRX_N7 FDI1_TX#[3] PEG_RX[10]
F32 PCIE_GTX_C_CRX_P4
PEG_RX[11] PCIE_GTX_C_CRX_P3
D34
FDI_CTX_PRX_P0 PEG_RX[12] PCIE_GTX_C_CRX_P2
<31> FDI_CTX_PRX_P0 A22 E31
FDI_CTX_PRX_P1 FDI0_TX[0] PEG_RX[13] PCIE_GTX_C_CRX_P1
<31> FDI_CTX_PRX_P1 G19 C33
FDI_CTX_PRX_P2 FDI0_TX[1] PEG_RX[14] PCIE_GTX_C_CRX_P0
<31> FDI_CTX_PRX_P2 E20 B32
FDI_CTX_PRX_P3 FDI0_TX[2] PEG_RX[15]
<31> FDI_CTX_PRX_P3 G18 PCIE_CTX_C_GRX_N[0..15] <14>
FDI_CTX_PRX_P4 FDI0_TX[3] PCIE_CTX_GRX_N15 C10 0.22U_0402_10V6K PCIE_CTX_C_GRX_N15
<31> FDI_CTX_PRX_P4 B20 M29 1 2
FDI_CTX_PRX_P5 FDI1_TX[0] PEG_TX#[0] PCIE_CTX_GRX_N14 C11 0.22U_0402_10V6K PCIE_CTX_C_GRX_N14
<31> FDI_CTX_PRX_P5 C19 M32 1 2
FDI_CTX_PRX_P6 FDI1_TX[1] PEG_TX#[1] PCIE_CTX_GRX_N13 C12 0.22U_0402_10V6K PCIE_CTX_C_GRX_N13
<31> FDI_CTX_PRX_P6 D19 M31 1 2
FDI_CTX_PRX_P7 FDI1_TX[2] PEG_TX#[2] PCIE_CTX_GRX_N12 C13 0.22U_0402_10V6K PCIE_CTX_C_GRX_N12
<31> FDI_CTX_PRX_P7 F17 L32 1 2
FDI1_TX[3] PEG_TX#[3] PCIE_CTX_GRX_N11 C14 0.22U_0402_10V6K PCIE_CTX_C_GRX_N11
L29 1 2
+1.05VS_VCCP FDI_FSYNC0 PEG_TX#[4] PCIE_CTX_GRX_N10 C15 0.22U_0402_10V6K PCIE_CTX_C_GRX_N10
<31> FDI_FSYNC0 J18 K31 1 2
FDI_FSYNC1 FDI0_FSYNC PEG_TX#[5] PCIE_CTX_GRX_N9 C16 0.22U_0402_10V6K PCIE_CTX_C_GRX_N9
<31> FDI_FSYNC1 J17 K28 1 2
FDI1_FSYNC PEG_TX#[6] PCIE_CTX_GRX_N8 C17 0.22U_0402_10V6K PCIE_CTX_C_GRX_N8
J30 1 2
FDI_INT PEG_TX#[7] PCIE_CTX_GRX_N7 C18 0.22U_0402_10V6K PCIE_CTX_C_GRX_N7
<31> FDI_INT H20 J28 1 2
FDI_INT PEG_TX#[8] PCIE_CTX_GRX_N6 C19 0.22U_0402_10V6K PCIE_CTX_C_GRX_N6
H29 1 2
PEG_TX#[9]
1
<31> FDI_LSYNC0 FDI_LSYNC0 J19 G27 PCIE_CTX_GRX_N5 C20 1 2 0.22U_0402_10V6K PCIE_CTX_C_GRX_N5
R56 FDI_LSYNC1 FDI0_LSYNC PEG_TX#[10] PCIE_CTX_GRX_N4 C21 0.22U_0402_10V6K PCIE_CTX_C_GRX_N4
<31> FDI_LSYNC1 H17 E29 1 2
FDI1_LSYNC PEG_TX#[11] PCIE_CTX_GRX_N3 C22 0.22U_0402_10V6K PCIE_CTX_C_GRX_N3
24.9_0402_1% F27 1 2
PEG_TX#[12] PCIE_CTX_GRX_N2 C23 0.22U_0402_10V6K PCIE_CTX_C_GRX_N2
D28 1 2
PEG_TX#[13] PCIE_CTX_GRX_N1 C24 0.22U_0402_10V6K PCIE_CTX_C_GRX_N1
F26 1 2
2
PEG_TX#[14] PCIE_CTX_GRX_N0 C25 0.22U_0402_10V6K PCIE_CTX_C_GRX_N0
E25 1 2
EDP_COMP PEG_TX#[15]
A18 PCIE_CTX_C_GRX_P[0..15] <14>
eDP_COMPIO PCIE_CTX_GRX_P15 C26 0.22U_0402_10V6K PCIE_CTX_C_GRX_P15
A17 M28 1 2
eDP_ICOMPO PEG_TX[0] PCIE_CTX_GRX_P14 C27 0.22U_0402_10V6K PCIE_CTX_C_GRX_P14
B16 M33 1 2
eDP_HPD PEG_TX[1] PCIE_CTX_GRX_P13 C28 0.22U_0402_10V6K PCIE_CTX_C_GRX_P13
M30 1 2
B PEG_TX[2] PCIE_CTX_GRX_P12 C29 0.22U_0402_10V6K PCIE_CTX_C_GRX_P12 B
L31 1 2
PEG_TX[3] PCIE_CTX_GRX_P11 C30 0.22U_0402_10V6K PCIE_CTX_C_GRX_P11
C15 L28 1 2
eDP_AUX PEG_TX[4] PCIE_CTX_GRX_P10 C31 0.22U_0402_10V6K PCIE_CTX_C_GRX_P10
D15 K30 1 2
eDP_AUX# PEG_TX[5]
eDP
K27 PCIE_CTX_GRX_P9 C32 1 2 0.22U_0402_10V6K PCIE_CTX_C_GRX_P9
PEG_TX[6] PCIE_CTX_GRX_P8 C33 0.22U_0402_10V6K PCIE_CTX_C_GRX_P8
J29 1 2
PEG_TX[7] PCIE_CTX_GRX_P7 C34 0.22U_0402_10V6K PCIE_CTX_C_GRX_P7
C17 J27 1 2
eDP_TX[0] PEG_TX[8] PCIE_CTX_GRX_P6 C35 0.22U_0402_10V6K PCIE_CTX_C_GRX_P6
F16 H28 1 2
eDP_TX[1] PEG_TX[9] PCIE_CTX_GRX_P5 C36 0.22U_0402_10V6K PCIE_CTX_C_GRX_P5
C16 G28 1 2
eDP_TX[2] PEG_TX[10] PCIE_CTX_GRX_P4 C37 0.22U_0402_10V6K PCIE_CTX_C_GRX_P4
G15 E28 1 2
eDP_TX[3] PEG_TX[11] PCIE_CTX_GRX_P3 C38 0.22U_0402_10V6K PCIE_CTX_C_GRX_P3
F28 1 2
PEG_TX[12] PCIE_CTX_GRX_P2 C39 0.22U_0402_10V6K PCIE_CTX_C_GRX_P2
C18 D27 1 2
eDP_TX#[0] PEG_TX[13] PCIE_CTX_GRX_P1 C40 0.22U_0402_10V6K PCIE_CTX_C_GRX_P1
E16 E26 1 2
eDP_TX#[1] PEG_TX[14] PCIE_CTX_GRX_P0 C41 0.22U_0402_10V6K PCIE_CTX_C_GRX_P0
D16 D25 1 2
eDP_TX#[2] PEG_TX[15]
F15
eDP_TX#[3]
Sandy Bridge_rPGA_Rev0p61
CONN@
Typ- suggest 220nF. The change in AC capacitor
value from 100nF to 220nF is to enable
compatibility with future platforms having PCIE
Gen3 (8GT/s)
A A
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2010/12/03 Deciphered Date 2011/12/03 Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Sandy Bridge(2/6)-DMI/FDI/PEG/eDP
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
WWW.AliSaler.Com
Custom 0.3
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
PBL80 LA-7441P M/B
Date: Monday, April 11, 2011 Sheet 6 of 59
5 4 3 2 1
5 4 3 2 1
JCPUC JCPUD
<12> DDR_A_D[0..63]
<13> DDR_B_D[0..63]
SA_CLK[0] AB6 DDRA_CLK0 <12> SB_CLK[0] AE2 DDRB_CLK0 <13>
SA_CLK#[0] AA6 DDRA_CLK0# <12> SB_CLK#[0] AD2 DDRB_CLK0# <13>
DDR_A_D0 C5 V9 DDR_B_D0 C9 R9
DDR_A_D1 SA_DQ[0] SA_CKE[0] DDRA_CKE0 <12> DDR_B_D1 SB_DQ[0] SB_CKE[0] DDRB_CKE0 <13>
D5 A7
DDR_A_D2 SA_DQ[1] DDR_B_D2 SB_DQ[1]
D3 D10
DDR_A_D3 SA_DQ[2] DDR_B_D3 SB_DQ[2]
D2 C8
D DDR_A_D4 SA_DQ[3] DDR_B_D4 SB_DQ[3] D
D6 AA5 DDRA_CLK1 <12> A9 AE1 DDRB_CLK1 <13>
DDR_A_D5 SA_DQ[4] SA_CLK[1] DDR_B_D5 SB_DQ[4] SB_CLK[1]
C6 AB5 DDRA_CLK1# <12> A8 AD1 DDRB_CLK1# <13>
DDR_A_D6 SA_DQ[5] SA_CLK#[1] DDR_B_D6 SB_DQ[5] SB_CLK#[1]
C2 V10 DDRA_CKE1 <12> D9 R10 DDRB_CKE1 <13>
DDR_A_D7 SA_DQ[6] SA_CKE[1] DDR_B_D7 SB_DQ[6] SB_CKE[1]
C3 D8
DDR_A_D8 SA_DQ[7] DDR_B_D8 SB_DQ[7]
F10 G4
DDR_A_D9 SA_DQ[8] DDR_B_D9 SB_DQ[8]
F8 F4
DDR_A_D10 SA_DQ[9] DDR_B_D10 SB_DQ[9]
G10 AB4 DDRA_CLK2 <12> F1 AB2 DDRB_CLK2 <13>
DDR_A_D11 SA_DQ[10] SA_CLK[2] DDR_B_D11 SB_DQ[10] SB_CLK[2]
G9 AA4 DDRA_CLK2# <12> G1 AA2 DDRB_CLK2# <13>
DDR_A_D12 SA_DQ[11] SA_CLK#[2] DDR_B_D12 SB_DQ[11] SB_CLK#[2]
F9 W9 DDRA_CKE2 <12> G5 T9 DDRB_CKE2 <13>
DDR_A_D13 SA_DQ[12] SA_CKE[2] DDR_B_D13 SB_DQ[12] SB_CKE[2]
F7 F5
DDR_A_D14 SA_DQ[13] DDR_B_D14 SB_DQ[13]
G8 F2
DDR_A_D15 SA_DQ[14] DDR_B_D15 SB_DQ[14]
G7 SA_DQ[15] G2 SB_DQ[15]
DDR_A_D16 K4 AB3 DDR_B_D16 J7 AA1
SA_DQ[16] SA_CLK[3] DDRA_CLK3 <12> SB_DQ[16] SB_CLK[3] DDRB_CLK3 <13>
DDR_A_D17 K5 AA3 DDR_B_D17 J8 AB1
DDR_A_D18 SA_DQ[17] SA_CLK#[3] DDRA_CLK3# <12> DDR_B_D18 SB_DQ[17] SB_CLK#[3] DDRB_CLK3# <13>
K1 SA_DQ[18] SA_CKE[3] W10 DDRA_CKE3 <12> K10 SB_DQ[18] SB_CKE[3] T10 DDRB_CKE3 <13>
DDR_A_D19 J1 DDR_B_D19 K9
DDR_A_D20 SA_DQ[19] DDR_B_D20 SB_DQ[19]
J5 SA_DQ[20] J9 SB_DQ[20]
DDR_A_D21 J4 DDR_B_D21 J10
DDR_A_D22 SA_DQ[21] DDR_B_D22 SB_DQ[21]
J2 SA_DQ[22] SA_CS#[0] AK3 DDRA_SCS0# <12> K8 SB_DQ[22] SB_CS#[0] AD3 DDRB_SCS0# <13>
DDR_A_D23 K2 AL3 DDR_B_D23 K7 AE3
SA_DQ[23] SA_CS#[1] DDRA_SCS1# <12> SB_DQ[23] SB_CS#[1] DDRB_SCS1# <13>
DDR_A_D24 M8 AG1 DDR_B_D24 M5 AD6
DDR_A_D25 SA_DQ[24] SA_CS#[2] DDRA_SCS2# <12> DDR_B_D25 SB_DQ[24] SB_CS#[2] DDRB_SCS2# <13>
N10 SA_DQ[25] SA_CS#[3] AH1 DDRA_SCS3# <12> N4 SB_DQ[25] SB_CS#[3] AE6 DDRB_SCS3# <13>
DDR_A_D26 N8 DDR_B_D26 N2
DDR_A_D27 SA_DQ[26] DDR_B_D27 SB_DQ[26]
N7 SA_DQ[27] N1 SB_DQ[27]
DDR_A_D28 M10 DDR_B_D28 M4
DDR_A_D29 SA_DQ[28] DDR_B_D29 SB_DQ[28]
M9 SA_DQ[29] SA_ODT[0] AH3 DDRA_ODT0 <12> N5 SB_DQ[29] SB_ODT[0] AE4 DDRB_ODT0 <13>
DDR SYSTEM MEMORY B
DDR_A_D30 N9 AG3 DDR_B_D30 M2 AD4
DDR SYSTEM MEMORY A
DDR_A_D31 SA_DQ[30] SA_ODT[1] DDRA_ODT1 <12> DDR_B_D31 SB_DQ[30] SB_ODT[1] DDRB_ODT1 <13>
M7 SA_DQ[31] SA_ODT[2] AG2 DDRA_ODT2 <12> M1 SB_DQ[31] SB_ODT[2] AD5 DDRB_ODT2 <13>
DDR_A_D32 AG6 AH2 DDR_B_D32 AM5 AE5
SA_DQ[32] SA_ODT[3] DDRA_ODT3 <12> SB_DQ[32] SB_ODT[3] DDRB_ODT3 <13>
DDR_A_D33 AG5 DDR_B_D33 AM6
DDR_A_D34 SA_DQ[33] DDR_B_D34 SB_DQ[33]
AK6 SA_DQ[34] AR3 SB_DQ[34]
DDR_A_D35 AK5 DDR_B_D35 AP3
C DDR_A_D36 SA_DQ[35] DDR_B_D36 SB_DQ[35] C
AH5 SA_DQ[36] DDR_A_DQS#[0..7] <12> AN3 SB_DQ[36] DDR_B_DQS#[0..7] <13>
DDR_A_D37 AH6 C4 DDR_A_DQS#0 DDR_B_D37 AN2 D7 DDR_B_DQS#0
DDR_A_D38 SA_DQ[37] SA_DQS#[0] SB_DQ[37] SB_DQS#[0]
AJ5 SA_DQ[38] SA_DQS#[1] G6 DDR_A_DQS#1 DDR_B_D38 AN1 SB_DQ[38] SB_DQS#[1] F3 DDR_B_DQS#1
DDR_A_D39 AJ6 J3 DDR_A_DQS#2 DDR_B_D39 AP2 K6 DDR_B_DQS#2
DDR_A_D40 SA_DQ[39] SA_DQS#[2] SB_DQ[39] SB_DQS#[2]
AJ8 SA_DQ[40] SA_DQS#[3] M6 DDR_A_DQS#3 DDR_B_D40 AP5 SB_DQ[40] SB_DQS#[3] N3 DDR_B_DQS#3
DDR_A_D41 AK8 AL6 DDR_A_DQS#4 DDR_B_D41 AN9 AN5 DDR_B_DQS#4
DDR_A_D42 SA_DQ[41] SA_DQS#[4] SB_DQ[41] SB_DQS#[4]
AJ9 SA_DQ[42] SA_DQS#[5] AM8 DDR_A_DQS#5 DDR_B_D42 AT5 SB_DQ[42] SB_DQS#[5] AP9 DDR_B_DQS#5
DDR_A_D43 AK9 AR12 DDR_A_DQS#6 DDR_B_D43 AT6 AK12 DDR_B_DQS#6
DDR_A_D44 SA_DQ[43] SA_DQS#[6] SB_DQ[43] SB_DQS#[6]
AH8 AM15 DDR_A_DQS#7 DDR_B_D44 AP6 AP15 DDR_B_DQS#7
DDR_A_D45 SA_DQ[44] SA_DQS#[7] DDR_B_D45 SB_DQ[44] SB_DQS#[7]
AH9 AN8
DDR_A_D46 SA_DQ[45] DDR_B_D46 SB_DQ[45]
AL9 AR6
DDR_A_D47 SA_DQ[46] DDR_B_D47 SB_DQ[46]
AL8 AR5
DDR_A_D48 SA_DQ[47] DDR_B_D48 SB_DQ[47]
AP11 DDR_A_DQS[0..7] <12> AR9 DDR_B_DQS[0..7] <13>
DDR_A_D49 SA_DQ[48] DDR_A_DQS0 DDR_B_D49 SB_DQ[48] DDR_B_DQS0
AN11 D4 AJ11 C7
DDR_A_D50 SA_DQ[49] SA_DQS[0] DDR_A_DQS1 DDR_B_D50 SB_DQ[49] SB_DQS[0] DDR_B_DQS1
AL12 F6 AT8 G3
DDR_A_D51 SA_DQ[50] SA_DQS[1] DDR_A_DQS2 DDR_B_D51 SB_DQ[50] SB_DQS[1] DDR_B_DQS2
AM12 K3 AT9 J6
DDR_A_D52 SA_DQ[51] SA_DQS[2] DDR_A_DQS3 DDR_B_D52 SB_DQ[51] SB_DQS[2] DDR_B_DQS3
AM11 N6 AH11 M3
DDR_A_D53 SA_DQ[52] SA_DQS[3] DDR_A_DQS4 DDR_B_D53 SB_DQ[52] SB_DQS[3] DDR_B_DQS4
AL11 AL5 AR8 AN6
DDR_A_D54 SA_DQ[53] SA_DQS[4] DDR_A_DQS5 DDR_B_D54 SB_DQ[53] SB_DQS[4] DDR_B_DQS5
AP12 AM9 AJ12 AP8
DDR_A_D55 SA_DQ[54] SA_DQS[5] DDR_A_DQS6 DDR_B_D55 SB_DQ[54] SB_DQS[5] DDR_B_DQS6
AN12 AR11 AH12 AK11
DDR_A_D56 SA_DQ[55] SA_DQS[6] DDR_A_DQS7 DDR_B_D56 SB_DQ[55] SB_DQS[6] DDR_B_DQS7
AJ14 AM14 AT11 AP14
DDR_A_D57 SA_DQ[56] SA_DQS[7] DDR_B_D57 SB_DQ[56] SB_DQS[7]
AH14 AN14
DDR_A_D58 SA_DQ[57] DDR_B_D58 SB_DQ[57]
AL15 AR14
DDR_A_D59 SA_DQ[58] DDR_B_D59 SB_DQ[58]
AK15 DDR_A_MA[0..15] <12> AT14
DDR_A_D60 SA_DQ[59] DDR_B_D60 SB_DQ[59]
AL14 AT12 DDR_B_MA[0..15] <13>
DDR_A_D61 SA_DQ[60] DDR_A_MA0 DDR_B_D61 SB_DQ[60] DDR_B_MA0
AK14 AD10 AN15 AA8
DDR_A_D62 SA_DQ[61] SA_MA[0] DDR_A_MA1 DDR_B_D62 SB_DQ[61] SB_MA[0] DDR_B_MA1
AJ15 W1 AR15 T7
DDR_A_D63 SA_DQ[62] SA_MA[1] DDR_A_MA2 DDR_B_D63 SB_DQ[62] SB_MA[1] DDR_B_MA2
AH15 W2 AT15 R7
SA_DQ[63] SA_MA[2] DDR_A_MA3 SB_DQ[63] SB_MA[2] DDR_B_MA3
W7 T6
SA_MA[3] DDR_A_MA4 SB_MA[3] DDR_B_MA4
V3 T2
SA_MA[4] DDR_A_MA5 SB_MA[4] DDR_B_MA5
V2 T4
SA_MA[5] DDR_A_MA6 SB_MA[5] DDR_B_MA6
W3 T3
B SA_MA[6] DDR_A_MA7 SB_MA[6] DDR_B_MA7 B
<12> DDR_A_BS0 AE10 W6 <13> DDR_B_BS0 AA9 R2
SA_BS[0] SA_MA[7] DDR_A_MA8 SB_BS[0] SB_MA[7] DDR_B_MA8
<12> DDR_A_BS1 AF10 V1 <13> DDR_B_BS1 AA7 T5
SA_BS[1] SA_MA[8] DDR_A_MA9 SB_BS[1] SB_MA[8] DDR_B_MA9
<12> DDR_A_BS2 V6 W5 <13> DDR_B_BS2 R6 R3
SA_BS[2] SA_MA[9] DDR_A_MA10 SB_BS[2] SB_MA[9] DDR_B_MA10
AD8 AB7
SA_MA[10] DDR_A_MA11 SB_MA[10] DDR_B_MA11
V4 R1
SA_MA[11] DDR_A_MA12 SB_MA[11] DDR_B_MA12
W4 T1
SA_MA[12] DDR_A_MA13 SB_MA[12] DDR_B_MA13
<12> DDR_A_CAS# AE8 AF8 <13> DDR_B_CAS# AA10 AB10
SA_CAS# SA_MA[13] DDR_A_MA14 SB_CAS# SB_MA[13] DDR_B_MA14
<12> DDR_A_RAS# AD9 V5 <13> DDR_B_RAS# AB8 R5
SA_RAS# SA_MA[14] DDR_A_MA15 SB_RAS# SB_MA[14] DDR_B_MA15
<12> DDR_A_WE# AF9 V7 <13> DDR_B_WE# AB9 R4
SA_WE# SA_MA[15] SB_WE# SB_MA[15]
Sandy Bridge_rPGA_Rev0p61 CONN@ Sandy Bridge_rPGA_Rev0p61
CONN@
+1.5V
@ R59
1
0_0402_5%
1 2 R60
1K_0402_5%
R61
2
1K_0402_5%
S
H_DRAMRST# 3 1 DDR3_DRAMRST#_R 1 2
<5> H_DRAMRST# SM_DRAMRST# <12,13>
Q2
2
BSS138_NL_SOT23-3
A R62 WHY ADD THE IK SERISE RESISTOR? A
G
2
4.99K_0402_1%
1
R63
0_0402_5%
1 2 DRAMRST_CNTRL
<30> DRAMRST_CNTRL_PCH
1
C42
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2010/12/03 Deciphered Date 2011/12/03 Title
0.047U_0402_16V4Z
2
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Sandy Bridge(3/6)-DDR III
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom 0.3
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
PBL80 LA-7441P M/B
Date: Monday, April 11, 2011 Sheet 7 of 59
5 4 3 2 1
5 4 3 2 1
Group1
+CPU_CORE
Material Note (+1.05VS_VCCP)
JCPUF POWER 2 x 330 µF
(3x 330 µF for 2012 capable designs)
94A 18A Top Socket Cavity 22U 0805 *7
Bottom Socket Cavity 22U 0805 *5 +1.05VS_VCCP
D D
AG35
VCC1
AG34 AH13
VCC2 VCCIO1
22U_0805_6.3V6M
22U_0805_6.3V6M
22U_0805_6.3V6M
22U_0805_6.3V6M
22U_0805_6.3V6M
22U_0805_6.3V6M
22U_0805_6.3V6M
22U_0805_6.3V6M
22U_0805_6.3V6M
22U_0805_6.3V6M
AG33 AH10 1 1 1 1 1 1 1 1 1 1
VCC3 VCCIO2
AG32 AG10
VCC4 VCCIO3 +1.05VS_VCCP
C43
C44
C45
C46
C47
C48
C49
C50
C51
C52
AG31 AC10
VCC5 VCCIO4
AG30 Y10
VCC6 VCCIO5 2 2 2 2 2 2 2 2 2 2
AG29 U10
VCC7 VCCIO6
AG28 P10 1 1
VCC8 VCCIO7 C83 C73
AG27 L10
VCC9 VCCIO8 + +
AG26 J14
VCC10 VCCIO9
AF35 VCC11 VCCIO10 J13
AF34 J12 @ 330U_2.5V_M_R17 @ 330U_2.5V_M_R17
VCC12 VCCIO11 2 2
22U_0805_6.3V6M
22U_0805_6.3V6M
AF33 VCC13 VCCIO12 J11 1 1
330U_D2_2V_Y
330U_D2_2V_Y
AF32 VCC14 VCCIO13 H14 1 1 1
C53
C54
AF31 VCC15 VCCIO14 H12
C62
C63
AF30 H11 + + + @ C64
VCC16 VCCIO15 2 2 330U_D2_2V_Y
AF29 VCC17 VCCIO16 G14
AF28 VCC18 VCCIO17 G13 reserve for test
2 2 2
PEG AND DDR
AF27 VCC19 VCCIO18 G12 please co-layout with C62,C63
AF26 VCC20 VCCIO19 F14
AD35 VCC21 VCCIO20 F13
AD34 VCC22 VCCIO21 F12
AD33 VCC23 VCCIO22 F11
AD32 VCC24 VCCIO23 E14
AD31 VCC25 VCCIO24 E12
AD30 VCC26 Cap quantity follow 439028_HR_PDDG_R1_51
AD29 VCC27 VCCIO25 E11
AD28 VCC28 VCCIO26 D14
AD27 VCC29 VCCIO27 D13
AD26 VCC30 VCCIO28 D12
AC35 VCC31 VCCIO29 D11
C C
AC34 VCC32 VCCIO30 C14
AC33 VCC33 VCCIO31 C13
AC32 VCC34 VCCIO32 C12
AC31 VCC35 VCCIO33 C11
AC30 VCC36 VCCIO34 B14
AC29 VCC37 VCCIO35 B12
AC28 VCC38 VCCIO36 A14
AC27 A13
VCC39 VCCIO37
AC26 A12
VCC40 VCCIO38
AA35 A11
VCC41 VCCIO39
AA34
VCC42
AA33 J23
VCC43 VCCIO40
AA32
VCC44
AA31
VCC45
AA30
VCC46
AA29
VCC47
AA28
VCC48
AA27
VCC49
AA26
VCC50
CORE SUPPLY
Y35
VCC51
Y34
VCC52
Y33
VCC53 +1.05VS_VCCP +1.05VS_VCCP
Y32
VCC54
Y31
VCC55
Y30
VCC56
1
Y29
VCC57 R65 R66
Y28
VCC58 130_0402_5% 75_0402_5%
Y27
VCC59 R67
Y26
VCC60 43_0402_1%
V35
2
VCC61
SVID
V34 AJ29 H_CPU_SVIDALRT# 1 2
VCC62 VIDALERT# H_CPU_SVIDCLK VR_SVID_ALRT# <55>
V33 AJ30 R68 1 2 0_0402_5%
B VCC63 VIDSCLK VR_SVID_CLK <55> B
V32 AJ28 H_CPU_SVIDDAT R69 1 2 0_0402_5%
VCC64 VIDSOUT VR_SVID_DAT <55>
V31
VCC65
V30
VCC66
V29
VCC67
V28
VCC68 Resistors
V27
V26
VCC69 close to CPU
VCC70
U35
VCC71
U34
VCC72
U33
VCC73
U32
VCC74 Close to CPU +CPU_CORE
U31
VCC75
U30
VCC76 VCCSENSE
U29 1 2
VCC77 R70 100_0402_1%
U28
VCC78 VSSSENSE
U27 1 2
VCC79 R71 100_0402_1%
U26
VCC80
R35
VCC81
R34
VCC82
R33
VCC83
R32
VCC84
R31
VCC85
R30
VCC86
R29
VCC87
SENSE LINES
R28 0_0402_5%
VCC88
R27 AJ35 VCCSENSE_R 1 R72 2 VCCSENSE
VCCSENSE <55>
VCC89 VCC_SENSE
R26 AJ34 VSSSENSE_R 1 2 VSSSENSE
VSSSENSE <55>
VCC90 VSS_SENSE R73 0_0402_5%
P35
VCC91
P34
VCC92
P33
VCC93
P32 B10 VCCIO_SENSE <52>
VCC94 VCCIO_SENSE
P31 VCC95 VSSIO_SENSE A10 1 R74 2
A A
P30 VCC96
P29 10_0402_5%
VCC97
P28 VCC98
P27 VCC99
P26 VCC100
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2010/12/03 Deciphered Date 2011/12/03 Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Sandy Bridge(4/6)-PWR
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
WWW.AliSaler.Com
Sandy Bridge_rPGA_Rev0p61 Custom 0.3
CONN@
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
PBL80 LA-7441P M/B
Date: Monday, April 11, 2011 Sheet 8 of 59
5 4 3 2 1
5 4 3 2 1
Material Note (GFXCORE)
2 x 330 µF on Bottom socket edge
Bottom Socket Cavity 22U 0805 *2
+GFX_CORE Bottom Socket Edge 22U 0805 *4
Top Socket Cavity 22U 0805 *2 POWER Group2
Top Socket Edge 22U 0805 *4 1 R131 2 +GFX_CORE
JCPUG 100_0402_1%
26A
SENSE
LINES
AT24 VAXG1 VAXG_SENSE AK35 VCC_AXG_SENSE <55>
330U_D2_2V_Y
C217
330U_D2_2V_Y
C225
1 1 AT23 AK34 VSS_AXG_SENSE <55>
VAXG2 VSSAXG_SENSE
AT21
+ + VAXG3
AT20
D VAXG4 +1.5V_CPU D
AT18 1 R129 2
VAXG5 100_0402_1%
AT17
2 2 VAXG6
AR24
VAXG7
1
AR23
VAXG8 R76
AR21
VAXG9 0_0402_5% R75
AR20
VAXG10
VREF
AR18
AR17
VAXG11
2 1 1K_0402_1% Follow DG V1.5 P.109
2
22U_0805_6.3V6M 22U_0805_6.3V6M 22U_0805_6.3V6M VAXG12 +V_SM_VREF_CNT +V_SM_VREF
AP24 AL1 2 3
VAXG13 SM_VREF
AP23
VAXG14 +V_SM_VREF should have 20
1
1 1 1 1 1 1 AP21 1
C284 C285 C286 C414 C415 C416 AP20
VAXG15
VAXG16
C65 @ mil trace width
AP18 Q3 R77
VAXG17 1 AP2302GN-HF_SOT23-3 1K_0402_1%
AP17 VAXG18
2 2 2 2 2 2 2 RUN_ON_CPU1.5VS3
AN24
2
VAXG19
AN23 VAXG20
22U_0805_6.3V6M 22U_0805_6.3V6M 22U_0805_6.3V6M AN21 VAXG21 0.1U_0402_16V4Z
AN20 VAXG22 +1.5V_CPU
DDR3 -1.5V RAILS
AN18 VAXG23
AN17 5A @ JP1
VAXG24
GRAPHICS
AM24 VAXG25 VDDQ1 AF7 1 1 2 2 +1.5V
22U_0805_6.3V6M 22U_0805_6.3V6M 22U_0805_6.3V6M AM23 AF4
VAXG26 VDDQ2
AM21 VAXG27 VDDQ3 AF1
JUMP_43X118
1 1 1 1 1 1 AM20 VAXG28 VDDQ4 AC7 1 Material Note (VDDQ)
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
330U_D2_2V_Y
C364 C365 C410 C412 C411 C413 AM18 AC4 1 1 1 1 1 1
VAXG29 VDDQ5 +
AM17 VAXG30 VDDQ6 AC1 Bottom Socket Edge
C66
C67
C68
C69
C70
C71
C72
AL24 VAXG31 VDDQ7 Y7 1 x 330 µF
2 2 2 2 2 2 AL23 Y4
VAXG32 VDDQ8 2 2 2 2 2 2 2 10U 0805 *6
AL21 VAXG33 VDDQ9 Y1
22U_0805_6.3V6M 22U_0805_6.3V6M 22U_0805_6.3V6M AL20 U7
VAXG34 VDDQ10
AL18 VAXG35 VDDQ11 U4
AL17 VAXG36 VDDQ12 U1
C C
AK24 VAXG37 VDDQ13 P7
AK23 VAXG38 VDDQ14 P4
AK21 VAXG39 VDDQ15 P1
AK20 VAXG40
AK18 VAXG41
AK17 VAXG42
AJ24 VAXG43
AJ23
VAXG44
AJ21
VAXG45
AJ20
VAXG46
AJ18
VAXG47
AJ17
VAXG48 +VCCSA
AH24 6A
SA RAIL
VAXG49
AH23
VAXG50 +VCCSA
AH21 M27
VAXG51 VCCSA1 R78
AH20 M26
VAXG52 VCCSA2 0_0402_5%
AH18 L26
VAXG53 VCCSA3
10U_0805_6.3V6M
10U_0805_6.3V6M
10U_0805_6.3V6M
AH17
VAXG54 VCCSA4
J26 1 1 1 1 2 VCCSA_SENSE Material Note (VCCSA)
330U_D2_2V_Y
C78
J25 1
VCCSA5
C74
C75
C76
VCCSA6
J24
+
1 x 330 µF
H26 Bottom Socket Cavity 10U 0805 *2
VCCSA7 2 2 2
H25
VCCSA8 Bottom Socket Edge 10U 0805 *1
2
1.8V RAIL
+1.8VS R124
0_0805_5%
1 2 +1.8VS_VCCPLL B6 H23
VCCPLL1 VCCSA_SENSE VCCSA_SENSE <54>
MISC
A6
VCCPLL2
330U_D2_2V_Y
C79
10U_0603_6.3V6M
C80
1U_0402_6.3V6K
C81
1U_0402_6.3V6K
C82
1 1 1 A2
VCCPLL3
1
+ C22 H_FC_C22
B @ FC_C22 B
C24 VCCSA_SEL <54>
2 2 VCCSA_VID1
1
2 2
R79 @ R80
Sandy Bridge_rPGA_Rev0p61 10K_0402_5% 0_0402_5%
Material Note (+1.8VS_VCCPLL) CONN@
2
1 x 330 µF
Bottom Socket Edge
1U 0402 *1
10U 0805 *1
+1.5V_CPU Source
+1.5V Q4 +1.5V_CPU
+VSB SI4634DY-T1-GE3_SO8
8 1
7 2
1
+3VALW 6 3
2
5
R81 R82
100K_0402_5% 470_0603_5%
4
1
R83
1
100K_0402_5% RUN_ON_CPU1.5VS3
3
A D A
2
R84 Q35B 1 2 RUN_ON_CPU1.5VS3#
0_0402_5% RUN_ON_CPU1.5VS3# 5 2N7002DW-T/R7_SOT363-6 G
<43> CPU1.5V_S3_GATE 1 2 C86 S Q6
3
6
R85 0.1U_0402_16V4Z 2N7002H 1N SOT23-3
4
@ R86 330K_0402_5% 2
2
0_0402_5% Q35A
1 2 2 2N7002DW-T/R7_SOT363-6
<43,46,50,52,54,57,58> SUSP# Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2010/12/03 Deciphered Date 2011/12/03 Title
1
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Sandy Bridge(4/6)-PWR
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom 0.3
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
PBL80 LA-7441P M/B
Date: Monday, April 11, 2011 Sheet 9 of 59
5 4 3 2 1
5 4 3 2 1
CFG Straps for Processor
CFG2
1
R87
1K_0402_1%
2
D D
JCPUE PEG Static Lane Reversal - CFG2 is for the 16x
RSVD28
L7 1: Normal Operation; Lane # definition matches
RSVD29
AG7 CFG2 socket pin map definition
CFG0 AK28 AE7
<5> CFG0 CFG1 CFG[0] RSVD30
T4 PAD @ AK29 AK2
CFG[1] RSVD31
T5 PAD @ CFG2 AL26 W8 0:Lane Reversed
T6
T7
PAD
PAD
@
@
CFG3
CFG4
AL27
AK26
CFG[2]
CFG[3]
CFG[4]
RSVD32
*
T3 PAD @ CFG5 AL29 AT26 CFG4
T8 PAD @ CFG6 CFG[5] RSVD33
AL30 CFG[6] RSVD34 AM33
1
T9 PAD @ CFG7 AM31 AJ27
T10 PAD @ CFG8 CFG[7] RSVD35 @
AM32 CFG[8]
T11 PAD @ CFG9 AM30 R88
T12 PAD @ CFG10 CFG[9] 1K_0402_1%
AM28 CFG[10]
T13 PAD @ CFG11 AM26
2
CFG12 CFG[11]
<5> CFG12 AN28 CFG[12]
CFG13 AN31 T8
<5> CFG13 CFG14 CFG[13] RSVD37
<5> CFG14 AN26 CFG[14] RSVD38 J16
CFG15 AM27 H16
<5> CFG15 CFG16 CFG[15] RSVD39
T14 PAD @ AK31 G16
T15 PAD @ CFG17 CFG[16] RSVD40
AN29 CFG[17]
Display Port Presence Strap
C C
AR35 1 : Disabled; No Physical Display Port
T16
T17
PAD
PAD
@
@
AJ31
AH31
RSVD1
RSVD2
RSVD41
RSVD42
RSVD43
AT34
AT33
CFG4 * attached to Embedded Display Port
T18 PAD @ AJ33 AP35
RSVD3 RSVD44
T19 PAD @ AH33 RSVD4 RSVD45 AR34 0 : Enabled; An external Display Port device is
connected to the Embedded Display Port
AJ26
RSVD5
RESERVED
B34 CFG6
CPU_RSVD6 RSVD46
B4 A33
CPU_RSVD7 RSVD6 RSVD47 CFG5
D1 A34
RSVD7 RSVD48
B35
RSVD49
1
C35
RSVD50
1
@ R91 @ R92
F25 1K_0402_1% 1K_0402_1%
R89 R90 RSVD8
F24
1K_0402_1% 1K_0402_1% RSVD9
F23
2
RSVD10
D24 AJ32
2
RSVD11 RSVD51
G25 AK32
RSVD12 RSVD52
G24
RSVD13
E23
RSVD14
D23
RSVD15 @ PAD T20
C30 AH27
RSVD16 RSVD53
A31
RSVD17
B30
RSVD18
B29
RSVD19 PCIE Port Bifurcation Straps
D30 AN35 CLK_RES_ITP <5,30>
RSVD20 RSVD54
B31 AM35 CLK_RES_ITP# <5,30>
RSVD21 RSVD55
A30 11: (Default) x16 - Device 1 functions 1 and 2 disabled
B
C29
RSVD22
RSVD23
CFG[6:5] *10: x8, x8 - Device 1 function 1 enabled ; function 2 B
J20
disabled
RSVD24
B18
RSVD25 RSVD56
AT2 01: Reserved - (Device 1 function 1 disabled ; function
A19 AT1 2 enabled)
RSVD26 RSVD57
AR1
RSVD58
00: x8,x4,x4 - Device 1 functions 1 and 2 enabled
J15
RSVD27
B1
KEY CFG7
1
@R93
@ R93
1K_0402_1%
Sandy Bridge_rPGA_Rev0p61
2
CONN@
PEG DEFER TRAINING
1: (Default) PEG Train immediately following xxRESETB
CFG7 de assertion
A
0: PEG Wait for BIOS for training A
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2010/12/03 Deciphered Date 2011/12/03 Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Sandy Bridge(5/6) Reserve
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
WWW.AliSaler.Com
Custom 0.3
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
PBL80 LA-7441P M/B
Date: Monday, April 11, 2011 Sheet 10 of 59
5 4 3 2 1
5 4 3 2 1
Material Note (+CPU_CORE)
4 x 330 µF
Top Socket Cavity 22U 0805 *8
JCPUH JCPUI Top Socket Edge 22U 0805 *8
Bottom Socket Cavity 10U 0805 *10
AT35 VSS1 VSS81 AJ22
AT32 VSS2 VSS82 AJ19
AT29 VSS3 VSS83 AJ16 T35 VSS161 VSS234 F22
AT27 AJ13 T34 F19 +CPU_CORE
VSS4 VSS84 VSS162 VSS235
AT25 AJ10 T33 E30
VSS5 VSS85 VSS163 VSS236
AT22 AJ7 T32 E27
VSS6 VSS86 VSS164 VSS237
AT19 AJ4 T31 E24
D VSS7 VSS87 VSS165 VSS238 D
AT16 AJ3 T30 E21
VSS8 VSS88 VSS166 VSS239
AT13 AJ2 T29 E18 1 1 1 1 1
VSS9 VSS89 VSS167 VSS240
10U_0805_10V7M
C87
10U_0805_10V7M
C88
10U_0805_10V7M
C89
10U_0805_10V7M
C90
10U_0805_10V7M
C91
AT10 AJ1 T28 E15
VSS10 VSS90 VSS168 VSS241
AT7 AH35 T27 E13
VSS11 VSS91 VSS169 VSS242
AT4 AH34 T26 E10
VSS12 VSS92 VSS170 VSS243 2 2 2 2 2
AT3 AH32 P9 E9
VSS13 VSS93 VSS171 VSS244
AR25 AH30 P8 E8
VSS14 VSS94 VSS172 VSS245
AR22 AH29 P6 E7
VSS15 VSS95 VSS173 VSS246
AR19 AH28 P5 E6
VSS16 VSS96 VSS174 VSS247
AR16 AH26 P3 E5
VSS17 VSS97 VSS175 VSS248
AR13 AH25 P2 E4
VSS18 VSS98 VSS176 VSS249
AR10 VSS19 VSS99 AH22 N35 VSS177 VSS250 E3 1 1 1 1 1
10U_0805_10V7M
C92
10U_0805_10V7M
C93
10U_0805_10V7M
C99
10U_0805_10V7M
C106
10U_0805_10V7M
C110
AR7 VSS20 VSS100 AH19 N34 VSS178 VSS251 E2
AR4 VSS21 VSS101 AH16 N33 VSS179 VSS252 E1
AR2 VSS22 VSS102 AH7 N32 VSS180 VSS253 D35
2 2 2 2 2
AP34 VSS23 VSS103 AH4 N31 VSS181 VSS254 D32
AP31 VSS24 VSS104 AG9 N30 VSS182 VSS255 D29
AP28 VSS25 VSS105 AG8 N29 VSS183 VSS256 D26
AP25 VSS26 VSS106 AG4 N28 VSS184 VSS257 D20
AP22 VSS27 VSS107 AF6 N27 VSS185 VSS258 D17
AP19 VSS28 VSS108 AF5 N26 VSS186 VSS259 C34
AP16 VSS29 VSS109 AF3 M34 VSS187 VSS260 C31
AP13 AF2 L33 C28 +CPU_CORE
VSS30 VSS110 VSS188 VSS261
AP10 VSS31 VSS111 AE35 L30 VSS189 VSS262 C27
AP7 VSS32 VSS112 AE34 L27 VSS190 VSS263 C25
AP4 VSS33 VSS113 AE33 L9 VSS191 VSS264 C23
AP1 VSS34 VSS114 AE32 L8 VSS192 VSS265 C10 1 1 1 1 1
22U_0805_6.3V6M
C98
22U_0805_6.3V6M
C94
22U_0805_6.3V6M
C100
22U_0805_6.3V6M
C101
22U_0805_6.3V6M
C102
AN30 VSS35 VSS115 AE31 L6 VSS193 VSS266 C1
AN27 VSS36 VSS116 AE30 L5 VSS194 VSS267 B22
AN25 AE29 L4 B19
C
AN22
AN19
VSS37
VSS38
VSS39
VSS VSS117
VSS118
VSS119
AE28
AE27
L3
L2
VSS195
VSS196
VSS197
VSS VSS268
VSS269
VSS270
B17
B15
2 2 2 2 2
C
AN16 VSS40 VSS120 AE26 L1 VSS198 VSS271 B13
AN13 VSS41 VSS121 AE9 K35 VSS199 VSS272 B11
AN10 VSS42 VSS122 AD7 K32 VSS200 VSS273 B9
AN7 VSS43 VSS123 AC9 K29 VSS201 VSS274 B8
AN4 VSS44 VSS124 AC8 K26 VSS202 VSS275 B7 1 1 1 1 1
22U_0805_6.3V6M
C103
22U_0805_6.3V6M
C104
22U_0805_6.3V6M
C105
22U_0805_6.3V6M
C95
22U_0805_6.3V6M
C107
AM29 VSS45 VSS125 AC6 J34 VSS203 VSS276 B5
AM25 VSS46 VSS126 AC5 J31 VSS204 VSS277 B3
AM22 AC3 H33 B2
VSS47 VSS127 VSS205 VSS278 2 2 2 2 2
AM19 AC2 H30 A35
VSS48 VSS128 VSS206 VSS279
AM16 AB35 H27 A32
VSS49 VSS129 VSS207 VSS280
AM13 AB34 H24 A29
VSS50 VSS130 VSS208 VSS281
AM10 AB33 H21 A26
VSS51 VSS131 VSS209 VSS282
AM7 AB32 H18 A23
VSS52 VSS132 VSS210 VSS283
AM4 AB31 H15 A20
VSS53 VSS133 VSS211 VSS284
AM3 AB30 H13 A3 1 1 1 1 1
VSS54 VSS134 VSS212 VSS285
22U_0805_6.3V6M
C108
22U_0805_6.3V6M
C109
22U_0805_6.3V6M
C96
22U_0805_6.3V6M
C111
22U_0805_6.3V6M
C112
AM2 AB29 H10
VSS55 VSS135 VSS213
AM1 AB28 H9
VSS56 VSS136 VSS214
AL34 AB27 H8
VSS57 VSS137 VSS215 2 2 2 2 2
AL31 AB26 H7
VSS58 VSS138 VSS216
AL28 Y9 H6
VSS59 VSS139 VSS217
AL25 Y8 H5
VSS60 VSS140 VSS218
AL22 Y6 H4
VSS61 VSS141 VSS219
AL19 Y5 H3
VSS62 VSS142 VSS220
AL16 Y3 H2
VSS63 VSS143 VSS221
AL13 Y2 H1
VSS64 VSS144 VSS222
22U_0805_6.3V6M
AL10 W35 G35 1
VSS65 VSS145 VSS223
C113
AL7 W34 G32
VSS66 VSS146 VSS224
AL4 W33 G29
VSS67 VSS147 VSS225
AL2 W32 G26
VSS68 VSS148 VSS226 2
AK33 W31 G23
VSS69 VSS149 VSS227
AK30 W30 G20
VSS70 VSS150 VSS228
AK27 W29 G17
B VSS71 VSS151 VSS229 B
AK25 W28 G11
VSS72 VSS152 VSS230 +CPU_CORE
AK22 W27 F34
VSS73 VSS153 VSS231
AK19 W26 F31
VSS74 VSS154 VSS232
AK16 U9 F29
VSS75 VSS155 VSS233
AK13 U8
VSS76 VSS156
AK10 U6
VSS77 VSS157
330U_D2_2V_Y
C219
330U_D2_2V_Y
C117
330U_D2_2V_Y
C118
330U_D2_2V_Y
C119
330U_D2_2V_Y
C120
AK7 U5 1 1 1 1 1
VSS78 VSS158
AK4 U3
VSS79 VSS159 + + + + +
AJ25 U2
VSS80 VSS160
2 2 2 2 2
Sandy Bridge_rPGA_Rev0p61 Sandy Bridge_rPGA_Rev0p61
CONN@ CONN@
A A
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2010/12/03 Deciphered Date 2011/12/03 Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Sandy Bridge(6/6)-GND
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom 0.3
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
PBL80 LA-7441P M/B
Date: Monday, April 11, 2011 Sheet 11 of 59
5 4 3 2 1
5 4 3 2 1
+1.5V +1.5V [email protected] +1.5V
JDDR1
Support SO DIMM X 4 +1.5V [email protected] +1.5V +1.5V
1
1K_0402_1%
+VREFA_DQ 1 2 JDDR2
3
VREF_DQ
VSS2
VSS1
DQ4 4 DDR_A_D4 Support 1066/1333MHz +VREFA_DQ 1 VREF_DQ VSS1 2
R94
0.1U_0402_10V6K
0.1U_0402_10V6K
0.1U_0402_10V6K
0.1U_0402_10V6K
DDR_A_D0 5 6 DDR_A_D5 3 4 DDR_A_D4
DQ0 DQ5 VSS2 DQ4
C202
C208
C216
C218
DDR_A_D1 7 8 DDR_A_D0 5 6 DDR_A_D5 1 1 1 1
+VREFA_DQ DQ1 VSS3 DDR_A_DQS#0 DDR_A_D1 DQ0 DQ5
9 10 7 8
2
VSS4 DQS#0 DDR_A_DQS0 DQ1 VSS3 DDR_A_DQS#0
11 DM0 DQS0 12 <7> DDR_A_D[0..63] 9 VSS4 DQS#0 10
13 14 11 12 DDR_A_DQS0
0.1U_0402_10V6K VSS5 VSS6 DM0 DQS0 2 2 2 2
2.2U_0603_6.3V4Z
DDR_A_D2 15 16 DDR_A_D6 13 14
C127 DQ2 DQ6 <7> DDR_A_DQS[0..7] VSS5 VSS6
C121
1 1 DDR_A_D3 17 18 DDR_A_D7 DDR_A_D2 15 16 DDR_A_D6
DQ3 DQ7 DQ2 DQ6
1
1K_0402_1%
19 20 DDR_A_D3 17 18 DDR_A_D7
VSS7 VSS8 <7> DDR_A_DQS#[0..7] DQ3 DQ7
DDR_A_D8 21 22 DDR_A_D12 19 20
DQ8 DQ12 VSS7 VSS8
R95
D DDR_A_D9 DDR_A_D13 DDR_A_D8 DDR_A_D12 D
23 24 <7> DDR_A_MA[0..15] 21 22
2 2 DQ9 DQ13 DDR_A_D9 DQ8 DQ12 DDR_A_D13
25
VSS9 VSS10
26 23
DQ9 DQ13
24 For EMI
DDR_A_DQS#1 27 28 25 26
2
DDR_A_DQS1 DQS#1 DM1 SM_DRAMRST# DDR_A_DQS#1 VSS9 VSS10
29 30 SM_DRAMRST# <7,13> 27 28
DQS1 RESET# DDR_A_DQS1 DQS#1 DM1 SM_DRAMRST#
31 32 29 30
DDR_A_D10 VSS11 VSS12 DDR_A_D14 DQS1 RESET#
33 34 31 32
DDR_A_D11 DQ10 DQ14 DDR_A_D15 DDR_A_D10 VSS11 VSS12 DDR_A_D14
35 36 33 34
DQ11 DQ15 DDR_A_D11 DQ10 DQ14 DDR_A_D15
37
VSS13 VSS14
38 Layout Note: 35
DQ11 DQ15
36
DDR_A_D16 39 40 DDR_A_D20 37 38
DDR_A_D17 DQ16 DQ20 DDR_A_D21
Place near JDIMMA DDR_A_D16 VSS13 VSS14 DDR_A_D20
41 42 39 40
DQ17 DQ21 +1.5V DDR_A_D17 DQ16 DQ20 DDR_A_D21
43 44 41 42
DDR_A_DQS#2 VSS15 VSS16 DQ17 DQ21
45 DQS#2 DM2 46 43 VSS15 VSS16 44
DDR_A_DQS2 47 48 DDR_A_DQS#2 45 46
DQS2 VSS17 DQS#2 DM2
330U_B2_2.5VM_R15M
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
49 50 DDR_A_D22 DDR_A_DQS2 47 48
VSS18 DQ22 DQS2 VSS17
C130
47P_0402_50V8J
DDR_A_D18 51 52 DDR_A_D23 1 49 50 DDR_A_D22
DQ18 DQ23 VSS18 DQ22
C128
C122
C129
C123
C124
C125
C126
DDR_A_D19 53 54 1 1 1 1 1 1 DDR_A_D18 51 52 DDR_A_D23
DQ19 VSS19 DQ18 DQ23
1
55 56 DDR_A_D28 + DDR_A_D19 53 54
DDR_A_D24 VSS20 DQ28 DDR_A_D29 DQ19 VSS19 DDR_A_D28
57 DQ24 DQ29 58 55 VSS20 DQ28 56
DDR_A_D25 59 60 DDR_A_D24 57 58 DDR_A_D29
2
DQ25 VSS21 DDR_A_DQS#3 2 2 2 2 2 2 2 DDR_A_D25 DQ24 DQ29
61 VSS22 DQS#3 62 59 DQ25 VSS21 60
63 64 DDR_A_DQS3 61 62 DDR_A_DQS#3
DM3 DQS3 VSS22 DQS#3 DDR_A_DQS3
65 VSS23 VSS24 66 63 DM3 DQS3 64
DDR_A_D26 67 68 DDR_A_D30 65 66
DDR_A_D27 DQ26 DQ30 DDR_A_D31 DDR_A_D26 VSS23 VSS24 DDR_A_D30
69 DQ27 DQ31 70 67 DQ26 DQ30 68
71 72 DDR_A_D27 69 70 DDR_A_D31
VSS25 VSS26 DQ27 DQ31
71 VSS25 VSS26 72
<7> DDRA_CKE0 DDRA_CKE0 73 74 DDRA_CKE1
CKE0 CKE1 DDRA_CKE1 <7>
75 76 DDRA_CKE2 73 74 DDRA_CKE3
VDD1 VDD2 <7> DDRA_CKE2 CKE0 CKE1 DDRA_CKE3 <7>
77 78 DDR_A_MA15 75 76
DDR_A_BS2 NC1 A15 DDR_A_MA14 VDD1 VDD2 DDR_A_MA15
<7> DDR_A_BS2 79 BA2 A14 80 77 NC1 A15 78
C DDR_A_BS2 DDR_A_MA14 C
81 VDD3 VDD4 82 79 BA2 A14 80
DDR_A_MA12 83 84 DDR_A_MA11 81 82
DDR_A_MA9 A12/BC# A11 DDR_A_MA7 DDR_A_MA12 VDD3 VDD4 DDR_A_MA11
85 A9 A7 86 83 A12/BC# A11 84
87 88 DDR_A_MA9 85 86 DDR_A_MA7
DDR_A_MA8 VDD5 VDD6 DDR_A_MA6 A9 A7
89 A8 A6 90 87 VDD5 VDD6 88
DDR_A_MA5 91 92 DDR_A_MA4 DDR_A_MA8 89 90 DDR_A_MA6
A5 A4 DDR_A_MA5 A8 A6 DDR_A_MA4
93 VDD7 VDD8 94 91 A5 A4 92
DDR_A_MA3 95 96 DDR_A_MA2 93 94
DDR_A_MA1 A3 A2 DDR_A_MA0 DDR_A_MA3 VDD7 VDD8 DDR_A_MA2
97 98 95 96
A1 A0 DDR_A_MA1 A3 A2 DDR_A_MA0
99 100 97 98
DDRA_CLK0 VDD9 VDD10 DDRA_CLK1 A1 A0
<7> DDRA_CLK0 101 102 DDRA_CLK1 <7> 99 100
DDRA_CLK0# CK0 CK1 DDRA_CLK1# DDRA_CLK2 VDD9 VDD10 DDRA_CLK3
<7> DDRA_CLK0# 103 104 DDRA_CLK1# <7> <7> DDRA_CLK2 101 102 DDRA_CLK3 <7>
CK0# CK1# +1.5V DDRA_CLK2# CK0 CK1 DDRA_CLK3#
105 106 <7> DDRA_CLK2# 103 104 DDRA_CLK3# <7>
DDR_A_MA10 VDD11 VDD12 DDR_A_BS1 CK0# CK1#
107 108 DDR_A_BS1 <7> 105 106
DDR_A_BS0 A10/AP BA1 DDR_A_RAS# DDR_A_MA10 VDD11 VDD12 DDR_A_BS1
<7> DDR_A_BS0 109 110 DDR_A_RAS# <7> 107 108
BA0 RAS# A10/AP BA1
1
111 112 DDR_A_BS0 109 110 DDR_A_RAS#
DDR_A_WE# VDD13 VDD14 DDRA_SCS0# R96 BA0 RAS#
<7> DDR_A_WE# 113 114 DDRA_SCS0# <7> 111 112
DDR_A_CAS# WE# S0# DDRA_ODT0 1K_0402_1% DDR_A_WE# VDD13 VDD14 DDRA_SCS2#
<7> DDR_A_CAS# 115 116 DDRA_ODT0 <7> 113 114 DDRA_SCS2# <7>
CAS# ODT0 DDR_A_CAS# WE# S0# DDRA_ODT2
117 118 115 116 DDRA_ODT2 <7>
DDR_A_MA13 VDD15 VDD16 DDRA_ODT1 CAS# ODT0
119 120 117 118
2
DDRA_SCS1# A13 ODT1 DDRA_ODT1 <7> DDR_A_MA13 VDD15 VDD16 DDRA_ODT3
<7> DDRA_SCS1# 121 122 119 120 DDRA_ODT3 <7>
S1# NC2 DDRA_SCS3# A13 ODT1
123 124 <7> DDRA_SCS3# 121 122
VDD17 VDD18 +VREF_CA S1# NC2 +VREF_CA
125 126 123 124
NCTEST VREF_CA VDD17 VDD18
127 128 125 126
VSS27 VSS28 NCTEST VREF_CA
0.1U_0402_10V6K
2.2U_0603_6.3V4Z
DDR_A_D32 129 130 DDR_A_D36 127 128
DQ32 DQ36 VSS27 VSS28
1
C131
C132
0.1U_0402_10V6K
2.2U_0603_6.3V4Z
DDR_A_D33 131 132 DDR_A_D37 1 1 DDR_A_D32 129 130 DDR_A_D36
DQ33 DQ37 DQ32 DQ36
C133
C134
133 134 DDR_A_D33 131 132 DDR_A_D37 1 1
DDR_A_DQS#4 VSS29 VSS30 R97 DQ33 DQ37
135 136 133 134
DDR_A_DQS4 DQS#4 DM4 1K_0402_1% DDR_A_DQS#4 VSS29 VSS30
137 138 135 136
DQS4 VSS31 DDR_A_D38 2 2 DDR_A_DQS4 DQS#4 DM4
139 140 137 138
2
DDR_A_D34 VSS32 DQ38 DDR_A_D39 DQS4 VSS31 DDR_A_D38 2 2
141 142 139 140
DDR_A_D35 DQ34 DQ39 DDR_A_D34 VSS32 DQ38 DDR_A_D39
143 144 141 142
B DQ35 VSS33 DDR_A_D44 DDR_A_D35 DQ34 DQ39 B
Layout Note: 145
VSS34 DQ44
146 143
DQ35 VSS33
144
Place near DDR_A_D40 147 148 DDR_A_D45 145 146 DDR_A_D44
DDR_A_D41 DQ40 DQ45 DDR_A_D40 VSS34 DQ44 DDR_A_D45
149 150 147 148
JDIMMA1.203,204 DQ41 VSS35 DDR_A_DQS#5 DDR_A_D41 DQ40 DQ45
151 152 149 150
VSS36 DQS#5 DDR_A_DQS5 DQ41 VSS35 DDR_A_DQS#5
153
DM5 DQS5
154 Layout Note: Place these 4 Caps near 151
VSS36 DQS#5
152
155 156 153 154 DDR_A_DQS5
DDR_A_D42 VSS37 VSS38 DDR_A_D46
Command and Control signals of JDIMMA DM5 DQS5
+0.75VS 157
DQ42 DQ46
158 155
VSS37 VSS38
156 Layout Note:
DDR_A_D43 159 160 DDR_A_D47 DDR_A_D42 157 158 DDR_A_D46 Place near
DQ43 DQ47 +1.5V DDR_A_D43 DQ42 DQ46 DDR_A_D47
161 162 159 160 JDIMMA2.203,204
DDR_A_D48 VSS39 VSS40 DDR_A_D52 DQ43 DQ47
163 164 161 162
DDR_A_D49 DQ48 DQ52 DDR_A_D53 DDR_A_D48 VSS39 VSS40 DDR_A_D52
165 166 163 164
DQ49 DQ53 DQ48 DQ52
1U_0402_6.3V6K
C135
0.1U_0402_10V6K
167 168 DDR_A_D49 165 166 DDR_A_D53
VSS41 VSS42 DQ49 DQ53
1U_0402_6.3V6K
C136
0.1U_0402_10V6K
0.1U_0402_10V6K
0.1U_0402_10V6K
C140
1 DDR_A_DQS#6 169 170 1 167 168 +0.75VS
DQS#6 DM6 VSS41 VSS42
C137
C138
C139
1 DDR_A_DQS6 171 172 1 1 1 DDR_A_DQS#6 169 170
DQS6 VSS43 DDR_A_D54 DDR_A_DQS6 DQS#6 DM6
173 174 171 172
DDR_A_D50 VSS44 DQ54 DDR_A_D55 DQS6 VSS43 DDR_A_D54
175 176 173 174
2 DDR_A_D51 DQ50 DQ55 2 DDR_A_D50 VSS44 DQ54 DDR_A_D55
177 178 175 176
2 DQ51 VSS45 2 2 2 DQ50 DQ55
1U_0402_6.3V6K
C141
1U_0402_6.3V6K
C142
179 180 DDR_A_D60 DDR_A_D51 177 178
DDR_A_D56 VSS46 DQ60 DDR_A_D61 DQ51 VSS45 DDR_A_D60
181 182 179 180 1 1
DDR_A_D57 DQ56 DQ61 DDR_A_D56 VSS46 DQ60 DDR_A_D61
183 184 181 182
DQ57 VSS47 DDR_A_DQS#7 DDR_A_D57 DQ56 DQ61
185 186 183 184
VSS48 DQS#7 DDR_A_DQS7 DQ57 VSS47 DDR_A_DQS#7
187 188 185 186
DM7 DQS7 VSS48 DQS#7 DDR_A_DQS7 2 2
189 190 187 188
DDR_A_D58 VSS49 VSS50 DDR_A_D62 DM7 DQS7
191 192 189 190
DDR_A_D59 DQ58 DQ62 DDR_A_D63 DDR_A_D58 VSS49 VSS50 DDR_A_D62
193 194 191 192
DQ59 DQ63 DDR_A_D59 DQ58 DQ62 DDR_A_D63
195 196 193 194
VSS51 VSS52 DQ59 DQ63
197 198 195 196
SA0 EVENT# PM_SMBDATA 10K_0402_5% VSS51 VSS52
+3VS 199 200 PM_SMBDATA <13,30,39> 1 2 R98 197 198
VDDSPD SDA SA0 EVENT#
2.2U_0603_6.3V4Z
0.1U_0402_10V6K
201 202 PM_SMBCLK 199 200 PM_SMBDATA
SA1 SCL PM_SMBCLK <13,30,39> +3VS VDDSPD SDA
C143
C144
1 1 203 204 201 202 PM_SMBCLK
VTT1 VTT2 +0.75VS SA1 SCL
1
1
10K_0402_5%
R99
10K_0402_5%
R100
2.2U_0603_6.3V4Z
0.1U_0402_10V6K
1 1 203 204 +0.75VS
VTT1 VTT2
1 10K_0402_5%
R101
205 206 [email protected]
G1 G2 [email protected]
C145
C146
A A
205 G1 G2 206
2 2 TYCO_2-2013289-1
2 2
Reverse:4mm
@ TYCO_2-2013287-1
<Address: SA1:SA0=01>
2
2
TOP
Standard:5.2mm
<Address: SA1:SA0=00> Security Classification Compal Secret Data Compal Electronics, Inc.
BOT Issued Date 2010/12/03 Deciphered Date 2011/12/03 Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
DDRIII-DIMMA
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
WWW.AliSaler.Com
Custom 0.3
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
PBL80 LA-7441P M/B
Date: Monday, April 11, 2011 Sheet 12 of 59
5 4 3 2 1
5 4 3 2 1
+1.5V
+1.5V [email protected] +1.5V
<7> DDR_B_DQS#[0..7]
1 +1.5V [email protected] +1.5V
1K_0402_1%
JDDR4
+VREFB_DQ 1 2
<7> DDR_B_D[0..63] VREF_DQ VSS1
R102
JDDR3 3 4 DDR_B_D4
+VREFB_DQ DDR_B_D0 VSS2 DQ4 DDR_B_D5
1 VREF_DQ VSS1 2 <7> DDR_B_DQS[0..7] 5 DQ0 DQ5 6
+VREFB_DQ 3 4 DDR_B_D4 DDR_B_D1 7 8
2
DDR_B_D0 VSS2 DQ4 DDR_B_D5 DQ1 VSS3 DDR_B_DQS#0
5 DQ0 DQ5 6 <7> DDR_B_MA[0..15] 9 VSS4 DQS#0 10
DDR_B_D1 7 8 11 12 DDR_B_DQS0
DQ1 VSS3 DM0 DQS0
0.1U_0402_10V6K
2.2U_0603_6.3V4Z
9 10 DDR_B_DQS#0 13 14
VSS4 DQS#0 VSS5 VSS6
C147
C148
1 1 11 12 DDR_B_DQS0 DDR_B_D2 15 16 DDR_B_D6
DM0 DQS0 DQ2 DQ6
1
1K_0402_1%
13 14 DDR_B_D3 17 18 DDR_B_D7
DDR_B_D2 VSS5 VSS6 DDR_B_D6 DQ3 DQ7
15 16 19 20
DQ2 DQ6 VSS7 VSS8
R103
D DDR_B_D3 DDR_B_D7 DDR_B_D8 DDR_B_D12 D
17 18 21 22
2 2 DQ3 DQ7 DDR_B_D9 DQ8 DQ12 DDR_B_D13
19 20 23 24
DDR_B_D8 VSS7 VSS8 DDR_B_D12 DQ9 DQ13
21 22 25 26
2
DDR_B_D9 DQ8 DQ12 DDR_B_D13 DDR_B_DQS#1 VSS9 VSS10
23 24 27 28
DQ9 DQ13 DDR_B_DQS1 DQS#1 DM1 SM_DRAMRST#
25 26 29 30
DDR_B_DQS#1 VSS9 VSS10 DQS1 RESET#
27 28 31 32
DDR_B_DQS1 DQS#1 DM1 SM_DRAMRST# DDR_B_D10 VSS11 VSS12 DDR_B_D14
29 30 SM_DRAMRST# <7,12> 33 34
DQS1 RESET# DDR_B_D11 DQ10 DQ14 DDR_B_D15
31 32 35 36
DDR_B_D10 VSS11 VSS12 DDR_B_D14 DQ11 DQ15
33 34 37 38
DDR_B_D11 DQ10 DQ14 DDR_B_D15 DDR_B_D16 VSS13 VSS14 DDR_B_D20
35 36 39 40
DQ11 DQ15 DDR_B_D17 DQ16 DQ20 DDR_B_D21
37
VSS13 VSS14
38 Layout Note: 41
DQ17 DQ21
42
DDR_B_D16 39 40 DDR_B_D20 43 44
DDR_B_D17 DQ16 DQ20 DDR_B_D21
Place near JDIMMB DDR_B_DQS#2 VSS15 VSS16
41 DQ17 DQ21 42 45 DQS#2 DM2 46
43 44 +1.5V DDR_B_DQS2 47 48
DDR_B_DQS#2 VSS15 VSS16 DQS2 VSS17 DDR_B_D22
45 DQS#2 DM2 46 49 VSS18 DQ22 50
DDR_B_DQS2 47 48 DDR_B_D18 51 52 DDR_B_D23
DQS2 VSS17 DQ18 DQ23
330U_B2_2.5VM_R15M
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
49 50 DDR_B_D22 DDR_B_D19 53 54
VSS18 DQ22 DQ19 VSS19
C156
47P_0402_50V8J
DDR_B_D18 51 52 DDR_B_D23 1 55 56 DDR_B_D28
DQ18 DQ23 VSS20 DQ28
C149
C150
C151
C152
C153
C154
C155
DDR_B_D19 53 54 1 1 1 1 1 1 DDR_B_D24 57 58 DDR_B_D29
DQ19 VSS19 DQ24 DQ29
1
55 56 DDR_B_D28 + DDR_B_D25 59 60
DDR_B_D24 VSS20 DQ28 DDR_B_D29 DQ25 VSS21 DDR_B_DQS#3
57 DQ24 DQ29 58 61 VSS22 DQS#3 62
DDR_B_D25 59 60 63 64 DDR_B_DQS3
2
DQ25 VSS21 DDR_B_DQS#3 2 2 2 2 2 2 2 DM3 DQS3
61 VSS22 DQS#3 62 65 VSS23 VSS24 66
63 64 DDR_B_DQS3 DDR_B_D26 67 68 DDR_B_D30
DM3 DQS3 DDR_B_D27 DQ26 DQ30 DDR_B_D31
65 VSS23 VSS24 66 69 DQ27 DQ31 70
DDR_B_D26 67 68 DDR_B_D30 71 72
DDR_B_D27 DQ26 DQ30 DDR_B_D31 VSS25 VSS26
69 DQ27 DQ31 70
71 VSS25 VSS26 72
DDRB_CKE2 73 74 DDRB_CKE3
<7> DDRB_CKE2 CKE0 CKE1 DDRB_CKE3 <7>
75 VDD1 VDD2 76
DDRB_CKE0 73 74 DDRB_CKE1 77 78 DDR_B_MA15
C <7> DDRB_CKE0 CKE0 CKE1 DDRB_CKE1 <7> NC1 A15 C
75 76 DDR_B_BS2 79 80 DDR_B_MA14
VDD1 VDD2 DDR_B_MA15 BA2 A14
77 NC1 A15 78 81 VDD3 VDD4 82
<7> DDR_B_BS2 DDR_B_BS2 79 80 DDR_B_MA14 DDR_B_MA12 83 84 DDR_B_MA11
BA2 A14 DDR_B_MA9 A12/BC# A11 DDR_B_MA7
81 VDD3 VDD4 82 85 A9 A7 86
DDR_B_MA12 83 84 DDR_B_MA11 87 88
DDR_B_MA9 A12/BC# A11 DDR_B_MA7 DDR_B_MA8 VDD5 VDD6 DDR_B_MA6
85 A9 A7 86 89 A8 A6 90
87 88 DDR_B_MA5 91 92 DDR_B_MA4
DDR_B_MA8 VDD5 VDD6 DDR_B_MA6 A5 A4
89 90 93 94
DDR_B_MA5 A8 A6 DDR_B_MA4 DDR_B_MA3 VDD7 VDD8 DDR_B_MA2
91 92 95 96
A5 A4 DDR_B_MA1 A3 A2 DDR_B_MA0
93 94 97 98
DDR_B_MA3 VDD7 VDD8 DDR_B_MA2 A1 A0
95 96 99 100
DDR_B_MA1 A3 A2 DDR_B_MA0 DDRB_CLK2 VDD9 VDD10 DDRB_CLK3
97 98 <7> DDRB_CLK2 101 102 DDRB_CLK3 <7>
A1 A0 DDRB_CLK2# CK0 CK1 DDRB_CLK3#
99 100 <7> DDRB_CLK2# 103 104 DDRB_CLK3# <7>
DDRB_CLK0 VDD9 VDD10 DDRB_CLK1 CK0# CK1#
<7> DDRB_CLK0 101 102 DDRB_CLK1 <7> 105 106
DDRB_CLK0# CK0 CK1 DDRB_CLK1# DDR_B_MA10 VDD11 VDD12 DDR_B_BS1
<7> DDRB_CLK0# 103 104 DDRB_CLK1# <7> 107 108
CK0# CK1# +1.5V DDR_B_BS0 A10/AP BA1 DDR_B_RAS#
105 106 109 110
DDR_B_MA10 VDD11 VDD12 DDR_B_BS1 BA0 RAS#
107 108 DDR_B_BS1 <7> 111 112
DDR_B_BS0 A10/AP BA1 DDR_B_RAS# DDR_B_WE# VDD13 VDD14 DDRB_SCS2#
<7> DDR_B_BS0 109 110 DDR_B_RAS# <7> 113 114 DDRB_SCS2# <7>
BA0 RAS# WE# S0#
1
111 112 DDR_B_CAS# 115 116 DDRB_ODT2
DDR_B_WE# VDD13 VDD14 DDRB_SCS0# CAS# ODT0 DDRB_ODT2 <7>
<7> DDR_B_WE# 113 114 R104 117 118
DDR_B_CAS# WE# S0# DDRB_ODT0 DDRB_SCS0# <7> DDR_B_MA13 VDD15 VDD16 DDRB_ODT3
<7> DDR_B_CAS# 115 116 1K_0402_1% 119 120
CAS# ODT0 DDRB_ODT0 <7> A13 ODT1 DDRB_ODT3 <7>
117 118 DDRB_SCS3# 121 122
VDD15 VDD16 <7> DDRB_SCS3# S1# NC2 +VREF_CB
DDR_B_MA13 119 120 DDRB_ODT1 123 124
2
A13 ODT1 DDRB_ODT1 <7> VDD17 VDD18
<7> DDRB_SCS1# DDRB_SCS1# 121 122 125 126 +VREF_CB
S1# NC2 NCTEST VREF_CA
123 124 127 128
VDD17 VDD18 VSS27 VSS28
0.1U_0402_10V6K
2.2U_0603_6.3V4Z
125 126 +VREF_CB DDR_B_D32 129 130 DDR_B_D36
NCTEST VREF_CA DQ32 DQ36
C159
C160
127 128 DDR_B_D33 131 132 DDR_B_D37 1 1
VSS27 VSS28 DQ33 DQ37
0.1U_0402_10V6K
2.2U_0603_6.3V4Z
DDR_B_D32 129 130 DDR_B_D36 133 134
DQ32 DQ36 VSS29 VSS30
1
C157
C158
DDR_B_D33 131 132 DDR_B_D37 1 1 DDR_B_DQS#4 135 136
DQ33 DQ37 DDR_B_DQS4 DQS#4 DM4
133 134 137 138
DDR_B_DQS#4 VSS29 VSS30 R105 DQS4 VSS31 DDR_B_D38 2 2
135 136 139 140
DDR_B_DQS4 DQS#4 DM4 1K_0402_1% DDR_B_D34 VSS32 DQ38 DDR_B_D39
137 138 141 142
B DQS4 VSS31 DDR_B_D38 2 2 DDR_B_D35 DQ34 DQ39 B
139 140 143 144
2
DDR_B_D34 VSS32 DQ38 DDR_B_D39 DQ35 VSS33 DDR_B_D44
141 142 145 146
DDR_B_D35 DQ34 DQ39 DDR_B_D40 VSS34 DQ44 DDR_B_D45
Layout Note: 143
DQ35 VSS33
144 147
DQ40 DQ45
148
Place near 145 146 DDR_B_D44 DDR_B_D41 149 150
DDR_B_D40 VSS34 DQ44 DDR_B_D45 DQ41 VSS35 DDR_B_DQS#5
JDIMMB1.203,204 147 148 151 152
DDR_B_D41 DQ40 DQ45 VSS36 DQS#5 DDR_B_DQS5
149
DQ41 VSS35
150 Layout Note: Place these 4 Caps near 153
DM5 DQS5
154 Layout Note:
151 152 DDR_B_DQS#5 155 156 Place near
VSS36 DQS#5 DDR_B_DQS5
Command and Control signals of JDIMMB DDR_B_D42 VSS37 VSS38 DDR_B_D46
153 154 157 158 JDIMMB2.203,204
+0.75VS DM5 DQS5 DDR_B_D43 DQ42 DQ46 DDR_B_D47
155 156 159 160
DDR_B_D42 VSS37 VSS38 DDR_B_D46 +1.5V DQ43 DQ47
157 158 161 162
DDR_B_D43 DQ42 DQ46 DDR_B_D47 DDR_B_D48 VSS39 VSS40 DDR_B_D52
159 160 163 164
DQ43 DQ47 DDR_B_D49 DQ48 DQ52 DDR_B_D53 +0.75VS
161 162 165 166
DDR_B_D48 VSS39 VSS40 DDR_B_D52 DQ49 DQ53
163 164 167 168
DQ48 DQ52 VSS41 VSS42
1U_0402_6.3V6K
C161
1U_0402_6.3V6K
C162
0.1U_0402_10V6K
0.1U_0402_10V6K
0.1U_0402_10V6K
0.1U_0402_10V6K
DDR_B_D49 165 166 DDR_B_D53 DDR_B_DQS#6 169 170
DQ49 DQ53 DQS#6 DM6
C163
C164
C165
C166
1 1 167 168 1 1 1 1 DDR_B_DQS6 171 172
DDR_B_DQS#6 VSS41 VSS42 DQS6 VSS43 DDR_B_D54
169 170 173 174
DQS#6 DM6 VSS44 DQ54
1U_0402_6.3V6K
C167
1U_0402_6.3V6K
C168
DDR_B_DQS6 171 172 DDR_B_D50 175 176 DDR_B_D55
DQS6 VSS43 DDR_B_D54 DDR_B_D51 DQ50 DQ55
173 174 177 178 1 1
2 2 DDR_B_D50 VSS44 DQ54 DDR_B_D55 2 2 2 2 DQ51 VSS45 DDR_B_D60
175 176 179 180
DDR_B_D51 DQ50 DQ55 DDR_B_D56 VSS46 DQ60 DDR_B_D61
177 178 181 182
DQ51 VSS45 DDR_B_D60 DDR_B_D57 DQ56 DQ61
179 180 183 184
DDR_B_D56 VSS46 DQ60 DDR_B_D61 DQ57 VSS47 DDR_B_DQS#7 2 2
181 182 185 186
DDR_B_D57 DQ56 DQ61 VSS48 DQS#7 DDR_B_DQS7
183 184 187 188
DQ57 VSS47 DDR_B_DQS#7 DM7 DQS7
185 186 189 190
VSS48 DQS#7 DDR_B_DQS7 DDR_B_D58 VSS49 VSS50 DDR_B_D62
187 188 191 192
DM7 DQS7 DDR_B_D59 DQ58 DQ62 DDR_B_D63
189 190 193 194
DDR_B_D58 VSS49 VSS50 DDR_B_D62 DQ59 DQ63
191 192 195 196
DDR_B_D59 DQ58 DQ62 DDR_B_D63 10K_0402_5% R106 2 VSS51 VSS52
193 194 1 197 198
DQ59 DQ63 SA0 EVENT# PM_SMBDATA
1 R107 2 195
VSS51 VSS52
196 +3VS 199
VDDSPD SDA
200
10K_0402_5% 197 198 1 2 201 202 PM_SMBCLK
SA0 EVENT# SA1 SCL
2.2U_0603_6.3V4Z
C169
0.1U_0402_10V6K
C170
199 200 PM_SMBDATA 1 1 R108 10K_0402_5% 203 204
+3VS VDDSPD SDA PM_SMBDATA <12,30,39> VTT1 VTT2 +0.75VS
201 202 PM_SMBCLK
SA1 SCL PM_SMBCLK <12,30,39> [email protected]
2.2U_0603_6.3V4Z
C171
0.1U_0402_10V6K
C172
A A
1 1 1 2 203 204 +0.75VS 205 206
VTT1 VTT2 G1 G2
R109 10K_0402_5%
2 2
Reverse:8mm
205 206 [email protected]
G1 G2 TYCO 2-1932323-1 <Address: SA1:SA0=11>
2 2 TYCO_2-2013310-1 @ TOP
@
Security Classification Compal Secret Data Compal Electronics, Inc.
Standard:9.2mm Issued Date 2010/12/03 Deciphered Date 2011/12/03 Title
<Address: SA1:SA0=10>
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
DDRIII-DIMMB
BOT AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
0.3
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
PBL80 LA-7441P M/B
Date: Monday, April 11, 2011 Sheet 13 of 59
5 4 3 2 1
5 4 3 2 1
UV1A
PCIE_GTX_C_CRX_P[0..15]
PCIE_CTX_C_GRX_P0 <6> PCIE_GTX_C_CRX_P[0..15]
AP17 Part 1 of 7 K1
PCIE_CTX_C_GRX_N0 PEX_RX0 GPIO0 VGA_GPIO1
AN17 PEX_RX0_N GPIO1 K2
N12PGS@ PCIE_CTX_C_GRX_P1 AN19 K3 PCIE_GTX_C_CRX_N[0..15]
PCIE_CTX_C_GRX_N1 PEX_RX1 GPIO2 <6> PCIE_GTX_C_CRX_N[0..15]
UV1 AP19 H3
N12P-GS-A1_BGA_973P PCIE_CTX_C_GRX_P2 PEX_RX1_N GPIO3
AR19 PEX_RX2 GPIO4 H2
PCIE_CTX_C_GRX_N2 AR20 H1 GPU_VID0 PCIE_CTX_C_GRX_P[0..15]
PCIE_CTX_C_GRX_P3 PEX_RX2_N GPIO5 GPU_VID1 GPU_VID0 <57> <6> PCIE_CTX_C_GRX_P[0..15]
AP20 PEX_RX3 GPIO6 H4 GPU_VID1 <57>
PCIE_CTX_C_GRX_N3 AN20 H5
PCIE_CTX_C_GRX_P4 PEX_RX3_N GPIO7 GPIO8 PCIE_CTX_C_GRX_N[0..15]
AN22 PEX_RX4 GPIO8 H6 <6> PCIE_CTX_C_GRX_N[0..15]
PCIE_CTX_C_GRX_N4 AP22 J7 THERM#_VGA
PCIE_CTX_C_GRX_P5 PEX_RX4_N GPIO9 THERM#_VGA <15>
AR22 K4
PCIE_CTX_C_GRX_N5 PEX_RX5 GPIO10
AR23 K5
PCIE_CTX_C_GRX_P6 PEX_RX5_N GPIO11 GPIO12
AP23 H7
GPIO
D PCIE_CTX_C_GRX_N6 PEX_RX6 GPIO12 @ D
AN23 J4 TV1
PCIE_CTX_C_GRX_P7 PEX_RX6_N GPIO13
AN25 J6
PCIE_CTX_C_GRX_N7 PEX_RX7 GPIO14 VGA_HDMI_HPD
AP25 L1
PCIE_CTX_C_GRX_P8 PEX_RX7_N GPIO15
AR25 L2
PCIE_CTX_C_GRX_N8 PEX_RX8 GPIO16
Under GPU(below 150mils) Near GPU AR26
PEX_RX8_N GPIO17
L4
150mA PCIE_CTX_C_GRX_P9 AP26 M4
BLM18PG330SN1D_0603 PCIE_CTX_C_GRX_N9 PEX_RX9 GPIO18
AN26 L7
0.1U_0402_16V4Z 0.1U_0402_16V4Z 10U_0603_6.3V6M +PLLVDD PCIE_CTX_C_GRX_P10 PEX_RX9_N GPIO19
+1.05VS_DGPU 1 2 AN28
PEX_RX10 GPIO20
L5
LV1 PCIE_CTX_C_GRX_N10 AP28 K6 C879
PCIE_CTX_C_GRX_P11 PEX_RX10_N GPIO21 +3VS_DGPU
1 1 1 1 2 AR28 L6
CV1 CV2 CV3 CV4 CV5 PCIE_CTX_C_GRX_N11 PEX_RX11 GPIO22 0.1U_0402_16V4Z
AR29 M6
PCIE_CTX_C_GRX_P12 PEX_RX11_N GPIO23 R1430
AP29 PEX_RX12 GPIO24 M7 1 2
PCIE_CTX_C_GRX_N12 AN29 PEX_RX12_N
5
2 2 2 2 1 PCIE_CTX_C_GRX_P13 AN31 N1 0_0402_5% U55
PCIE_CTX_C_GRX_N13 PEX_RX13 MIOA_D0_NC
AP31 P4 2 1 1
P
PEX_RX13_N MIOA_D1_NC <33,34,46,57> VGA_PWROK IN1
0.1U_0402_16V4Z 0.1U_0402_16V4Z PCIE_CTX_C_GRX_P14 AR31 P1 4 VGA_HDMI_HPD
PCIE_CTX_C_GRX_N14 PEX_RX14 MIOA_D2_NC O
AR32 PEX_RX14_N MIOA_D3_NC P2 <28> HDMI_HPD 2 IN2
G
PCIE_CTX_C_GRX_P15 AR34 P3
PCIE_CTX_C_GRX_N15 PEX_RX15 MIOA_D4_NC SN74AHC1G08DCKR_SC70-5
AP34 T3
3
PEX_RX15_N MIOA_D5_NC
MIOA_D6_NC T2
T1 +3VS_DGPU
PCIE_GTX_C_CRX_P0 CV6 0.22U_0402_10V6K PCIE_GTX_CRX_P0 MIOA_D7_NC
1 2 AL17 U4
PCIE_GTX_C_CRX_N0 0.22U_0402_10V6K PCIE_GTX_CRX_N0 PEX_TX0 MIOA_D8_NC
PCI EXPRESS
CV7 1 2 AM17 U1 1 2
PCIE_GTX_C_CRX_P1 CV8 0.22U_0402_10V6K PCIE_GTX_CRX_P1 PEX_TX0_N MIOA_D9_NC
1 2 AM18 PEX_TX1 MIOA_D10_NC U2
PCIE_GTX_C_CRX_N1 CV9 1 2 0.22U_0402_10V6K PCIE_GTX_CRX_N1 AM19 U3 0_0402_5% GPIO8 1 2
PCIE_GTX_C_CRX_P2 CV10 0.22U_0402_10V6K PCIE_GTX_CRX_P2 PEX_TX1_N MIOA_D11_NC @ RV1 10K_0402_5%
1 2 AL19 PEX_TX2 MIOA_D12_NC R6
PCIE_GTX_C_CRX_N2 CV11 1 2 0.22U_0402_10V6K PCIE_GTX_CRX_N2 AK19 T6 R1431
DVO
PCIE_GTX_C_CRX_P3 CV12 0.22U_0402_10V6K PCIE_GTX_CRX_P3 PEX_TX2_N MIOA_D13_NC GPIO12
1 2 AL20 PEX_TX3 MIOA_D14_NC N6 1 2
PCIE_GTX_C_CRX_N3 CV13 1 2 0.22U_0402_10V6K PCIE_GTX_CRX_N3 AM20 RV2 10K_0402_5%
PCIE_GTX_C_CRX_P4 CV14 0.22U_0402_10V6K PCIE_GTX_CRX_P4 PEX_TX3_N VGA_EDID_CLK
1 2 AM21 PEX_TX4 MIOB_D0_NC Y1 1 2
PCIE_GTX_C_CRX_N4 CV15 1 2 0.22U_0402_10V6K PCIE_GTX_CRX_N4 AM22 Y2 RV3 2.2K_0402_5%
PCIE_GTX_C_CRX_P5 CV16 0.22U_0402_10V6K PCIE_GTX_CRX_P5 PEX_TX4_N MIOB_D1_NC VGA_EDID_DATA
1 2 AL22 PEX_TX5 MIOB_D2_NC Y3 1 2
C PCIE_GTX_C_CRX_N5 CV17 0.22U_0402_10V6K PCIE_GTX_CRX_N5 RV4 2.2K_0402_5% C
1 2 AK22 PEX_TX5_N MIOB_D3_NC AB3
PCIE_GTX_C_CRX_P6 CV18 1 2 0.22U_0402_10V6K PCIE_GTX_CRX_P6 AL23 AB2
PCIE_GTX_C_CRX_N6 CV19 0.22U_0402_10V6K PCIE_GTX_CRX_N6 PEX_TX6 MIOB_D4_NC SMB_CLK_GPU
1 2 AM23 PEX_TX6_N MIOB_D5_NC AB1 1 2
PCIE_GTX_C_CRX_P7 CV20 1 2 0.22U_0402_10V6K PCIE_GTX_CRX_P7 AM24 AC4 RV5 2.2K_0402_5%
PCIE_GTX_C_CRX_N7 CV21 0.22U_0402_10V6K PCIE_GTX_CRX_N7 PEX_TX7 MIOB_D6_NC SMB_DATA_GPU
1 2 AM25 PEX_TX7_N MIOB_D7_NC AC1 1 2
PCIE_GTX_C_CRX_P8 CV22 1 2 0.22U_0402_10V6K PCIE_GTX_CRX_P8 AL25 AC2 RV6 2.2K_0402_5%
PCIE_GTX_C_CRX_N8 CV23 0.22U_0402_10V6K PCIE_GTX_CRX_N8 PEX_TX8 MIOB_D8_NC THERM#_VGA
1 2 AK25 PEX_TX8_N MIOB_D9_NC AC3 1 2
PCIE_GTX_C_CRX_P9 CV24 1 2 0.22U_0402_10V6K PCIE_GTX_CRX_P9 AL26 AE3 RV7 100K_0402_5%
PCIE_GTX_C_CRX_N9 CV25 0.22U_0402_10V6K PCIE_GTX_CRX_N9 PEX_TX9 MIOBD_10_NC HDCP_SCL
1 2 AM26
PEX_TX9_N MIOB_D11_NC
AE2 1 2
PCIE_GTX_C_CRX_P10 CV26 1 2 0.22U_0402_10V6K PCIE_GTX_CRX_P10 AM27 U6 RV8 2.2K_0402_5%
PCIE_GTX_C_CRX_N10 CV27 0.22U_0402_10V6K PCIE_GTX_CRX_N10 PEX_TX10 MIOB_D12_NC HDCP_SDA
1 2 AM28
PEX_TX10_N MIOB_D13_NC
W6 1 2
PCIE_GTX_C_CRX_P11 CV28 1 2 0.22U_0402_10V6K PCIE_GTX_CRX_P11 AL28 Y6 RV9 2.2K_0402_5%
PCIE_GTX_C_CRX_N11 CV29 0.22U_0402_10V6K PCIE_GTX_CRX_N11 PEX_TX11 MIOB_D14_NC I2CA_SDA
1 2 AK28
PEX_TX11_N 1 2
PCIE_GTX_C_CRX_P12 CV30 1 2 0.22U_0402_10V6K PCIE_GTX_CRX_P12 AK29 N3 RV10 2.2K_0402_5%
PCIE_GTX_C_CRX_N12 CV31 0.22U_0402_10V6K PCIE_GTX_CRX_N12 PEX_TX12 MIOA_HSYNC_NC I2CA_SCL
1 2 AL29
PEX_TX12_N MIOA_VSYNC_NC
L3 1 2
PCIE_GTX_C_CRX_P13 CV32 1 2 0.22U_0402_10V6K PCIE_GTX_CRX_P13 AM29 RV11 2.2K_0402_5%
PCIE_GTX_C_CRX_N13 CV33 0.22U_0402_10V6K PCIE_GTX_CRX_N13 PEX_TX13 I2CB_SCL
1 2 AM30 W1 1 2
PCIE_GTX_C_CRX_P14 CV34 0.22U_0402_10V6K PCIE_GTX_CRX_P14 PEX_TX13_N MIOB_HSYNC_NC RV12 2.2K_0402_5%
1 2 AM31
PEX_TX14 MIOB_VSYNC_NC
W2
PCIE_GTX_C_CRX_N14 CV35 1 2 0.22U_0402_10V6K PCIE_GTX_CRX_N14 AM32 I2CB_SDA 1 2
PCIE_GTX_C_CRX_P15 CV36 0.22U_0402_10V6K PCIE_GTX_CRX_P15 PEX_TX14_N RV13 2.2K_0402_5%
1 2 AN32
PEX_TX15 MIOA_DE_NC
N2
PCIE_GTX_C_CRX_N15 CV37 1 2 0.22U_0402_10V6K PCIE_GTX_CRX_N15 AP32 P5
PEX_TX15_N MIOA_CTL3_NC VGA_GPIO1
N5 1 2
MIOA_VREF_NC RV17 100K_0402_5%
Y5 VGA_HDMI_HPD 1 2
CLK_PCIE_VGA MIOB_DE_NC RV20 100K_0402_5%
<30> CLK_PCIE_VGA AR16 W3
CLK_PCIE_VGA# PEX_REFCLK MIOB_CTL3_NC
<30> CLK_PCIE_VGA# AR17 AF1
CLK_REQ_GPU# PEX_REFCLK_N MIOB_VREF_NC
AR13
PEX_CLKREQ_N
N4 1 2
PEX_TSTCLK_OUT MIOA_CLKIN_NC
RV19 stuff per NV request. 1 2 AJ17
PEX_TSTCLK_OUT MIOA_CLKOUT_NC
R4 RV18 10K_0402_5%
RV19 200_0402_1% PEX_TSTCLK_OUT# AJ18
12/17 PEX_TSTCLK_OUT_N
AE1 1 2
MIOB_CLKIN_NC RV21 10K_0402_5%
V4
B PLTRST_VGA_R# MIOB_CLKOUT_NC B
<33> PLTRST_VGA# 1 2 AM16
PEX_RST_N
1 2 RV22 0_0402_5% AG21 T4
RV24 10M_0402_5% PEX_TERMP MIOA_CLKOUT_NC_N
1 2 MIOB_CLKOUT_NC_N
W4
RV23 2.49K_0402_1%
YV1 60mA U5
+PLLVDD MIOACAL_PD_VDDQ_NC
AE9 T5
XTALIN XTAL_OUT PLLVDD MIOACAL_PU_GND_NC
1 2 45mA
AF9 AA7
27MHZ_16PF_X5H027000FG1H SP_PLLVDD MIOBCAL_PD_VDDQ_NC
45mA MIOBCAL_PU_GND_NC
AA6
1 1 AD9
CV46 CV47 VID_PLLVDD
CLK
18P_0402_50V8J 18P_0402_50V8J XTALIN B1
XTAL_OUT XTAL_IN
B2 AM15
2 2 RV27 10K_0402_5% XTAL_OUT DACA_RED
AM14
XTALOUT DACA_GREEN
1 2 D1
XTAL_OUTBUFF DACA_BLUE
AL14
2 1 XTALSSIN D2
RV26 10K_0402_5% XTAL_SSIN
AM13
DACA_HSYNC +3VS_DGPU
AL13
+3VS_DGPU DACA_VSYNC
Internal Thermal Sensor
SMB_CLK_GPU E2 AJ12
<17,33,57> DGPU_PWR_EN <15> SMB_CLK_GPU I2CS_SCL DACA_VDD
SMB_DATA_GPU E1 AK12 1
<15> SMB_DATA_GPU I2CS_SDA DACA_VREF
2
AK13
RV124 VGA_EDID_CLK E3 DACA_RSET C880
I2CC_SCL
2
DACs
10K_0402_5% VGA_EDID_DATA E4 AK4 0.1U_0402_16V4Z
RV118 I2CC_SDA DACB_RED 2
AL4
10K_0402_5% I2CB_SCL DACB_GREEN
G3 AJ4
2 1
I2CB_SDA I2CB_SCL DACB_BLUE
I2C
G2
I2CB_SDA
G
AM1
1
QV2 I2CA_SCL DACB_HSYNC
G1 AM2
CLK_REQ_GPU# I2CA_SDA I2CA_SCL DACB_VSYNC
<30> CLK_REQ_VGA# 1 3 G4
I2CA_SDA
AG7 +DACB_VDD 2 1
D
HDCP_SCL DACB_VDD RV32 10K_0402_5%
F6 I2CH_SCL DACB_VREF AK6
2
A 2N7002_SOT23-3 HDCP_SDA A
G6 I2CH_SDA DACB_RSET AH7
@ 1 @ 2 RV123
1
D RV115 0_0402_5% 10K_0402_5%
2N7002_SOT23-3 @
2 +3VS_DGPU
QV4 G N12P-GV-A1_BGA_973P
1
S N12PGV@
3
RV128
10K_0402_5%
@
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2010/12/03 Deciphered Date 2011/12/03 Title
VGA(1/12)-PCIE/DAC/GPIO
1
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
WWW.AliSaler.Com
0.3
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
PBL80 LA-7441P M/B
Date: Monday, April 11, 2011 Sheet 14 of 59
5 4 3 2 1
5 4 3 2 1
Internal Thermal Sensor
External VGA Thermal Sensor SMB_CLK_GPU <14>
SMB_DATA_GPU <14>
1
UV1D
RV35 RV36
Part 4 of 7 0_0402_5% 0_0402_5%
AM11 IFPA_TXC NC_0 A2
AM12 A7
2
IFPA_TXC_N NC_1 +3VS_DGPU
AM8 B7
IFPA_TXD0 NC_2 @ UV4 @
AL8 C5
IFPA_TXD0_N NC_3 STRAP4 VGA_SMB_CK2
AM10 C7 STRAP4 <25> 2 1 1 8
D IFPA_TXD1 NC_4 CV49 0.1U_0402_16V4Z VDD SCLK D
AM9 D5
IFPA_TXD1_N NC_5 THERM_D+ VGA_SMB_DA2
AK10 D6 2 7
IFPA_TXD2 NC_6 STRAP3 CV50 @ D+ SDATA
AL10 D7 STRAP3 <25>
IFPA_TXD2_N NC_7 THERM#_VGA
AK11 E5 1 2 3 6 THERM#_VGA <14>
IFPA_TXD3 NC_8 PGOOD D- ALERT#
AL11 E7
IFPA_TXD3_N NC_9 THERM_D- 2200P_0402_50V7K
F4 4 5
NC_10 THERM# GND
G5
NC_11
1
AP13 H32
IFPB_TXC NC_12
AN13
AN8
IFPB_TXC_N NC_13
J25
J26 N12PGV@ 10K_0402_5%
ADM1032ARMZ-2REEL_MSOP8 Address: 0x9A H 0x9E H
IFPB_TXD4 NC_14 Strap_Ref2_GND RV102
AP8 P6
IFPB_TXD4_N NC_15
1
AP10 U7
2
IFPB_TXD5 NC_16 RV107
AN10 IFPB_TXD5_N NC_17 V6
AR11 IFPB_TXD6 NC_18 Y4 40.2K_0402_1%
AR10 IFPB_TXD6_N NC_19 AA4 N12PGV@
AN11 AB4
2
IFPB_TXD7 NC_20 +3VS_DGPU
AP11 IFPB_TXD7_N NC_21 AB7
NC_22 AC5
+3VS_DGPU
NC
NC_23 AD6 Add C7,D7,E7,P6 for support GV
AM7 IFPC_L0 NC_24 AF6
2
AM6 IFPC_L0_N NC_25 AG6
AL5 AG20 RV25 RV28
IFPC_L1 NC_26 2.2K_0402_5% 2.2K_0402_5%
AM5 IFPC_L1_N NC_27 AJ5
AM3 IFPC_L2 NC_28 AK15
5
AM4 AL7
1
IFPC_L2_N NC_29 QV3B
AP1 IFPC_L3
AR2 VGA_SMB_CK2 4 3
IFPC_L3_N EC_SMB_CK2 <30,43>
2
2N7002DW-T/R7_SOT363-6
AR8 QV3A
IFPD_L0 VGA_SMB_DA2
AR7 IFPD_L0_N 1 6 EC_SMB_DA2 <30,43>
AP7 IFPD_L1
C 2N7002DW-T/R7_SOT363-6 C
AN7 IFPD_L1_N
AN5 IFPD_L2
LVDS/TMDS
AP5 IFPD_L2_N
AR5 IFPD_L3
AR4 IFPD_L3_N
<28> VGA_HDMI_TX2+ VGA_HDMI_TX2+ AH6
VGA_HDMI_TX2- IFPE_L0
<28> VGA_HDMI_TX2- AH5
VGA_HDMI_TX1+ IFPE_L0_N
<28> VGA_HDMI_TX1+ AH4
VGA_HDMI_TX1- IFPE_L1
<28> VGA_HDMI_TX1- AG4
VGA_HDMI_TX0+ IFPE_L1_N
<28> VGA_HDMI_TX0+ AF4
VGA_HDMI_TX0- IFPE_L2
<28> VGA_HDMI_TX0- AF5
VGA_HDMI_CLK+ IFPE_L2_N
<28> VGA_HDMI_CLK+ AE6
VGA_HDMI_CLK- IFPE_L3
<28> VGA_HDMI_CLK- AE5
IFPE_L3_N
D35 VDD_SENSE VDD_SENSE <57>
VDD_SENSE_0
AL2 P7
IFPF_L0 VDD_SENSE_1
AL3 AD20
IFPF_L0_N VDD_SENSE_2
AJ3
IFPF_L1
AJ2
IFPF_L1_N
AJ1
+3VS_DGPU IFPF_L2
AH1 AD19
IFPF_L2_N GND_SENSE_0
AH2 E35
IFPF_L3 GND_SENSE_1
AH3 R7
VGA_HDMI_CLK IFPF_L3_N GND_SENSE_2
1 2
RV40 4.7K_0402_5%
1 2 VGA_HDMI_DATA AP2
RV43 4.7K_0402_5% IFPC_AUX_I2CW_SCL
AN3
IFPC_AUX_I2CW_SDA_N TEST
B TESTMODE B
AP4 AP35
IFPD_AUX_I2CX_SCL TESTMODE @
AN4 AP14 TV2
IFPD_AUX_I2CX_SDA_N JTAG_TCK
1
AN14 @
JTAG_TDI TV3
AN16 @
JTAG_TDO TV4 10K_0402_5%
VGA_HDMI_CLK @
HDMI <28> VGA_HDMI_CLK VGA_HDMI_DATA
AE4
AD4
IFPE_AUX_I2CY_SCL JTAG_TMS
AR14
AP16 1 2
TV5
RV41
<28> VGA_HDMI_DATA IFPE_AUX_I2CY_SDA_N JTAG_TRST_N RV42 10K_0402_5%
2
AF3
IFPF_AUX_I2CZ_SCL
AF2
IFPF_AUX_I2CZ_SDA_N SERIAL
C3
ROM_CS_N ROM_SI
D3 ROM_SI <25>
+3VS_DGPU ROM_SI ROM_SO
C4 ROM_SO <25>
ROM_SO ROM_SCLK
D4 ROM_SCLK <25>
ROM_SCLK
2
RV44
10K_0402_5% GENERAL A5 1 2
NC/SPDIF_NC RV45 36K_0402_5%
A4
BUFRST_N
N9 1 2
1
MULTI_STRAP_REF0_GND RV46 40.2K_0402_1%
AB5
CEC
M9 1 2
STRAP0 MULTI_STRAP_REF1_GND RV47 40.2K_0402_1%
<25> STRAP0 W5
STRAP1 STRAP0 THERM_D+
<25> STRAP1 W7 B5
STRAP2 STRAP1 THERMDP THERM_D-
<25> STRAP2 V7 B4
STRAP2 THERMDN
N12P-GV-A1_BGA_973P
N12PGV@
A A
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2010/12/03 Deciphered Date 2011/12/03 Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
VGA(2/12)-LVDS/HDMI/DP/THM
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
0.3
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
PBL80 LA-7441P M/B
Date: Monday, April 11, 2011 Sheet 15 of 59
5 4 3 2 1
5 4 3 2 1
Pstate GPU_VID0 GPU_VID1 N12P-GS N12P-GV
P8-P12 0 0 0.825V 0.85V
P0(Hot) 1 0 0.975V 1V
D
0 1 D
P0(cold) 1 1 1V 1.025V
+VGA_CORE +VGA_CORE
UV1G
AB11 P21
GS EDP Peak is 35.32A +VGA_CORE +VGA_CORE
VDD_0 VDD_56
AB13 VDD_1
Part 7 of 7
VDD_57 P23 GV EDP Peak is 21.56A 22U_0603_6.3V6M 22U_0603_6.3V6M
AB15 VDD_2 VDD_58 P25
AB17 VDD_3 VDD_59 R11 1 1
AB19 VDD_4 VDD_60 R12 2 2 2
AB21 R13 + CV51 + CV52 CV53 CV54 CV55
VDD_5 VDD_61
AB23 VDD_6 VDD_62 R14
AB25 R15 @ @ @
VDD_7 VDD_63 2 2 1 1 1
AC11 VDD_8 VDD_64 R16
AC12 VDD_9 VDD_65 R17
AC13 R18 470U_D2_2VM_R4M 470U_D2_2VM_R4M 22U_0603_6.3V6M
VDD_10 VDD_66
AC14 VDD_11 VDD_67 R19
AC15 VDD_12 VDD_68 R20
AC16 VDD_13 VDD_69 R21
+VGA_CORE
Near GPU Under GPU(below 150mils)
AC17 VDD_14 VDD_70 R22
AC18 VDD_15 VDD_71 R23
AC19 R24 10U_0603_6.3V6M 4.7U_0603_6.3V6K 0.22U_0402_6.3V6K 0.22U_0402_6.3V6K
C VDD_16 VDD_72 C
AC20 VDD_17 VDD_73 R25
AC21 VDD_18 VDD_74 T12
AC22 VDD_19 VDD_75 T14 1 2 2 2 1 1
1
AC23 T16 CV57 CV56 CV58 CV59 CV60 CV61 CV62 CV63 CV64
VDD_20 VDD_76
POWER
AC24 T18 47U_0805_4V6
VDD_21 VDD_77
AC25 T20
2
VDD_22 VDD_78 2 1 1 1 2 2
AD12 VDD_23 VDD_79 T22
AD14 T24
VDD_24 VDD_80
AD16 V11
VDD_25 VDD_81 22U_0603_6.3V6M 10U_0603_6.3V6M 1U_0402_6.3V6K 0.22U_0402_6.3V6K
AD18 V13
VDD_26 VDD_82
AD22 V15
VDD_27 VDD_83
AD24 V17
VDD_28 VDD_84
L11 V19
VDD_29 VDD_85
L12 V21
VDD_30 VDD_86
L13
VDD_31 VDD_87
V23
+VGA_CORE
Under GPU(below 150mils)
L14 V25
VDD_32 VDD_88
L15 W11
VDD_33 VDD_89 0.1U_0402_16V7K 0.047U_0402_25V6K 0.022U_0402_25V7K 0.022U_0402_25V7K
L16 W12
VDD_34 VDD_90
L17 W13
VDD_35 VDD_91
L18 W14
VDD_36 VDD_92
L19 W15 1 1 1 1 1 1 1 1
VDD_37 VDD_93 CV65 CV66 CV67 CV68 CV69 CV70 CV71 CV72
L20 W16
VDD_38 VDD_94
L21 W17
VDD_39 VDD_95 0.1U_0402_16V7K
L22 W18
VDD_40 VDD_96 2 2 2 2 2 2 2 2
L23 W19
VDD_41 VDD_97
L24 W20
VDD_42 VDD_98
L25 W21
VDD_43 VDD_99 0.047U_0402_25V6K 0.047U_0402_25V6K 0.022U_0402_25V7K
M12 W22
VDD_44 VDD_100
M14 W23
VDD_45 VDD_101
M16 W24
VDD_46 VDD_102
M18 W25
VDD_47 VDD_103
M20 Y12
B VDD_48 VDD_104 +VGA_CORE B
M22 Y14
VDD_49 VDD_105
M24 Y16
VDD_50 VDD_106 0.01U_0402_25V7K 0.01U_0402_25V7K 0.01U_0402_25V7K
P11 Y18
VDD_51 VDD_107
P13 Y20
VDD_52 VDD_108
P15 Y22
VDD_53 VDD_109
P17 Y24 1 1 1 1 1 1 1 1
VDD_54 VDD_110 CV73 CV74 CV75 CV76 CV77 CV78 CV79 CV80
P19
VDD_55
0.01U_0402_25V7K
2 2 2 2 2 2 2 2
N12P-GV-A1_BGA_973P 0.01U_0402_25V7K 0.01U_0402_25V7K 0.01U_0402_25V7K 0.01U_0402_25V7K
N12PGV@
A A
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2010/12/03 Deciphered Date 2011/12/03 Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
VGA(3/12)-VGA CORE
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
WWW.AliSaler.Com
0.3
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
PBL80 LA-7441P M/B
Date: Monday, April 11, 2011 Sheet 16 of 59
5 4 3 2 1
5 4 3 2 1
GS is 2.95A
GS is 5.49A GV is 3.51A
GV is 2.99A
Near GPU UV1E
Under GPU(below 150mils) Near GPU
Part 5 of 7
+VRAM_1.5VS 4.7U_0603_6.3V6K 1U_0402_6.3V6K J23 AG11 0.1U_0402_16V4Z 1U_0402_6.3V4Z 10U_0603_6.3V6M +1.05VS_DGPU
FBVDDQ_0 PEX_IOVDDQ_0
J24 FBVDDQ_1 PEX_IOVDDQ_1 AG12
1 1 1 1 J29 FBVDDQ_2 PEX_IOVDDQ_2 AG13 1 1 1 1 1 1 1
CV82 CV83 CV84 CV81 AA27 AG15 CV85 CV92
FBVDDQ_3 PEX_IOVDDQ_3 CV86 CV88 CV89 CV90 CV91
AA29 AG16
4.7U_0603_6.3V6K FBVDDQ_4 PEX_IOVDDQ_4 22U_0805_6.3V6M
AA31 AG17
2 2 2 2 FBVDDQ_5 PEX_IOVDDQ_5 2 2 2 2 2 2 2
AB27 AG18
D FBVDDQ_6 PEX_IOVDDQ_6 D
AB29 AG22
1U_0402_6.3V6K FBVDDQ_7 PEX_IOVDDQ_7 0.1U_0402_16V4Z 1U_0402_6.3V4Z 4.7U_0603_6.3V6K
AC27 AG23
FBVDDQ_8 PEX_IOVDDQ_8
AD27 AG24
FBVDDQ_9 PEX_IOVDDQ_9
Under GPU(below 150mils) AE27
FBVDDQ_10 PEX_IOVDDQ_10
AG25
AJ28 AG26 0.1U_0402_16V4Z 1U_0402_6.3V4Z 10U_0603_6.3V6M +1.05VS_DGPU
FBVDDQ_11 PEX_IOVDDQ_11
B18 AJ14
FBVDDQ_12 PEX_IOVDDQ_12
+VRAM_1.5VS0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z E21
FBVDDQ_13 PEX_IOVDDQ_13
AJ15 1 1 1 1 1 1 1
G17 AJ19 CV93 CV100
FBVDDQ_14 PEX_IOVDDQ_14 CV94 CV96 CV97 CV98 CV99
1 1 1 1 1 1 1 1 G18 AJ21
FBVDDQ_15 PEX_IOVDDQ_15 22U_0805_6.3V6M
G22 AJ22
CV101 CV102 CV103 CV104 CV105 CV106 CV107 CV108 FBVDDQ_16 PEX_IOVDDQ_16 2 2 2 2 2 2 2
G8 AJ24
FBVDDQ_17 PEX_IOVDDQ_17
G9 FBVDDQ_18 PEX_IOVDDQ_18 AJ25
2 2 2 2 2 2 2 2 H29 AJ27 0.1U_0402_16V4Z 1U_0402_6.3V4Z 4.7U_0603_6.3V6K
FBVDDQ_19 PEX_IOVDDQ_19
POWER
J14 FBVDDQ_20 PEX_IOVDDQ_20 AK18
0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z J15 AK20
FBVDDQ_21 PEX_IOVDDQ_21
J16 FBVDDQ_22 PEX_IOVDDQ_22 AK23
J17 FBVDDQ_23 PEX_IOVDDQ_23 AK26 Under GPU(below 150mils) Near GPU
J20 FBVDDQ_24 PEX_IOVDDQ_24 AL16
J21 LV3
FBVDDQ_25 1U_0402_6.3V4Z
J22 FBVDDQ_26
2 1 +1.05VS_DGPU
N27 FBVDDQ_27
P27 AK16 1 1 1 BLM18PG121SN1D_0603 1
FBVDDQ_28 PEX_IOVDD_0 CV112
R27 FBVDDQ_29 PEX_IOVDD_1 AK17
T27 AK21 CV109 CV110 CV111
FBVDDQ_30 PEX_IOVDD_2 4.7U_0603_6.3V6K
U27 FBVDDQ_31 PEX_IOVDD_3 AK24
U29 AK27 2 2 2 4.7U_0603_6.3V6K 2
FBVDDQ_32 PEX_IOVDD_4
V27
V29
FBVDDQ_33 120mA 0.1U_0402_16V4Z
FBVDDQ_34
V34 FBVDDQ_35
W27 AG14 +PEX_PLLVDD
FBVDDQ_36 PEX_PLLVDD
Y27 FBVDDQ_37
Near GPU +3VS_DGPU
C C
2 1 +IFPAB_PLLVDD AK9 AG19
240mA (120mA each)
RV116 10K_0402_5% 1 @ IFPAB_PLLVDD PEX_SVDD_3V3
2 AJ11 IFPAB_RSET PEX_SVDD_3V3_NC F7
RV48 1K_0402_1% Near GPU+3VS_DGPU 1 1
2 1 +IFPAB_IOVDD AG9
120mA(12~16mils) CV113 CV114
RV117 10K_0402_5% IFPA_IOVDD 0.1U_0402_16V4Z 1U_0402_6.3V4Z
AG10 IFPB_IOVDD VDD33_0 J10
J11 0.1U_0402_16V4Z 2 2 4.7U_0603_6.3V6K
VDD33_1
J12 1 1 1 1 1
VDD33_2
2 1 +IFPC_PLLVDD AJ9 J13 CV119
@ IFPC_PLLVDD VDD33_3 CV118
1 2 RV49 10K_0402_5% AK7
IFPC_RSET VDD33_4
J9 CV115 CV116 CV117
RV50 1K_0402_1% 4.7U_0603_6.3V6K
2 2 2 2 2
2 1 +IFPC_IOVDD AJ8
IFPC_IOVDD
RV51 10K_0402_5%
P9 0.1U_0402_16V4Z 0.1U_0402_16V4Z
MIOA_VDDQ_NC_0
2 1 +IFPD_PLLVDD AC6 R9
IFPD_PLLVDD MIOA_VDDQ_NC_1
2
1 @ 2 RV52 10K_0402_5% AB6
IFPD_RSET MIOA_VDDQ_NC_2
T9 Under GPU(below 150mils)
RV53 1K_0402_1% U9
MIOA_VDDQ_NC_3
2 1 +IFPD_IOVDD AK8 RV54
RV55 10K_0402_5% IFPD_IOVDD 10K_0402_5%
AA9
1
+IFPEF_PLLVDD MIOB_VDDQ_NC_0
AJ6 AB9
IFPEF_PLLVDD MIOB_VDDQ_NC_1
1 2 AL1 W9
RV56 1K_0402_1%
+IFPE_IOVDD AE7
IFPEF_RSET MIOB_VDDQ_NC_2
MIOB_VDDQ_NC_3
Y9 +3VS to +3VS_DGPU
IFPE_IOVDD
2
AD7
IFPF_IOVDD RV57
10K_0402_5% +3VS
+3VALW
1
N12PGV@ N12P-GV-A1_BGA_973P
2
B Vgs=-4.5V,Id=3A,Rds<97mohm B
2
+3VS_DGPU
Near GPU Under GPU(below 150mils) R445 C491
0.1U_0402_16V7K
LV4 220mA 10K_0402_5%
1
1U_0402_6.3V6K 0.1U_0402_16V4Z +IFPEF_PLLVDD 1
2 1
1
S
3
BLM18PG181SN1D_0603 Q54
G R128
DGPU_PWR_EN# 1 R444 2 2 0_0805_5%
<46> DGPU_PWR_EN#
4.99K_0402_1% @
AO3413_SOT23 D +3VS_DGPU
1 1 1 1 1 1 2
2
6
CV120 CV125
4.7U_0603_6.3V6K CV121 CV122 CV123 CV124 0.1U_0402_16V4Z Q206A C492
0.01U_0402_25V7K
2 2 2 2 2 2 2 1
<14,33,57> DGPU_PWR_EN 1
2N7002DW-T/R7_SOT363-6 1
C683 C684
1
4.7U_0603_6.3V6K 0.1U_0402_16V4Z 4.7U_0805_10V4Z 1U_0402_6.3V6K
@ 2
2
+1.05VS_DGPU
LV6 570mA
2 1 4.7U_0603_6.3V6K 0.1U_0402_16V4Z +IFPE_IOVDD
BLM18PG181SN1D_0603
1 1 1 1 1
CV130 CV134
4.7U_0603_6.3V6K CV131 CV132 CV133 0.1U_0402_16V4Z
2 2 2 2 2
1U_0402_6.3V6K
A A
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2010/12/03 Deciphered Date 2011/12/03 Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
VGA(4/12)-POWER
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
0.3
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
PBL80 LA-7441P M/B
Date: Monday, April 11, 2011 Sheet 17 of 59
5 4 3 2 1
5 4 3 2 1
UV1F
B3 Part 6 of 7
GND_0
B6 GND_1 GND_97 V18
B9 GND_2 GND_98 V20
B12 GND_3 GND_99 V22
B15 GND_4 GND_100 V24
B21 GND_5 GND_101 V31
B24 Y11
GND_6 GND_102
B27 Y13
GND_7 GND_103
B30 Y15
D GND_8 GND_104 D
B33 Y17
GND_9 GND_105
C2 Y19
GND_10 GND_106
C34 Y21
GND_11 GND_107
E6 Y23
GND_12 GND_108
E9 Y25
GND_13 GND_109
E12 AA2
GND_14 GND_110
E15 AA5
GND_15 GND_111
E18 AA11
GND_16 GND_112
E24 AA12
GND_17 GND_113
E27 AA13
GND_18 GND_114
E30 AA14
GND_19 GND_115
F2 GND_20 GND_116 AA15
F31 GND_21 GND_117 AA16
F34 GND_22 GND_118 AA17
F5 GND_23 GND_119 AA18
J2 GND_24 GND_120 AA19
J5 GND_25 GND_121 AA20
J31 GND_26 GND_122 AA21
J34 GND_27 GND_123 AA22
K9 GND_28 GND_124 AA23
L9 GND_29 GND_125 AA24
M2 GND_30 GND_126 AA25
M5 GND_31 GND_127 AA34
M11 GND_32 GND_128 AB12
M13 GND_33 GND_129 AB14
M15 GND_34 GND_130 AB16
M17 GND_35 GND_131 AB18
M19 GND_36 GND_132 AB20
M21 GND_37 GND_133 AB22
M23 GND_38 GND_134 AB24
M25 GND_39 GND_135 AC9
M31 GND_40 GND_136 AD2
C C
M34 GND_41 GND_137 AD5
GND
N11 GND_42 GND_138 AD11
N12 GND_43 GND_139 AD13
N13 GND_44 GND_140 AD15
N14 GND_45 GND_141 AD17
N15 GND_46 GND_142 AD21
N16 GND_47 GND_143 AD23
N17 AD25
GND_48 GND_144
N18 AD31
GND_49 GND_145
N19 AD34
GND_50 GND_146
N20 AE11
GND_51 GND_147
N21 AE12
GND_52 GND_148
N22 AE13
GND_53 GND_149
N23 AE14
GND_54 GND_150
N24 AE15
GND_55 GND_151
N25 AE16
GND_56 GND_152
P12 AE17
GND_57 GND_153
P14 AE18
GND_58 GND_154
P16 AE19
GND_59 GND_155
P18 AE20
GND_60 GND_156
P20 AE21
GND_61 GND_157
P22 AE22
GND_62 GND_158
P24 AE23
GND_63 GND_159
R2 AE24
GND_64 GND_160
R5 AE25
GND_65 GND_161
R31 AG2
GND_66 GND_162
R34 AG5
GND_67 GND_163
T11 AG31
GND_68 GND_164
T13 AG34
GND_69 GND_165
T15 AK2
GND_70 GND_166
T17 AK5
GND_71 GND_167
T19 AK14
B GND_72 GND_168 B
T21 AK31
GND_73 GND_169
T23 AK34
GND_74 GND_170
T25 AL6
GND_75 GND_171
U11 AL9
GND_76 GND_172
U12 AL12
GND_77 GND_173
U13 AL15
GND_78 GND_174
U14 AL18
GND_79 GND_175
U15 AL21
GND_80 GND_176
U16 AL24
GND_81 GND_177
U17 AL27
GND_82 GND_178
U18 AL30
GND_83 GND_179
U19 AN2
GND_84 GND_180
U20 AN34
GND_85 GND_181
U21 AP3
GND_86 GND_182
U22 AP6
GND_87 GND_183
U23 AP9
GND_88 GND_184
U24 AP12
GND_89 GND_185
U25 AP15
GND_90 GND_186
V2 AP18
GND_91 GND_187
V5 AP21
GND_92 GND_188
V9 AP24
GND_93 GND_189
V12 AP27
GND_94 GND_190
V14 AP30
GND_95 GND_191
V16 AP33
GND_96 GND_192
N12P-GV-A1_BGA_973P
N12PGV@
A A
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2010/12/03 Deciphered Date 2011/12/03 Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
VGA(5/12)-GND
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
WWW.AliSaler.Com
0.3
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
PBL80 LA-7441P M/B
Date: Monday, April 11, 2011 Sheet 18 of 59
5 4 3 2 1
5 4 3 2 1
UV1B
Part 2 of 7 U30 CMDA0
MDA[0..63] FBA_CMD0 CMDA0 <21>
MDA0 L32 V30
D <21,22> MDA[0..63] FBA_D0 FBA_CMD1 D
MDA1 CMDA2
MDA2
N33
L33
FBA_D1
FBA_D2
FBA_CMD2
FBA_CMD3
U31
V32 CMDA3 CMDA2
CMDA3
<21>
<21>
Mode E - Mirror Mode Mapping
MDA3 N34 T35 CMDA4
FBA_D3 FBA_CMD4 CMDA4 <21,22>
MDA4 N35
FBA_D4 FBA_CMD5
U33 CMDA5
CMDA5 <21,22> DATA Bus
MDA5 P35 W32 CMDA6
FBA_D5 FBA_CMD6 CMDA6 <21,22>
MDA6 P33
FBA_D6 FBA_CMD7
W33 CMDA7
CMDA7 <21,22>
Address 0..31 32..63
MDA7 P34 W31 CMDA8
FBA_D7 FBA_CMD8 CMDA8 <21,22>
MDA8 K35
FBA_D8 FBA_CMD9
W34 CMDA9
CMDA9 <21,22> CMD3 CKE_L
MDA9 K33 U34 CMDA10
FBA_D9 FBA_CMD10 CMDA10 <21,22>
MDA10 K34
FBA_D10 FBA_CMD11
U35 CMDA11
CMDA11 <21,22> CMD8 A8 A8
MDA11 H33 U32 CMDA12
MDA12 FBA_D11 FBA_CMD12 CMDA13 CMDA12 <21,22>
G34 FBA_D12 FBA_CMD13 T34 CMDA13 <21,22> CMD2 CS0#_L
MDA13 G33 T33 CMDA14
FBA_D13 FBA_CMD14 CMDA14 <21,22>
MDA14 E34 FBA_D14 FBA_CMD15 W30 CMDA15
CMDA15 <21,22> CMD21 A7 A6
MDA15 E33 AB30 CMDA16
FBA_D15 FBA_CMD16 CMDA16 <22>
MDA16 G31 FBA_D16 FBA_CMD17 AA30 CMD24 A2 A1
MDA17 F30 AB31 CMDA18
FBA_D17 FBA_CMD18 CMDA18 <22>
MDA18 G30 FBA_D18 FBA_CMD19 AA32 CMDA19
CMDA19 <22> CMD23 A11 A9
MDA19 G32 AB33 CMDA20
FBA_D19 FBA_CMD20 CMDA20 <21,22>
MDA20 K30 FBA_D20 FBA_CMD21 Y32 CMDA21
CMDA21 <21,22> CMD26 A5 A4
MDA21 K32 Y33 CMDA22
MDA22 FBA_D21 FBA_CMD22 CMDA23 CMDA22 <21,22>
H30 FBA_D22 FBA_CMD23 AB34 CMDA23 <21,22> CMD7 A0 A12
MDA23 K31 AB35 CMDA24
FBA_D23 FBA_CMD24 CMDA24 <21,22>
MDA24 L31 FBA_D24 FBA_CMD25 Y35 CMDA25
CMDA25 <21,22> CMD15 CAS# CAS#
MDA25 L30 W35 CMDA26
FBA_D25 FBA_CMD26 CMDA26 <21,22>
MDA26 M32 Y34 CMDA27 CMD13 BA1 A3
MEMORY INTERFACE
MDA27 FBA_D26 FBA_CMD27 CMDA28 CMDA27 <21,22>
N30 FBA_D27 FBA_CMD28 Y31 CMDA28 <21,22>
MDA28 M30 FBA_D28 FBA_CMD29 Y30 CMDA29
CMDA29 <21,22> CMD4 A9 A11
MDA29 P31 W29 CMDA30
FBA_D29 FBA_CMD30 CMDA30 <21,22>
MDA30 R32 FBA_D30 FBA_CMD31 Y29 CMD18 CS0#_H
MDA31 R30
MDA32 FBA_D31 DQMA0
C
AG30 FBA_D32 FBA_DQM0 P32 CMD29 BA0 BA0 C
MDA33 AG32 H34 DQMA1
FBA_D33 FBA_DQM1 DQMA[7..0] <21,22>
MDA34 AH31 FBA_D34 FBA_DQM2 J30 DQMA2 CMD27 BA2 A15
MDA35 AF31 P30 DQMA3
FBA_D35 FBA_DQM3
MDA36 AF30 FBA_D36 FBA_DQM4 AF32 DQMA4 CMD6 A3 BA1
MDA37 AE30 AL32 DQMA5
FBA_D37 FBA_DQM5
MDA38 AC32 FBA_D38 FBA_DQM6 AL34 DQMA6 CMD17 CS1#_H
MDA39 AD30 AF35 DQMA7
+VRAM_1.5VS FBA_D39 FBA_DQM7
MDA40 AN33
FBA_D40 CMD19 ODT_H
MDA41 AL31 L35 DQSA#0
FBA_D41 FBA_DQS_RN0
A
MDA42 AM33 G35 DQSA#1 CMD22 A4 A5
FBA_D42 FBA_DQS_RN1
1
MDA43 AL33 H31 DQSA#2
FBA_D43 FBA_DQS_RN2
RV58 MDA44 AK30
FBA_D44 FBA_DQS_RN3
N32 DQSA#3
DQSA#[7..0] <21,22> CMD12 A13 A14
1.1K_0402_1% MDA45 AK32 AD32 DQSA#4
FBA_D45 FBA_DQS_RN4
@ MDA46 AJ30
FBA_D46 FBA_DQS_RN5
AJ31 DQSA#5 CMD28 WE# A10
12mil MDA47 AH30 AJ35 DQSA#6
2
FBA_D47 FBA_DQS_RN6
+FB_VREF MDA48 AH33
FBA_D48 FBA_DQS_RN7
AC34 DQSA#7 CMD10 A1 A2
MDA49 AH35
FBA_D49
1
1 MDA50 AH34
FBA_D50 FBA_DQS_WP0
L34 DQSA0 CMD25 A10 WE#
RV59 CV140 MDA51 AH32 H35 DQSA1
MDA52 FBA_D51 FBA_DQS_WP1 DQSA2
1.1K_0402_1% 0.01U_0402_25V7K AJ33
FBA_D52 FBA_DQS_WP2
J32 CMD9 A12 A0
@ @ MDA53 AL35 N31 DQSA3
2 FBA_D53 FBA_DQS_WP3
MDA54 AM34 AE31 DQSA4 CMD1 CS1#_L
2
MDA55 FBA_D54 FBA_DQS_WP4 DQSA5
AM35 AJ32 DQSA[7..0] <21,22>
FBA_D55 FBA_DQS_WP5
MDA56 AF33
FBA_D56 FBA_DQS_WP6
AJ34 DQSA6 CMD11 RAS# RAS#
MDA57 AE32 AC33 DQSA7
FBA_D57 FBA_DQS_WP7
MDA58 AF34
FBA_D58 CMD0 ODT_L
MDA59 AE35 P29
FBA_D59 FBA_WCK0
MDA60 AE34
FBA_D60 FBA_WCK0_N
R29 CMD5 A6 A7
Near GPU MDA61 AE33 L29
+1.05VS_DGPU MDA62 FBA_D61 FBA_WCK1
AB32
FBA_D62 FBA_WCK1_N
M29 CMD16 CKE_H
200mA MDA63 AC35 AG29
FBA_D63 FBA_WCK2
B
BLM18PG330SN1D_0603
FBA_WCK2_N
AH29 CMD20 RST RST B
1 2 0.1U_0402_16V4Z 10U_0603_6.3V6M +FB_AVDD AG27 AD29
FB_DLLAVDD_0 FBA_WCK3
LV8 +FB_AVDD_NC AF27
FB_PLLAVDD_0 FBA_WCK3_N
AE29 CMD14 A14 A13
2 1 1 1 2
CV141 J19
FB_DLLAVDD_1 CMD30 A15 BA2
CV258 CV142 CV143 CV144 J18 T32 CLKA0
FB_PLLAVDD_1 FBA_CLK0 CLKA0# CLKA0 <21>
10U_0603_6.3V6M T31
1 2 2 2 1 +FB_VREF FBA_CLK0_N CLKA0# <21>
J27
0.1U_0402_16V4Z 1U_0402_6.3V6K 60.4_0402_1% FB_VREF_NC CLKA1
2 1 T30 AC31 CLKA1 <22>
RV60 FBA_DEBUG0 FBA_CLK1 CLKA1#
T29 AC30 CLKA1# <22>
FBA_DEBUG1 FBA_CLK1_N
1
RV61
+VRAM_1.5VS 10K_0402_5%
N12P-GV-A1_BGA_973P
+1.05VS_DGPU N12PGV@
2
200mA
BLM18PG330SN1D_0603
1 2 0.1U_0402_16V4Z 10U_0603_6.3V6M +FB_AVDD_NC
LV9
2 1 1 1 2
CV145
CV259 CV146 CV147 CV148
10U_0603_6.3V6M
1 2 2 2 1
0.1U_0402_16V4Z 1U_0402_6.3V6K
Under GPU(below 150mils)
A A
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2010/12/03 Deciphered Date 2011/12/03 Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
VGA(6/12)-MEM Interface A
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
0.3
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
PBL80 LA-7441P M/B
Date: Monday, April 11, 2011 Sheet 19 of 59
5 4 3 2 1
5 4 3 2 1
UV1C
Part 3 of 7 F18 CMDB0
MDB[0..63] MDB0 FBC_CMD0 CMDB0 <23>
<23,24> MDB[0..63] B13 FBC_D0 FBC_CMD1 E19
MDB1 D13 D18 CMDB2
MDB2 FBC_D1 FBC_CMD2 CMDB3 CMDB2 <23>
MDB3
A13
A14
FBC_D2
FBC_D3
FBC_CMD3
FBC_CMD4
C17
F19 CMDB4
CMDB3
CMDB4
<23>
<23,24>
Mode E - Mirror Mode Mapping
MDB4 C16 C19 CMDB5
D FBC_D4 FBC_CMD5 CMDB5 <23,24> D
MDB5 B16 B17 CMDB6
MDB6 FBC_D5 FBC_CMD6 CMDB7 CMDB6 <23,24>
A17
FBC_D6 FBC_CMD7
E20 CMDB7 <23,24> DATA Bus
MDB7 D16 B19 CMDB8
FBC_D7 FBC_CMD8 CMDB8 <23,24>
MDB8 C13
FBC_D8 FBC_CMD9
D20 CMDB9
CMDB9 <23,24>
Address 0..31 32..63
MDB9 B11 A19 CMDB10
FBC_D9 FBC_CMD10 CMDB10 <23,24>
MDB10 C11
FBC_D10 FBC_CMD11
D19 CMDB11
CMDB11 <23,24> CMD3 CKE_L
MDB11 A11 C20 CMDB12
FBC_D11 FBC_CMD12 CMDB12 <23,24>
MDB12 C10
FBC_D12 FBC_CMD13
F20 CMDB13
CMDB13 <23,24> CMD8 A8 A8
MDB13 C8 B20 CMDB14
FBC_D13 FBC_CMD14 CMDB14 <23,24>
MDB14 B8
FBC_D14 FBC_CMD15
G21 CMDB15
CMDB15 <23,24> CMD2 CS0#_L
MDB15 A8 F22 CMDB16
MDB16 FBC_D15 FBC_CMD16 CMDB16 <24>
E8 FBC_D16 FBC_CMD17 F24 CMD21 A7 A6
MDB17 F8 F23 CMDB18
FBC_D17 FBC_CMD18 CMDB18 <24>
MDB18 F10 FBC_D18 FBC_CMD19 C25 CMDB19
CMDB19 <24> CMD24 A2 A1
MDB19 F9 C23 CMDB20
FBC_D19 FBC_CMD20 CMDB20 <23,24>
MDB20 F12 FBC_D20 FBC_CMD21 F21 CMDB21
CMDB21 <23,24> CMD23 A11 A9
MDB21 D8 E22 CMDB22
FBC_D21 FBC_CMD22 CMDB22 <23,24>
MDB22 D11 FBC_D22 FBC_CMD23 D21 CMDB23
CMDB23 <23,24> CMD26 A5 A4
MDB23 E11 A23 CMDB24
FBC_D23 FBC_CMD24 CMDB24 <23,24>
MDB24 D12 FBC_D24 FBC_CMD25 D22 CMDB25
CMDB25 <23,24> CMD7 A0 A12
MDB25 E13 B23 CMDB26
MDB26 FBC_D25 FBC_CMD26 CMDB27 CMDB26 <23,24>
F13 C22 CMD15 CAS# CAS#
MEMORY INTERFACE C
MDB27 FBC_D26 FBC_CMD27 CMDB28 CMDB27 <23,24>
F14 FBC_D27 FBC_CMD28 B22 CMDB28 <23,24>
MDB28 F15 FBC_D28 FBC_CMD29 A22 CMDB29
CMDB29 <23,24> CMD13 BA1 A3
MDB29 E16 A20 CMDB30
FBC_D29 FBC_CMD30 CMDB30 <23,24>
MDB30 F16 FBC_D30 FBC_CMD31 G20 CMD4 A9 A11
MDB31 F17 FBC_D31
MDB32 D29 FBC_D32 FBC_DQM0 A16 DQMB0 CMD18 CS0#_H
MDB33 F27 D10 DQMB1
FBC_D33 FBC_DQM1
MDB34 F28 FBC_D34 FBC_DQM2 F11 DQMB2
DQMB[7..0] <23,24> CMD29 BA0 BA0
MDB35 E28 D15 DQMB3
MDB36 FBC_D35 FBC_DQM3 DQMB4
C
D26 FBC_D36 FBC_DQM4 D27 CMD27 BA2 A15 C
MDB37 F25 D34 DQMB5
FBC_D37 FBC_DQM5
MDB38 D24 FBC_D38 FBC_DQM6 A34 DQMB6 CMD6 A3 BA1
MDB39 E25 D28 DQMB7
FBC_D39 FBC_DQM7
MDB40 E32 FBC_D40 CMD17 CS1#_H
MDB41 F32 B14 DQSB#0
FBC_D41 FBC_DQS_RN0
MDB42 D33 FBC_D42 FBC_DQS_RN1 B10 DQSB#1 CMD19 ODT_H
MDB43 E31 D9 DQSB#2
FBC_D43 FBC_DQS_RN2
MDB44 C33
FBC_D44 FBC_DQS_RN3
E14 DQSB#3
DQSB#[7..0] <23,24> CMD22 A4 A5
MDB45 F29 F26 DQSB#4
MDB46 FBC_D45 FBC_DQS_RN4 DQSB#5
D30
FBC_D46 FBC_DQS_RN5
D31 CMD12 A13 A14
MDB47 E29 A31 DQSB#6
FBC_D47 FBC_DQS_RN6
MDB48 B29
FBC_D48 FBC_DQS_RN7
A26 DQSB#7 CMD28 WE# A10
MDB49 C31
FBC_D49
MDB50 C29
FBC_D50 FBC_DQS_WP0
C14 DQSB0 CMD10 A1 A2
MDB51 B31 A10 DQSB1
FBC_D51 FBC_DQS_WP1
MDB52 C32
FBC_D52 FBC_DQS_WP2
E10 DQSB2 CMD25 A10 WE#
MDB53 B32 D14 DQSB3
FBC_D53 FBC_DQS_WP3
MDB54 B35
FBC_D54 FBC_DQS_WP4
E26 DQSB4 CMD9 A12 A0
MDB55 B34 D32 DQSB5
MDB56 FBC_D55 FBC_DQS_WP5 DQSB6 DQSB[7..0] <23,24>
A29
FBC_D56 FBC_DQS_WP6
A32 CMD1 CS1#_L
MDB57 B28 B26 DQSB7
FBC_D57 FBC_DQS_WP7
MDB58 A28
FBC_D58 CMD11 RAS# RAS#
MDB59 C28 G14
FBC_D59 FBC_WCK0
MDB60 C26
FBC_D60 FBC_WCK0_N
G15 CMD0 ODT_L
MDB61 D25 G11
FBC_D61 FBC_WCK1
MDB62 B25
FBC_D62 FBC_WCK1_N
G12 CMD5 A6 A7
MDB63 A25 G27
FBC_D63 FBC_WCK2
FBC_WCK2_N
G28 CMD16 CKE_H
G24
FBC_WCK3
+VRAM_1.5VS 1 2 K27
FBCAL_PD_VDDQ FBC_WCK3_N
G25 CMD20 RST RST
RV62 40.2_0402_1%
B
1 2 L27
FBCAL_PU_GND CMD14 A14 A13 B
RV63 40.2_0402_1% E17 CLKB0
FBC_CLK0 CLKB0 <23>
1 2 M27
FBCAL_TERM_GND FBC_CLK0_N
D17 CLKB0#
CLKB0# <23> CMD30 A15 BA2
RV64 60.4_0402_1%
60.4_0402_1% 2 1 RV65 G19 D23 CLKB1
+VRAM_1.5VS FBC_DEBUG0 FBC_CLK1 CLKB1 <24>
2 1 G16 E23 CLKB1#
FBB_DEBUG1 FBC_CLK1_N CLKB1# <24>
RV66 10K_0402_5%
N12P-GV-A1_BGA_973P
N12PGV@
A A
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2010/12/03 Deciphered Date 2011/12/03 Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
VGA(7/12)-MEM Interface C
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
WWW.AliSaler.Com
0.3
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
PBL80 LA-7441P M/B
Date: Monday, April 11, 2011 Sheet 20 of 59
5 4 3 2 1
5 4 3 2 1
Support N12P-GV/GS
Memory Partition A - Lower 32 bits Support Max VRAM 2G
MDA[0..63] <19,22>
CMDA[30..0] <19,22>
D DQMA[7..0] <19,22> D
UV5 UV6
DQSA[7..0] <19,22>
+VRAM_1.5VS +FBA_VREF0 M8 E3 MDA3 +FBA_VREF0 M8 E3 MDA18
VREFCA DQL0 MDA4 VREFCA DQL0 MDA19 DQSA#[7..0] <19,22>
H1 F7 H1 F7
VREFDQ DQL1 MDA2 VREFDQ DQL1 MDA23
F2 F2
DQL2 DQL2
1
CMDA7 N3 F8 MDA7 CMDA7 N3 F8 MDA17 Group2
CMDA10 A0 DQL3 MDA0 CMDA10 A0 DQL3 MDA21
RV67 P7
A1 DQL4
H3 Group0 P7
A1 DQL4
H3
CMDA24 P3 H8 MDA5 CMDA24 P3 H8 MDA16
1.1K_0402_1% CMDA6 A2 DQL5 MDA1 CMDA6 A2 DQL5 MDA20
N2 G2 N2 G2
CMDA22 A3 DQL6 MDA6 CMDA22 A3 DQL6 MDA22
P8 H7 P8 H7
Mode E - Mirror
2
+FBA_VREF0 CMDA26 A4 DQL7 CMDA26 A4 DQL7
P2 A5 P2 A5
CMDA5 R8 CMDA5 R8
A6 A6
Mode Mapping
1
1 CMDA21 R2 D7 MDA29 CMDA21 R2 D7 MDA14
RV68 CV149 CMDA8 A7 DQU0 MDA26 CMDA8 A7 DQU0 MDA11
T8 A8 DQU1 C3 T8 A8 DQU1 C3
0.01U_0402_25V7K CMDA4 R3 A9 DQU2 C8 MDA31 CMDA4 R3 A9 DQU2 C8 MDA15 DATA Bus
1.1K_0402_1% CMDA25 L7 C2 MDA25 CMDA25 L7 C2 MDA8
2 A10/AP DQU3 A10/AP DQU3
CMDA23 R7 A7 MDA27 Group3 CMDA23 R7 A7 MDA13 Group1 Address 0..31 32..63
2
CMDA9 A11 DQU4 MDA28 CMDA9 A11 DQU4 MDA10
N7 A12 DQU5 A2 N7 A12 DQU5 A2
CMDA12 T3 A13 DQU6 B8 MDA30 CMDA12 T3 A13 DQU6 B8 MDA12 CMD3 CKE_L
CMDA14 T7 A3 MDA24 CMDA14 T7 A3 MDA9
CMDA30 A14 DQU7 CMDA30 A14 DQU7
M7 A15/BA3 +VRAM_1.5VS
M7 A15/BA3 +VRAM_1.5VS
CMD8 A8 A8
CMD2 CS0#_L
CMDA29 M2 B2 CMDA29 M2 B2
BA0 VDD BA0 VDD
CMDA13 N8 BA1 VDD D9 CMDA13 N8 BA1 VDD D9 CMD21 A7 A6
CLKA0 CMDA27 M3 G7 CMDA27 M3 G7
BA2 VDD BA2 VDD
VDD K2 VDD K2 CMD24 A2 A1
VDD K8 VDD K8
2
VDD N1 VDD N1 CMD23 A11 A9
RV69 CLKA0 J7 N9 CLKA0 J7 N9
<19> CLKA0 CLKA0# CK VDD CLKA0# CK VDD
C
160_0402_1% <19> CLKA0# K7 CK VDD R1 K7 CK VDD R1 CMD26 A5 A4 C
CMDA3 K9 R9 CMDA3 K9 R9
CKE/CKE0 VDD CKE/CKE0 VDD
CMD7 A0 A12
1
CLKA0# CMDA0 K1 ODT/ODT0 VDDQ A1 CMDA0 K1 ODT/ODT0 VDDQ A1 CMD15 CAS# CAS#
CMDA2 L2 A8 CMDA2 L2 A8
CS/CS0 VDDQ CS/CS0 VDDQ
CMDA11 J3 RAS VDDQ C1 CMDA11 J3 RAS VDDQ C1 CMD13 BA1 A3
CMDA15 K3 C9 CMDA15 K3 C9 CMDA0
CAS VDDQ CAS VDDQ
CMDA28 L3
WE VDDQ
D2 CMDA28 L3
WE VDDQ
D2 CMD4 A9 A11
E9 E9
VDDQ VDDQ CMDA3
VDDQ
F1
VDDQ
F1 CMD18 CS0#_H
DQSA0 F3 H2 DQSA2 F3 H2
DQSL VDDQ DQSL VDDQ
DQSA3 C7
DQSU VDDQ
H9 DQSA1 C7
DQSU VDDQ
H9 CMD29 BA0 BA0
2
RV70 RV71 CMD27 BA2 A15
DQMA0 E7 A9 DQMA2 E7 A9 10K_0402_5% 10K_0402_5%
DML VSS DML VSS
DQMA3 D3
DMU VSS
B3 DQMA1 D3
DMU VSS
B3 CMD6 A3 BA1
E1 E1
1
VSS VSS
VSS
G8
VSS
G8 CMD17 CS1#_H
DQSA#0 G3 J2 DQSA#2 G3 J2
DQSA#3 DQSL VSS DQSA#1 DQSL VSS
B7 DQSU VSS
J8 B7 DQSU VSS
J8 CMD19 ODT_H
M1 M1
VSS VSS
VSS
M9
VSS
M9 CMD22 A4 A5
P1 P1
VSS VSS
CMDA20 T2
RESET VSS
P9 CMDA20 T2
RESET VSS
P9 CMD12 A13 A14
T1 T1
VSS VSS
L8
ZQ/ZQ0 VSS
T9 L8
ZQ/ZQ0 VSS
T9 CMD28 WE# A10
CMD10 A1 A2
1
1
J1 B1 J1 B1
NC/ODT1 VSSQ NC/ODT1 VSSQ
1
RV72 RV73 L1
NC/CS1 VSSQ
B9 RV74 L1
NC/CS1 VSSQ
B9 CMD25 A10 WE#
243_0402_1% J9 D1 243_0402_1% J9 D1
NC/CE1 VSSQ NC/CE1 VSSQ
B
10K_0402_5% L9
NCZQ1 VSSQ
D8 L9
NCZQ1 VSSQ
D8 CMD9 A12 A0 B
E2 E2
2
2
VSSQ VSSQ
E8 E8 CMD1 CS1#_L
2
VSSQ VSSQ
F9 F9
VSSQ VSSQ
VSSQ
G1
VSSQ
G1 CMD11 RAS# RAS#
G9 G9
VSSQ VSSQ
CMD0 ODT_L
96-BALL 96-BALL
SDRAM DDR3 SDRAM DDR3 CMD5 A6 A7
H5TQ2G63BFR-11C FBGA 96P H5TQ2G63BFR-11C FBGA 96P
@ @ CMD16 CKE_H
Under UV5(below 150mils) Under UV6(below 150mils)
CMD20 RST RST
+VRAM_1.5VS +VRAM_1.5VS CMD14 A14 A13
1U_0402_6.3V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 1U_0402_6.3V4Z 1U_0402_6.3V4Z 1U_0402_6.3V4Z 1U_0402_6.3V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 1U_0402_6.3V4Z 1U_0402_6.3V4Z 1U_0402_6.3V4Z CMD30 A15 BA2
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
CV150 CV151 CV152 CV153 CV154 CV155 CV156 CV157 CV158 CV159 CV160 CV161 CV162 CV163 CV164 CV165 CV166 CV167 CV168 CV169 CV170 CV171 CV172 CV173
2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2
1U_0402_6.3V4Z 1U_0402_6.3V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 1U_0402_6.3V4Z 1U_0402_6.3V4Z 1U_0402_6.3V4Z 1U_0402_6.3V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 1U_0402_6.3V4Z 1U_0402_6.3V4Z
A A
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2010/12/03 Deciphered Date 2011/12/03 Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
VGA(8/12)-VRAM A Lower
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
0.3
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
PBL80 LA-7441P M/B
Date: Monday, April 11, 2011 Sheet 21 of 59
5 4 3 2 1
5 4 3 2 1
Memory Partition A - Upper 32 bits
MDA[0..63] <19,21>
CMDA[30..0] <19,21>
UV8 UV7
+VRAM_1.5VS
+FBA_VREF1 MDA39 +FBA_VREF1 MDA58 DQMA[7..0] <19,21>
M8 E3 M8 E3
VREFCA DQL0 MDA35 VREFCA DQL0 MDA59
H1 F7 H1 F7 DQSA[7..0] <19,21>
1 VREFDQ DQL1 MDA37 VREFDQ DQL1 MDA56
F2 F2
D RV76 CMDA9 DQL2 MDA33 CMDA9 DQL2 MDA63 D
N3 F8 N3 F8 DQSA#[7..0] <19,21>
CMDA24 A0 DQL3 MDA38 CMDA24 A0 DQL3 MDA57
P7
A1 DQL4
H3 Group4 P7
A1 DQL4
H3 Group7
1.1K_0402_1% CMDA10 P3 H8 MDA32 CMDA10 P3 H8 MDA61
CMDA13 A2 DQL5 MDA36 CMDA13 A2 DQL5 MDA60
N2 G2 N2 G2
2
+FBA_VREF1 CMDA26 A3 DQL6 MDA34 CMDA26 A3 DQL6 MDA62
P8 H7 P8 H7
CMDA22 A4 DQL7 CMDA22 A4 DQL7
P2 P2
A5 A5
1
1 CMDA21 R8 CMDA21 R8
RV75 CV174 CMDA5 A6 MDA42 CMDA5 A6 MDA49
0.01U_0402_25V7K CMDA8
R2
T8
A7
A8
DQU0
DQU1
D7
C3 MDA45 CMDA8
R2
T8
A7
A8
DQU0
DQU1
D7
C3 MDA53 Mode E - Mirror Mode Mapping
1.1K_0402_1% CMDA23 R3 C8 MDA40 CMDA23 R3 C8 MDA51
2 A9 DQU2 A9 DQU2
CMDA28 L7 C2 MDA44 CMDA28 L7 C2 MDA55 DATA Bus
2
CMDA4 A10/AP DQU3 MDA41 CMDA4 A10/AP DQU3 MDA48
R7 A11 DQU4 A7 Group5 R7 A11 DQU4 A7 Group6
CMDA7 N7 A12 DQU5 A2 MDA47 CMDA7 N7 A12 DQU5 A2 MDA54 Address 0..31 32..63
CMDA14 T3 B8 MDA43 CMDA14 T3 B8 MDA50
A13 DQU6 A13 DQU6
CMDA12 T7 A14 DQU7 A3 MDA46 CMDA12 T7 A14 DQU7 A3 MDA52 CMD3 CKE_L
CMDA27 M7 CMDA27 M7
A15/BA3 +VRAM_1.5VS A15/BA3 +VRAM_1.5VS CMD8 A8 A8
CMDA29 M2 BA0 VDD B2 CMDA29 M2 BA0 VDD B2 CMD2 CS0#_L
CMDA6 N8 D9 CMDA6 N8 D9
BA1 VDD BA1 VDD
CLKA1 CMDA30 M3 BA2 VDD G7 CMDA30 M3 BA2 VDD G7 CMD21 A7 A6
VDD K2 VDD K2
VDD K8 VDD K8 CMD24 A2 A1
2
VDD N1 VDD N1
RV77
<19> CLKA1
CLKA1 J7 CK VDD N9 CLKA1 J7 CK VDD N9 CMD23 A11 A9
160_0402_1% CLKA1# K7 R1 CLKA1# K7 R1
<19> CLKA1# CMDA16 CK VDD CMDA16 CK VDD
K9 CKE/CKE0 VDD R9 K9 CKE/CKE0 VDD R9 CMD26 A5 A4
1
CMD7 A0 A12
CLKA1# CMDA19 K1 A1 CMDA19 K1 A1
ODT/ODT0 VDDQ ODT/ODT0 VDDQ
CMDA18 L2 CS/CS0 VDDQ A8 CMDA18 L2 CS/CS0 VDDQ A8 CMD15 CAS# CAS#
CMDA11 J3 C1 CMDA11 J3 C1
C RAS VDDQ RAS VDDQ C
CMDA15 K3 CAS VDDQ C9 CMDA15 K3 CAS VDDQ C9 CMD13 BA1 A3
CMDA25 L3 D2 CMDA25 L3 D2
WE VDDQ WE VDDQ
VDDQ E9 VDDQ E9 CMD4 A9 A11
VDDQ F1 VDDQ F1
DQSA4 F3 H2 DQSA7 F3 H2 CMD18 CS0#_H
DQSA5 DQSL VDDQ DQSA6 DQSL VDDQ
C7 DQSU VDDQ H9 C7 DQSU VDDQ H9
CMD29 BA0 BA0
DQMA4 E7
DML VSS
A9 DQMA7 E7
DML VSS
A9 CMD27 BA2 A15
CMDA16 DQMA5 D3 B3 DQMA6 D3 B3
DMU VSS DMU VSS
VSS
E1
VSS
E1 CMD6 A3 BA1
G8 G8
VSS VSS
CMDA19 DQSA#4 G3 DQSL VSS
J2 DQSA#7 G3 DQSL VSS
J2 CMD17 CS1#_H
DQSA#5 B7 J8 DQSA#6 B7 J8
DQSU VSS DQSU VSS
VSS
M1
VSS
M1 CMD19 ODT_H
M9 M9
VSS VSS
2
VSS
P1
VSS
P1 CMD22 A4 A5
RV78 RV79 CMDA20 T2 P9 CMDA20 T2 P9
RESET VSS RESET VSS
10K_0402_5% 10K_0402_5%
VSS
T1
VSS
T1 CMD12 A13 A14
L8 T9 L8 T9
ZQ/ZQ0 VSS ZQ/ZQ0 VSS
CMD28 WE# A10
1
1
J1
NC/ODT1 VSSQ
B1 J1
NC/ODT1 VSSQ
B1 CMD10 A1 A2
RV80 L1 B9 RV81 L1 B9
NC/CS1 VSSQ NC/CS1 VSSQ
243_0402_1% J9
NC/CE1 VSSQ
D1 243_0402_1% J9
NC/CE1 VSSQ
D1 CMD25 A10 WE#
L9 D8 L9 D8
NCZQ1 VSSQ NCZQ1 VSSQ
E2 E2 CMD9 A12 A0
2
2
VSSQ VSSQ
E8 E8
VSSQ VSSQ
VSSQ
F9
VSSQ
F9 CMD1 CS1#_L
G1 G1
VSSQ VSSQ
VSSQ
G9
VSSQ
G9 CMD11 RAS# RAS#
B B
96-BALL 96-BALL CMD0 ODT_L
SDRAM DDR3 SDRAM DDR3
H5TQ2G63BFR-11C FBGA 96P H5TQ2G63BFR-11C FBGA 96P CMD5 A6 A7
Under UV8(below 150mils) @ Under UV7(below 150mils) @
CMD16 CKE_H
+VRAM_1.5VS
+VRAM_1.5VS CMD20 RST RST
1U_0402_6.3V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 1U_0402_6.3V4Z 1U_0402_6.3V4Z 1U_0402_6.3V4Z
1U_0402_6.3V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 1U_0402_6.3V4Z 1U_0402_6.3V4Z 1U_0402_6.3V4Z CMD14 A14 A13
1 1 1 1 1 1 1 1 1 1 1 1
CV175 CV176 CV177 CV178 CV179 CV180 CV181 CV182 CV183 CV184 CV185 CV186 1 1 1 1 1 1 1 1 1 1 1 1 CMD30 A15 BA2
CV187 CV188 CV189 CV190 CV191 CV192 CV193 CV194 CV195 CV196 CV197 CV198
2 2 2 2 2 2 2 2 2 2 2 2
1U_0402_6.3V4Z 1U_0402_6.3V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 1U_0402_6.3V4Z 1U_0402_6.3V4Z 2 2 2 2 2 2 2 2 2 2 2 2
1U_0402_6.3V4Z 1U_0402_6.3V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 1U_0402_6.3V4Z 1U_0402_6.3V4Z
A A
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2010/12/03 Deciphered Date 2011/12/03 Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
VGA(9/12)-VRAM A Upper
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
WWW.AliSaler.Com
0.3
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
PBL80 LA-7441P M/B
Date: Monday, April 11, 2011 Sheet 22 of 59
5 4 3 2 1
5 4 3 2 1
Memory Partition C - Lower 32 bits MDB[0..63] <20,24>
CMDB[30..0] <20,24>
DQMB[7..0] <20,24>
DQSB[7..0] <20,24>
+VRAM_1.5VS UV9 UV10
DQSB#[7..0] <20,24>
+FBB_VREF0 M8 E3 MDB0 +FBB_VREF0 M8 E3 MDB22
VREFCA DQL0 VREFCA DQL0
1 H1
VREFDQ DQL1
F7 MDB7 H1
VREFDQ DQL1
F7 MDB16
D RV82 MDB1 MDB18 D
F2 F2
CMDB7 DQL2 MDB4 CMDB7 DQL2 MDB21
N3
A0 DQL3
F8 Group0 N3
A0 DQL3
F8
1.1K_0402_1% CMDB10 P7 H3 MDB3 CMDB10 P7 H3 MDB23 Group2
8PCS@ CMDB24 A1 DQL4 MDB6 CMDB24 A1 DQL4 MDB19
P3 H8 P3 H8
Mode E - Mirror
2
+FBB_VREF0 CMDB6 A2 DQL5 MDB2 CMDB6 A2 DQL5 MDB20
N2 G2 N2 G2
CMDB22 A3 DQL6 MDB5 CMDB22 A3 DQL6 MDB17
P8 H7 P8 H7
A4 DQL7 A4 DQL7
Mode Mapping
1
1 CMDB26 P2 CMDB26 P2
RV83 CV199 CMDB5 A5 CMDB5 A5
R8 R8
A6 A6
0.01U_0402_25V7K CMDB21 R2
A7 DQU0
D7 MDB28 CMDB21 R2
A7 DQU0
D7 MDB13 DATA Bus
1.1K_0402_1% 8PCS@ CMDB8 T8 C3 MDB25 CMDB8 T8 C3 MDB11
2 A8 DQU1 A8 DQU1
8PCS@ CMDB4 R3 C8 MDB31 CMDB4 R3 C8 MDB14 Address 0..31 32..63
2
CMDB25 A9 DQU2 MDB24 CMDB25 A9 DQU2 MDB9
L7 A10/AP DQU3 C2 L7 A10/AP DQU3 C2
CMDB23 R7 A11 DQU4 A7 MDB29 Group3 CMDB23 R7 A11 DQU4 A7 MDB12 Group1 CMD3 CKE_L
CMDB9 N7 A2 MDB27 CMDB9 N7 A2 MDB8
A12 DQU5 A12 DQU5
CMDB12 T3 A13 DQU6 B8 MDB30 CMDB12 T3 A13 DQU6 B8 MDB15 CMD8 A8 A8
CMDB14 T7 A3 MDB26 CMDB14 T7 A3 MDB10
CMDB30 A14 DQU7 CMDB30 A14 DQU7
M7 A15/BA3 M7 A15/BA3 CMD2 CS0#_L
+VRAM_1.5VS +VRAM_1.5VS
CMD21 A7 A6
CMDB29 M2 B2 CMDB29 M2 B2
BA0 VDD BA0 VDD
CMDB13 N8 BA1 VDD D9 CMDB13 N8 BA1 VDD D9 CMD24 A2 A1
CLKB0 CMDB27 M3 G7 CMDB27 M3 G7
BA2 VDD BA2 VDD
VDD K2 VDD K2 CMD23 A11 A9
VDD K8 VDD K8
2
VDD N1 VDD N1 CMD26 A5 A4
RV84 CLKB0 J7 N9 CLKB0 J7 N9
<20> CLKB0 CLKB0# CK VDD CLKB0# CK VDD
160_0402_1% <20> CLKB0# K7
CK VDD R1 K7
CK VDD R1 CMD7 A0 A12
CMDB3 K9 R9 CMDB3 K9 R9
CKE/CKE0 VDD CKE/CKE0 VDD
8PCS@ CMD15 CAS# CAS#
1
CLKB0# CMDB0 K1 ODT/ODT0 VDDQ A1 CMDB0 K1 ODT/ODT0 VDDQ A1 CMD13 BA1 A3
CMDB2 L2 A8 CMDB2 L2 A8
C CS/CS0 VDDQ CS/CS0 VDDQ C
CMDB11 J3 RAS VDDQ C1 CMDB11 J3 RAS VDDQ C1 CMD4 A9 A11
CMDB15 K3 C9 CMDB15 K3 C9
CAS VDDQ CAS VDDQ
CMDB28 L3 WE VDDQ D2 CMDB28 L3 WE VDDQ D2 CMD18 CS0#_H
VDDQ E9 VDDQ E9
VDDQ F1 VDDQ F1 CMD29 BA0 BA0
DQSB0 F3 H2 DQSB2 F3 H2 CMDB0
DQSL VDDQ DQSL VDDQ
DQSB3 C7 DQSU VDDQ H9 DQSB1 C7 DQSU VDDQ H9 CMD27 BA2 A15
CMDB3 CMD6 A3 BA1
DQMB0 E7 A9 DQMB2 E7 A9
DML VSS DML VSS
DQMB3 D3
DMU VSS
B3 DQMB1 D3
DMU VSS
B3 CMD17 CS1#_H
E1 E1
VSS VSS
2
VSS
G8
VSS
G8 CMD19 ODT_H
DQSB#0 G3 J2 DQSB#2 G3 J2 RV86
DQSB#3 DQSL VSS DQSB#1 DQSL VSS
B7 DQSU VSS
J8 B7 DQSU VSS
J8 RV85 10K_0402_5% CMD22 A4 A5
M1 M1 10K_0402_5% 8PCS@
VSS VSS
M9 M9 8PCS@ CMD12 A13 A14
1
VSS VSS
P1 P1
VSS VSS
CMDB20 T2
RESET VSS
P9 CMDB20 T2
RESET VSS
P9 CMD28 WE# A10
T1 T1
VSS VSS
L8
ZQ/ZQ0 VSS
T9 L8
ZQ/ZQ0 VSS
T9 CMD10 A1 A2
CMD25 A10 WE#
1
1
J1 B1 J1 B1
NC/ODT1 VSSQ NC/ODT1 VSSQ
1
RV87 RV88 L1
NC/CS1 VSSQ
B9 RV89 L1
NC/CS1 VSSQ
B9 CMD9 A12 A0
243_0402_1% J9 D1 243_0402_1% J9 D1
NC/CE1 VSSQ NC/CE1 VSSQ
10K_0402_5% L9
NCZQ1 VSSQ
D8 L9
NCZQ1 VSSQ
D8 CMD1 CS1#_L
8PCS@ E2 8PCS@ E2
2
2
VSSQ VSSQ
8PCS@ E8 E8 CMD11 RAS# RAS#
2
VSSQ VSSQ
F9 F9
VSSQ VSSQ
VSSQ
G1
VSSQ
G1 CMD0 ODT_L
G9 G9
B VSSQ VSSQ B
CMD5 A6 A7
96-BALL 96-BALL
SDRAM DDR3 SDRAM DDR3 CMD16 CKE_H
H5TQ2G63BFR-11C FBGA 96P H5TQ2G63BFR-11C FBGA 96P
@ @ CMD20 RST RST
Under UV9(below 150mils) Under UV10(below 150mils)
CMD14 A14 A13
+VRAM_1.5VS +VRAM_1.5VS
CMD30 A15 BA2
1U_0402_6.3V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 1U_0402_6.3V4Z 1U_0402_6.3V4Z 1U_0402_6.3V4Z 1U_0402_6.3V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 1U_0402_6.3V4Z 1U_0402_6.3V4Z 1U_0402_6.3V4Z
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
CV200 CV201 CV202 CV203 CV204 CV205 CV206 CV207 CV208 CV209 CV210 CV211 CV212 CV213 CV214 CV215 CV216 CV217 CV218 CV219 CV220 CV221 CV222 CV223
8PCS@ 8PCS@ 8PCS@ 8PCS@ 8PCS@ 8PCS@ 8PCS@ 8PCS@ 8PCS@ 8PCS@ 8PCS@ 8PCS@ 8PCS@ 8PCS@ 8PCS@ 8PCS@ 8PCS@ 8PCS@ 8PCS@ 8PCS@ 8PCS@ 8PCS@ 8PCS@ 8PCS@
2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2
1U_0402_6.3V4Z 1U_0402_6.3V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 1U_0402_6.3V4Z 1U_0402_6.3V4Z 1U_0402_6.3V4Z 1U_0402_6.3V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 1U_0402_6.3V4Z 1U_0402_6.3V4Z
A A
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2010/12/03 Deciphered Date 2011/12/03 Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
VGA(10/12)-VRAM C Lower
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom 0.3
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
PBL80 LA-7441P M/B
Date: Monday, April 11, 2011 Sheet 23 of 59
5 4 3 2 1
5 4 3 2 1
Memory Partition C - Upper 32 bits MDB[0..63] <20,23>
CMDB[30..0] <20,23>
UV11 UV12
+VRAM_1.5VS +FBB_VREF1 MDB39 +FBB_VREF1 MDB56 DQMB[7..0] <20,23>
M8 E3 M8 E3
VREFCA DQL0 MDB33 VREFCA DQL0 MDB63
H1 F7 H1 F7 DQSB[7..0] <20,23>
VREFDQ DQL1 MDB38 VREFDQ DQL1 MDB57
F2 F2
DQL2 DQL2
1
D CMDB9 MDB32 CMDB9 MDB60 D
N3 F8 N3 F8 DQSB#[7..0] <20,23>
CMDB24 A0 DQL3 MDB36 CMDB24 A0 DQL3 MDB59
RV90 P7
A1 DQL4
H3 Group4 P7
A1 DQL4
H3 Group7
CMDB10 P3 H8 MDB34 CMDB10 P3 H8 MDB61
1.1K_0402_1% CMDB13 A2 DQL5 MDB37 CMDB13 A2 DQL5 MDB58
N2 G2 N2 G2
8PCS@ CMDB26 A3 DQL6 MDB35 CMDB26 A3 DQL6 MDB62
P8 H7 P8 H7
2
+FBB_VREF1 CMDB22 A4 DQL7 CMDB22 A4 DQL7
P2 P2
CMDB21 A5 CMDB21 A5
R8
A6
R8
A6 Mode E - Mirror Mode Mapping
1
1 CMDB5 R2 D7 MDB42 CMDB5 R2 D7 MDB48
RV91 CV224 CMDB8 A7 DQU0 MDB43 CMDB8 A7 DQU0 MDB55
T8 C3 T8 C3
A8 DQU1 A8 DQU1
0.01U_0402_25V7K CMDB23 R3
A9 DQU2
C8 MDB41 CMDB23 R3
A9 DQU2
C8 MDB49 DATA Bus
1.1K_0402_1% 8PCS@ CMDB28 L7 C2 MDB46 CMDB28 L7 C2 MDB52
2 CMDB4 A10/AP DQU3 MDB40 CMDB4 A10/AP DQU3 MDB51
8PCS@ R7 A7 Group5 R7 A7 Group6 Address 0..31 32..63
2
CMDB7 A11 DQU4 MDB45 CMDB7 A11 DQU4 MDB54
N7 A12 DQU5 A2 N7 A12 DQU5 A2
CMDB14 T3 A13 DQU6 B8 MDB44 CMDB14 T3 A13 DQU6 B8 MDB50 CMD3 CKE_L
CMDB12 T7 A3 MDB47 CMDB12 T7 A3 MDB53
A14 DQU7 A14 DQU7
CMDB27 M7 A15/BA3
CMDB27 M7 A15/BA3 CMD8 A8 A8
+VRAM_1.5VS +VRAM_1.5VS
CMD2 CS0#_L
CMDB29 M2 B2 CMDB29 M2 B2
BA0 VDD BA0 VDD
CMDB6 N8 BA1 VDD D9 CMDB6 N8 BA1 VDD D9 CMD21 A7 A6
CMDB30 M3 G7 CMDB30 M3 G7
CLKB1 BA2 VDD BA2 VDD
VDD K2 VDD K2 CMD24 A2 A1
VDD K8 VDD K8
VDD N1 VDD N1 CMD23 A11 A9
2
CLKB1 J7 N9 CLKB1 J7 N9
<20> CLKB1 CK VDD CK VDD
RV92
<20> CLKB1#
CLKB1# K7 CK VDD R1 CLKB1# K7 CK VDD R1 CMD26 A5 A4
160_0402_1% CMDB16 K9 R9 CMDB16 K9 R9
CKE/CKE0 VDD CKE/CKE0 VDD
CMD7 A0 A12
8PCS@
1
CMDB19 K1 ODT/ODT0 VDDQ A1 CMDB19 K1 ODT/ODT0 VDDQ A1 CMD15 CAS# CAS#
CLKB1# CMDB18 L2 A8 CMDB18 L2 A8
CMDB11 CS/CS0 VDDQ CMDB11 CS/CS0 VDDQ
C
J3 RAS VDDQ C1 J3 RAS VDDQ C1 CMD13 BA1 A3 C
CMDB15 K3 C9 CMDB15 K3 C9
CAS VDDQ CAS VDDQ
CMDB25 L3
WE VDDQ D2 CMDB25 L3
WE VDDQ D2 CMD4 A9 A11
VDDQ E9 VDDQ E9
VDDQ F1 VDDQ F1 CMD18 CS0#_H
DQSB4 F3 H2 DQSB7 F3 H2
DQSL VDDQ DQSL VDDQ
DQSB5 C7 DQSU VDDQ H9 DQSB6 C7 DQSU VDDQ H9 CMD29 BA0 BA0
CMD27 BA2 A15
DQMB4 E7 A9 DQMB7 E7 A9
DQMB5 DML VSS DQMB6 DML VSS
D3
DMU VSS
B3 D3
DMU VSS
B3 CMD6 A3 BA1
CMDB16 E1 E1
VSS VSS
VSS
G8
VSS
G8 CMD17 CS1#_H
DQSB#4 G3 J2 +VRAM_1.5VS DQSB#7 G3 J2
DQSL VSS DQSL VSS
CMDB19 DQSB#5 B7
DQSU VSS
J8 DQSB#6 B7
DQSU VSS
J8 CMD19 ODT_H
M1 1 M1
VSS VSS
VSS
M9
VSS
M9 CMD22 A4 A5
2
P1 + CV225 P1
VSS VSS
RV93 RV94 CMDB20 T2 RESET VSS
P9 330U_B2_2.5VM_R15M CMDB20 T2 RESET VSS
P9 CMD12 A13 A14
10K_0402_5% 10K_0402_5% T1 8PCS@ T1
VSS 2 VSS
8PCS@ 8PCS@ L8
ZQ/ZQ0 VSS
T9 L8
ZQ/ZQ0 VSS
T9 CMD28 WE# A10
1
CMD10 A1 A2
1
1
J1 B1 J1 B1
NC/ODT1 VSSQ NC/ODT1 VSSQ
RV95 L1
NC/CS1 VSSQ
B9 RV96 L1
NC/CS1 VSSQ
B9 CMD25 A10 WE#
243_0402_1% J9 D1 243_0402_1% J9 D1
NC/CE1 VSSQ NC/CE1 VSSQ
L9
NCZQ1 VSSQ
D8 L9
NCZQ1 VSSQ
D8 CMD9 A12 A0
8PCS@ E2 8PCS@ E2
2
2
VSSQ VSSQ
VSSQ
E8
VSSQ
E8 CMD1 CS1#_L
F9 F9
VSSQ VSSQ
VSSQ
G1
VSSQ
G1 CMD11 RAS# RAS#
G9 G9
VSSQ VSSQ
B
CMD0 ODT_L B
96-BALL 96-BALL
SDRAM DDR3 SDRAM DDR3 CMD5 A6 A7
H5TQ2G63BFR-11C FBGA 96P H5TQ2G63BFR-11C FBGA 96P
@ @ CMD16 CKE_H
Under UV11(below 150mils) Under UV12(below 150mils)
CMD20 RST RST
+VRAM_1.5VS
+VRAM_1.5VS CMD14 A14 A13
1U_0402_6.3V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 1U_0402_6.3V4Z 1U_0402_6.3V4Z 1U_0402_6.3V4Z
1U_0402_6.3V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 1U_0402_6.3V4Z 1U_0402_6.3V4Z 1U_0402_6.3V4Z CMD30 A15 BA2
1 1 1 1 1 1 1 1 1 1 1 1
1 1 1 1 1 1 1 1 1 1 1 1 CV238 CV239 CV240 CV241 CV242 CV243 CV244 CV245 CV246 CV247 CV248 CV249
CV226 CV227 CV228 CV229 CV230 CV231 CV232 CV233 CV234 CV235 CV236 CV237
8PCS@ 8PCS@ 8PCS@ 8PCS@ 8PCS@ 8PCS@ 8PCS@ 8PCS@ 8PCS@ 8PCS@ 8PCS@ 8PCS@
8PCS@ 8PCS@ 8PCS@ 8PCS@ 8PCS@ 8PCS@ 8PCS@ 8PCS@ 8PCS@ 8PCS@ 8PCS@ 8PCS@ 2 2 2 2 2 2 2 2 2 2 2 2
2 2 2 2 2 2 2 2 2 2 2 2 1U_0402_6.3V4Z 1U_0402_6.3V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 1U_0402_6.3V4Z 1U_0402_6.3V4Z
1U_0402_6.3V4Z 1U_0402_6.3V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 1U_0402_6.3V4Z 1U_0402_6.3V4Z
A A
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2010/12/03 Deciphered Date 2011/12/03 Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
VGA(11/12)-VRAM C Upper
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
WWW.AliSaler.Com
Custom 0.3
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
PBL80 LA-7441P M/B
Date: Monday, April 11, 2011 Sheet 24 of 59
5 4 3 2 1
5 4 3 2 1
+3VS_DGPU
2
RV97 @ @ @ @
45.3K_0402_1% RV98 RV99 RV131 RV120 Physical Logical Logical Logical Logical
34.8K_0402_1% 15K_0402_1% 4.99K_0402_1% 34.8K_0402_1%
Strapping pin Power Rail Strapping Bit3 Strapping Bit2 Strapping Bit1 Strapping Bit0
D D
1
ROM_SO +3VS XCLK_417 FB_0_BAR_SIZE SMB_ALT_ADDR VGA_DEVICE
STRAP0
<15> STRAP0
<15> STRAP1
STRAP1 ROM_SCLK +3VS PCI_DEVID[4] SUB_VENDOR SLOT_CLK_CFG PEX_PLLEN_TERM
<15> STRAP2 STRAP2
<15> STRAP3 STRAP3 ROM_SI +3VS RAMCFG[3] RAMCFG[2] RAMCFG[1] RAMCFG[0]
STRAP4
<15> STRAP4
STRAP2 +3VS PCI_DEVID[3] PCI_DEVID[2] PCI_DEVID[1] PCI_DEVID[0]
STRAP1 +3VS 3GIO_PADCFG[3] 3GIO_PADCFG[2] 3GIO_PADCFG[1] 3GIO_PADCFG[0]
2
2
STRAP0 +3VS USER[3] USER[2] USER[1] USER[0]
@ RV101 RV103 RV130 RV119
RV100 34.8K_0402_1% 4.99K_0402_1% 4.99K_0402_1% 10K_0402_1%
45.3K_0402_1% N12PGV@ N12PGV@ N12PGV@
1
1
Resistor Values Pull-up to +3VS Pull-down to Gnd
5K 1000 0000
N12PGS@ 10K 1001 0001
RV103
24.9K 0402_1% 15K 1010 0010
20K 1011 0011
+3VS 25K 1100 0100
30K 1101 0101
35K 1110 0110
2
2
C C
45K 1111 0111
RV105 RV106 N12PGS@
@ RV104 10K_0402_1% 4.99K_0402_1% RV106
4.99K_0402_1% N12PGV@ N12PGV@ 15K +-1% 0402
1
ROM_SI
<15> ROM_SI
ROM_SO
<15> ROM_SO
ROM_SCLK
<15> ROM_SCLK
2
RV108 @
X76 @ RV109 RV110
45.3K_0402_1% 10K_0402_1% 15K_0402_1% SUB_VENDOR XCLK_417
See below Table N12PGS@
1
0 No VBIOS ROM 0 277MHz (Default)
1
1 BIOS ROM is present (Default) 1 Reserved
GPU DeviceID ROM_SI ROM_SCLK ROM_SO STRAP0 FB_0_BAR_SIZE USER Straps
N12P-GS 0x0DF4 Below Table Pull up 15K Pull down 10K Pull up 45K 0 256MB (Default) User[3:0]
B
N12P-GV 0x1050 Below Table Pull up 5K Pull up 10K Pull up 45K 1 Reserved 1000-1100 Customer defined B
GPU DeviceID STRAP1 STRAP2 STRAP3 STRAP4 3GIO_PADCFG PEX_PLL_EN_TERM
N12P-GS 0x0DF4 Pull down 35K Pull down 25K 3GIO_PADCFG[3:0] 0 Disable (Default)
N12P-GV 0x1050 Pull down 35K Pull down 5K Pull down 5K Pull down 10K 0110 Notebook Default 1 Enable
SLOT_CLK_CFG
GPU DDR3 Type VRAM RAMCFG[3..0] RV108 0 GPU and MCH don't share a common reference clock
Hynix H5TQ1G63DFR-11C 512MB 0010 PD 15K SD034154280
64M16 SA000041S20 1GB 0010 PD 15K SD034154280 1 GPU and MCH share a common reference clock (Default)
900MHz Samsung K4W1G1646E-HC11 512MB 0011 PD 20K SD034200280
SA000041T00 1GB 0011 PD 20K SD034200280
SMBUS_ALT_ADDR VGA_DEVICE
N12P-GS 1GB 0110 PD 34.8K SD034348280 0 0x9E (Default) 0 3D Device
Hynix H5TQ2G63BFR-11C
128M16 SA00003YO00 2GB 0110 PD 34.8K SD034348280
1 0x9C (Multi-GPU usage) 1 VGA Device (Default)
900MHz Samsung K4W2G1646C-HC11 1GB 0111 PD 45.3K SD034453280
SA000047Q00 2GB 0111 PD 45.3K SD034453280
A A
Hynix H5TQ1G63DFR-12C
512MB 0010 PD 15K SD034154280
64M16 SA0000324C0
800MHz Samsung K4W1G1646G-BC12
512MB 0011 PD 20K SD034200280
SA00004HS00
N12P-GV Security Classification Compal Secret Data Compal Electronics, Inc.
Hynix H5TQ2G63BFR-12C
1GB 0110 PD 34.8K SD034348280 Issued Date 2010/12/03 Deciphered Date 2011/12/03 Title
128M16 SA00003VS00 VGA(12/12)-MISC
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
800MHz Samsung K4W2G1646C-HC12
1GB 0111 PD 45.3K SD034453280
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number
Custom
Rev
0.3
SA00003MQ40
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
PBL80 LA-7441P M/B
Date: Monday, April 11, 2011 Sheet 25 of 59
5 4 3 2 1
5 4 3 2 1
D1 D4
CRT_B_L 2 HSYNC 2
1 1
CRT_G_L 3 VSYNC 3
YSDA0502C 3P C/A SOT-23 YSDA0502C 3P C/A SOT-23
D11
D2 CRT_DDC_DAT 2
CRT_R_L 2 1
1 CRT_DDC_CK 3
+CRT_VCC 3
D YSDA0502C 3P C/A SOT-23 D
YSDA0502C 3P C/A SOT-23
ESD
NBQ100505T-800Y_0402
L1
1 2 CRT_R_L
<32> VGA_CRT_R
NBQ100505T-800Y_0402
L2
1 2 CRT_G_L
<32> VGA_CRT_G
NBQ100505T-800Y_0402
L3
1 2 CRT_B_L
<32> VGA_CRT_B
2.2P_0402_50V8C
2.2P_0402_50V8C
2.2P_0402_50V8C
2.2P_0402_50V8C
2.2P_0402_50V8C
2.2P_0402_50V8C
150_0402_1%
150_0402_1%
150_0402_1%
1 1 1 1 1 1
1
1
R110 R111 R112 C173 C174 C175 C176 C177 C178
2 2 2 2 2 2
2
2 +3VS
+CRT_VCC
C C
2
R114
R113
4.7K_0402_5%
4.7K_0402_5%
1
1
+5VS
2
Q31A
1 6 CRT_DDC_DAT D3 +CRT_VCC_R +CRT_VCC
<32> VGA_CRT_DATA
2 F1 40mil
5
2N7002DW-T/R7_SOT363-6 1 1 2
Q31B 3 RB491D_SOT23-3 1
<32> VGA_CRT_CLK 4 3 CRT_DDC_CK 1.1A_6V_MINISMDC110F-2
1 1 If=1A C179 @
1 1 2N7002DW-T/R7_SOT363-6 0.1U_0402_16V4Z
@ C182 @ C183 2
@ C180 @ C181 470P_0402_50V8J 470P_0402_50V8J
33P_0402_50V8K 33P_0402_50V8K 2 2
2 2
CRT CONNECTOR
+CRT_VCC
R115 10K_0402_5% JCRT
B B
1 2 2 1 6
C184 T21 11
5
1
0.1U_0402_16V4Z @ CRT_R_L 1
7
OE#
P
2 4 D_CRT_HSYNC 1 2 HSYNC CRT_DDC_DAT 12
<32> VGA_CRT_HSYNC A Y CRT_G_L
L4 10_0402_5% 2
G
U4 8
SN74AHCT1G125GW_SOT353-5 HSYNC 13
3
+CRT_VCC 40mil CRT_B_L 3
+CRT_VCC 9
VSYNC 14
1 2 T22 4
C185 @ 10 G 16
5
1
0.1U_0402_16V4Z CRT_DDC_CK 15 G 17
5
OE#
P
2 4 D_CRT_VSYNC1 2 VSYNC
<32> VGA_CRT_VSYNC A Y L5 10_0402_5% SUYIN_070546HR015M22BZR
G
U5 10P_0402_50V8J @
10P_0402_50V8J
SN74AHCT1G125GW_SOT353-5
3
1 1
@ C186
@C186 @ C187
2 2
A A
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2010/12/03 Deciphered Date 2011/12/03 Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
CRT
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
WWW.AliSaler.Com
0.3
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
PBL80 LA-7441P M/B
Date: Monday, April 11, 2011 Sheet 26 of 59
5 4 3 2 1
5 4 3 2 1
+LCD_VDD
1
R119
300_0603_5% +3VS
+3VS
6 2
D20 @ Vds=-20V
1
D LCD_BL_PWM D
2 1 2 1 +3VS
<43> INVT_PWM Id=-3A
RB751V40_SC76-2 R117 4.7K_0402_5% Q32A R121 2 Rds=130m ohm
R118 2 1 2N7002DW-T/R7_SOT363-6 2 100K_0402_5% C189
<32> VGA_BL_PWM
0_0402_5% 0.1U_0402_16V7K Vgs=-4.5
1
2
S
3
Vth=-1
1
R120 C188 1 2 1 2
G
Q7
3
4.7K_0402_5% @ 180P_0402_50V8J R123 47K_0402_5% AO3413_SOT23
2 D
2
1
Q32B C190
2
5 0.01U_0402_25V7K +LCD_VDD
<32> VGA_ENVDD
1
2N7002DW-T/R7_SOT363-6 1
W=120mils
4
D19
BKOFF# 2 1 BKOFF#_R R130 1 1
<43> BKOFF#
100K_0402_5% 1 1
1
@ C193 C194 C191 C192
2
RB751V40_SC76-2
R122 4.7U_0805_10V4Z 0.1U_0402_16V4Z
10K_0402_5% 2 2 4.7U_0805_10V4Z 0.1U_0402_16V4Z
2 2
2
Close to JLVDS
C195 +3VS
0.1U_0402_16V4Z
C C
1 2
W=20mils
Dual Channel LVDS JLVDS
Support 18.4" HD/FHD 16:9 USB20_N10_R
USB20_P10_R
2
4
6
2
4
1
3
1
3
5
LCD_TXCLK+ <32>
DMIC_CLK 6 5 LCD_TXCLK- <32>
<42> DMIC_CLK 8 7
DMIC_DATA 8 7
<42> DMIC_DATA 10 9 LCD_TZCLK- <32>
10 9
12 11 LCD_TZCLK+ <32>
12 11
<32> LCD_TXOUT0+ 14 13
14 13
<32> LCD_TXOUT0- 16 15 LCD_EDID_CLK <32>
16 15
<32> LCD_TXOUT1+ 18 17 LCD_EDID_DATA <32>
18 17 LCD_BL_PWM
<32> LCD_TXOUT1- 20 19
20 19
<32> LCD_TXOUT2+ 22 21 +3VS
22 21
<32> LCD_TXOUT2- 24 23 1 1
24 23
1
26
26 25
25 W=120mils
<32> LCD_TZOUT0+ 28 27
28 27 +LCD_VDD @ R127
<32> LCD_TZOUT0- 30 29
30 29 BKOFF#_R 2 2 100K_0402_5%
<32> LCD_TZOUT1+ 32 31
32 31
34 33
2
<32> LCD_TZOUT1- 34 33
<32> LCD_TZOUT2+ 36 35
36 35
<32> LCD_TZOUT2- 38 37
38 37
40 39 +LCD_INV
40 39 C306 C197
42 41
GND GMD 1U_0603_10V6K 0.1U_0402_16V4Z
W=60mils
ACES_87242-4001-09
@
B
LCD/PANEL BD. Conn. B
B+
L6
2 1
FBMA-L11-201209-221LMA30T_0805
1 1 1
C198 C199 @ C200
68P_0402_50V8J 0.1U_0402_25V4K 680P_0402_50V7K
2 2 2
Rated Current MAX:3000mA
1 2 R137 USB20_P10_R
<33> USB20_P10
0_0402_5%
1 2 D17
1 2 DMIC_DATA USB20_P10_R
6 3
@ L7 I/O4 I/O2
4 3
4 3
WCM-2012-121T_0805 +3VS 5 2
USB20_N10_R VDD GND
<33> USB20_N10 1 2 R142
0_0402_5%
DMIC_CLK 4 1 USB20_N10_R
I/O3 I/O1
AZC099-04S.R7G_SOT23-6
@
A A
ESD
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2010/12/03 Deciphered Date 2011/12/03 Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
LVDS
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
0.3
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
PBL80 LA-7441P M/B
Date: Monday, April 11, 2011 Sheet 27 of 59
5 4 3 2 1
5 4 3 2 1
D
NV review, request for LC filter at HPD at 12/17. D
R979 L88
+5VS_HDMI 10K_0402_5% BLM18PG181SN1D_0603
<14> HDMI_HPD 1 2 2 1 HDMI_HPD_C
40mil
1
1
100K_0402_5%
R980
1.1A_6V_MINISMDC110F-2
2
G
RB161M-20_SOD123-2 D5 F2 D34
+5VS 2 1 2 1 +HDMI_5V_OUT BAV99_SOT23-3
1 1 3 1 DGPU_HPD_INT# <34>
C319 C201
D
2
3
Q65
0.1U_0402_16V4Z 0.1U_0402_16V4Z +3VS_DGPU 2N7002E-T1-GE3_SOT23-3
2 2
ESD, near D5.
+3VS_DGPU +HDMI_5V_OUT
HDMI Connector
1
R150 R151
2
4.7K_0402_5% 4.7K_0402_5%
G
JHDMI
HDMI_HPD_C 19
2
C HDMI_SCLK HP_DET C
<15> VGA_HDMI_CLK 3 1 +HDMI_5V_OUT 18 +5V
17 DDC/CEC_GND
2
S G
D
Q9 HDMI_SDATA 16
BSH111_SOT23-3 HDMI_SCLK SDA
15 SCL
VGA_DVI_TXC+ 1 @ 2 R152 HDMI_R_CK+ 14
HDMI_SDATA 0_0402_5% Reserved
<15> VGA_HDMI_DATA 3 1 13 CEC
L8 HDMI_R_CK- 12 20
CK- GND
S
Q10 1 2 11 21
BSH111_SOT23-3 1 2 HDMI_R_CK+ CK_shield GND
10 22
HDMI_R_D0- CK+ GND
9 23
D0- GND
4 3 8
4 3 HDMI_R_D0+ D0_shield
7
WCM-2012-900T HDMI_R_D1- D0+
6
VGA_DVI_TXC- HDMI_R_CK- D1-
1 2 R153 5
@ 0_0402_5% HDMI_R_D1+ D1_shield
4
VGA_HDMI_CLK- CV250 1 VGA_DVI_TXC- HDMI_R_D2- D1+
<15> VGA_HDMI_CLK- 2 0.1U_0402_16V7K 3
VGA_HDMI_TX0- CV251 1 VGA_DVI_TXD0- D2-
<15> VGA_HDMI_TX0- 2 0.1U_0402_16V7K 2
VGA_HDMI_TX1- CV252 1 VGA_DVI_TXD1- VGA_DVI_TXD0+ HDMI_R_D0+ HDMI_R_D2+ D2_shield
<15> VGA_HDMI_TX1- 2 0.1U_0402_16V7K 1 @ 2 R154 1
D2+
<15> VGA_HDMI_TX2- VGA_HDMI_TX2- CV253 1 2 0.1U_0402_16V7K VGA_DVI_TXD2- 0_0402_5%
L9 LOTES_ABA-HDM-022-K01
1 2 @
VGA_HDMI_CLK+ CV254 1 VGA_DVI_TXC+ 1 2
<15> VGA_HDMI_CLK+ 2 0.1U_0402_16V7K
<15> VGA_HDMI_TX0+ VGA_HDMI_TX0+ CV255 1 2 0.1U_0402_16V7K VGA_DVI_TXD0+
<15> VGA_HDMI_TX1+ VGA_HDMI_TX1+ CV256 1 2 0.1U_0402_16V7K VGA_DVI_TXD1+ 4 3
VGA_HDMI_TX2+ CV257 1 VGA_DVI_TXD2+ 4 3
<15> VGA_HDMI_TX2+ 2 0.1U_0402_16V7K
WCM-2012-900T
VGA_DVI_TXD0- 1 2 R156 HDMI_R_D0-
@ 0_0402_5%
HDMI_R_CK+ 1 2
R155 499_0402_1%
VGA_DVI_TXD1+ 1 @ 2 R159 HDMI_R_D1+ HDMI_R_CK- 1 2
B 0_0402_5% R157 499_0402_1% B
L10 HDMI_R_D1- 1 2
1 2 R158 499_0402_1%
1 2 HDMI_R_D1+ 1 2
R160 499_0402_1%
4 3 HDMI_R_D0- 1 2
4 3 R161 499_0402_1%
WCM-2012-900T HDMI_R_D0+ 1 2
VGA_DVI_TXD1- 1 2 R165 HDMI_R_D1- R162 499_0402_1%
D16 @ 0_0402_5% HDMI_R_D2+ 1 2
HDMI_HPD_C 6 3 HDMI_SDATA R163 499_0402_1%
I/O4 I/O2 HDMI_R_D2- 1 2
VGA_DVI_TXD2+ 1 @ 2 R166 HDMI_R_D2+ R164 499_0402_1%
1
0_0402_5% D
+5VS 5 2 L11 +5VS 2 Q11
VDD GND G 2N7002_SOT23-3
1 2
1 2
S
3
1 2
4 1 HDMI_SCLK 4 3 1 R167 100K_0402_5%
+HDMI_5V_OUT I/O3 I/O1 4 3 C203
AZC099-04S.R7G_SOT23-6 WCM-2012-900T
VGA_DVI_TXD2- 2 R168 HDMI_R_D2- 0.1U_0402_16V4Z
For ESD request. 1
@ 0_0402_5% 2
D12 D13
HDMI_R_CK- 1 1 109 HDMI_R_CK- HDMI_R_D1- 1 1 109 HDMI_R_D1-
HDMI_R_CK+ 2 2 98 HDMI_R_CK+ HDMI_R_D1+ 2 2 98 HDMI_R_D1+
A A
HDMI_R_D0- 4 4 77 HDMI_R_D0- HDMI_R_D2- 4 4 77 HDMI_R_D2-
HDMI_R_D0+ 5 5 66 HDMI_R_D0+ HDMI_R_D2+ 5 5 66 HDMI_R_D2+
3 3 3 3
8 8
Security Classification Compal Secret Data Compal Electronics, Inc.
L15ESDL5V0NA-4 SLP2510P8 L15ESDL5V0NA-4 SLP2510P8 Issued Date 2010/12/03 2011/12/03 Title
Deciphered Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
HDMI Connector
Size Document Number Rev
For ESD request. AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
WWW.AliSaler.Com
0.3
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
PBL80 LA-7441P M/B
Date: Monday, April 11, 2011 Sheet 28 of 59
5 4 3 2 1
5 4 3 2 1
CMOS Setting, near DDR Door JCMOS @
R169 1 2 PCH_RTCRST# 1 2
+RTCVCC
20K_0402_5% SHORT PADS
C206 1 2
1U_0402_6.3V4Z UPCHA
C204 18P_0402_50V8J
2 1 PCH_RTCX1 A20 C38
RTCX1 FWH0 / LAD0 LPC_AD0 <43>
iME Setting. A38
LPC
PCH_RTCX2 FWH1 / LAD1 LPC_AD1 <43>
JME @ Y1 C20 B37
RTCX2 FWH2 / LAD2 LPC_AD2 <43>
1
10M_0402_5%
R173 1 2 PCH_SRTCRST# 1 2 2 1 C37 LPC_AD3 <43>
20K_0402_5% SHORT PADS NC OSC PCH_RTCRST# FWH3 / LAD3
D20
RTCRST#
R170
C205 1 2 3 4 D36
NC OSC FWH4 / LFRAME# LPC_FRAME# <43>
1U_0402_6.3V4Z PCH_SRTCRST# G22
D 32.768KHZ_12.5PF_Q13MC14610002 SRTCRST# D
E36
RTC
2
SM_INTRUDER# LDRQ0#
2 1 K22
INTRUDER# LDRQ1# / GPIO23
K36 2 1 +3VS
R171 10K_0402_5%
C207 18P_0402_50V8J PCH_INTVRMEN C17 V5
INTVRMEN SERIRQ SERIRQ <43>
Integrated SUS 1.05V VRM Enable
High - Enable Internal VRs AM3 SATA_PRX_C_DTX_N0 NB HDD 3.5"
AZ_BITCLK SATA0RXN SATA_PRX_C_DTX_P0 SATA_PRX_C_DTX_N0 <38>
PCH_INTVRMEN (must be always pulled high) R172 1 2 33_0402_5% N34 AM1
<42> AZ_BITCLK_HD HDA_BCLK SATA0RXP SATA_PRX_C_DTX_P0 <38>
SATA 6G
AP7 SATA_PTX_DRX_N0
SATA0TXN SATA_PTX_DRX_N0 <38>
AZ_SYNC L34 AP5 SATA_PTX_DRX_P0
HDA_SYNC SATA0TXP SATA_PTX_DRX_P0 <38>
+RTCVCC PCH_SPKR T10 AM10 SATA_PRX_C_DTX_N1
SPKR SATA1RXN SATA_PRX_C_DTX_P1 SATA_PRX_C_DTX_N1 <38>
SM_INTRUDER# AZ_RST# SATA1RXP AM8
SATA_PTX_DRX_N1
SATA_PRX_C_DTX_P1 <38> NB HDD 2.5"
R175 1 2 R174 1 2 33_0402_5% K34 AP11
<42> AZ_RST_HD# HDA_RST# SATA1TXN SATA_PTX_DRX_P1 SATA_PTX_DRX_N1 <38>
1M_0402_5% AP10
SATA1TXP SATA_PTX_DRX_P1 <38>
R176 1 2 PCH_INTVRMEN
330K_0402_5% AZ_SDIN0_HD E34 AD7 SATA_PRX_C_DTX_N2
<42> AZ_SDIN0_HD HDA_SDIN0 SATA2RXN SATA_PRX_C_DTX_N2 <38>
AD5 SATA_PRX_C_DTX_P2 NB ODD
SATA2RXP SATA_PTX_DRX_N2 SATA_PRX_C_DTX_P2 <38>
G34 HDA_SDIN1 SATA2TXN AH5 SATA_PTX_DRX_N2 <38>
+3VS AH4 SATA_PTX_DRX_P2
SATA2TXP SATA_PTX_DRX_P2 <38>
C34
IHDA
HDA_SDIN2
SATA3RXN AB8
1 2 PCH_SPKR A34 AB10
R412 @ 1K_0402_5% HDA_SDIN3 SATA3RXP
SATA3TXN AF3
SATA3TXP AF1
AZ_SDOUT A36
SATA
HDA_SDO
High = Enable ( No Reboot ) SATA4RXN Y7
PCH_SPKR Low = Disabled (Default) SATA4RXP Y5
* C36 HDA_DOCK_EN# / GPIO33 SATA4TXN
SATA4TXP
AD3
AD1
N32 HDA_DOCK_RST# / GPIO13
SATA5RXN Y3
C +3VS Y1 C
R177 0_0402_5% SATA5RXP
SATA5TXN AB3
PCH_JTAG_TCK_R 2 1 PCH_JTAG_TCK J3 AB1
PCH_SPI_MOSI R179 0_0402_5% JTAG_TCK SATA5TXP
1 2
R178 @ 1K_0402_5% PCH_JTAG_TMS_R 2 1 PCH_JTAG_TMS H7 Y11 R181 +RTCBATT
JTAG
R180 0_0402_5% JTAG_TMS SATAICOMPO 37.4_0402_1%
PCH_JTAG_TDI_R 2 1 PCH_JTAG_TDI K5 Y10 SATAICOMP 1 2 +1.05VS_VCC_SATA
R182 0_0402_5% JTAG_TDI SATAICOMPI
1
ITPM Enabled Internal: Pull down 20k PCH_JTAG_TDO_R 2 1 PCH_JTAG_TDO H1 @
JTAG_TDO RH8 JRTC
AB12
+
SATA3RCOMPO 49.9_0402_1%
High = Enabled
SPI_MOSI AB13 SATA3_COMP 1 2
Low = Disabled (Default) SATA3COMPI +1.05VS_SATA3
*
PCH_SPI_CLK T3 AH1 RBIAS_SATA3 1 2
<41> PCH_SPI_CLK SPI_CLK SATA3RBIAS RH9 750_0402_1%
PCH_SPI_CS0# Y14
HDA_SYNC HDA_SDO <41> PCH_SPI_CS0# SPI_CS0#
1 2 +3VS
This signal has a weak internal pull down. This signal has a weak internal T1 R184 10K_0402_5%
SPI
SPI_CS1#
*H=>On
L=>On
Die PLL is supplied by 1.5V
Die PLL is supplied by 1.8V pull down. SATALED#
P3
SATA_LED# <39> LOTES_AAA-BAT-054-K01
-
This signal can't PU PCH_SPI_MOSI V4 V14 PCH_GPIO21
2
<41> PCH_SPI_MOSI SPI_MOSI SATA0GP / GPIO21
PCH_SPI_MISO U3 P1 BBS_BIT0_R 2 1 +3VS
<41> PCH_SPI_MISO SPI_MISO SATA1GP / GPIO19
+3VALW_PCH 2 1 AZ_SYNC R185 10K_0402_5%
R186 1K_0402_5% @ R187
1K_0402_5% COUGARPOINT_FCBGA989~D
+3VS 2 1 AZ_SDOUT HM65@
+3VALW_PCH
BSS138_NL_SOT23-3
2
G
R188 Q12 R189
33_0402_5% 1 2
<42> AZ_SDOUT_HD
<42> AZ_SYNC_HD 1 2 AZ_SYNC_R 3 1
B 33_0402_5% PCH_GPIO21 B
S
2 1 +3VS
2 1 R190 10K_0402_5%
<43> AZ_SDO
2 1 1 2 R191 @ JXDP2 2 1
0_0402_5% 1 @ R192 10K_0402_5%
R193 @ R194 1
2
1M_0402_5% 0_0402_5% 2
3
3
4
4
5
5
6
6
XDP Connector
7
7
0604 CHANG AZ_SYNC AND AZ_SDOUT TO FIT INTEL SPEC R195 8
8 W=20mils
0_0402_5% 9
9
Place near PCH
2 @ 1 XDP_PCH_RSMRST# 10
<31,43> PCH_RSMRST# 10
+3VALW_PCH +3VALW_PCH +3VALW_PCH 1 @ 2 XDP_PCH_HOOK1 11 +RTCBATT_R 1 R204 2
<5,31,43> PBTN_OUT# 11 +RTCBATT
R196 0_0402_5% 12 1K_0402_5%
12
1
13
13
1
+1.05VS_VCCP 1 @ 2 14
R197 0_0402_5% 14 D6
R198 R199 15
200_0402_5% 15 BAS40-04_SOT23-3
200_0402_5% 200_0402_5% +3VS 16
R200 16 +RTCVCC
17
XDP_DBRESET# 17 W=20mils
18
2
2
PCH_JTAG_TMS PCH_JTAG_TDO PCH_JTAG_TDI <5,31> XDP_DBRESET# 18
19 +CHGRTC
PCH_JTAG_TDO_R 19
20 1
20
1
21 W=10mils
PCH_JTAG_TDI_R 21 C209
R201 R202 22
100_0402_1% PCH_JTAG_TMS_R 22 0.1U_0402_16V4Z
100_0402_1% 100_0402_1% 23
R203 23 2
24
24
25 27
2
PCH_JTAG_TCK_R 25 G1
26 28
26 G2
ACES_87152-26051
A A
1 2 PCH_JTAG_TCK
R205 51_0402_1%
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2010/12/03 Deciphered Date 2011/12/03 Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Cougar Point(1/9)-HDA/SATA/XDP/RTC/SPI
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom 0.3
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
PBL80 LA-7441P M/B
Date: Monday, April 11, 2011 Sheet 29 of 59
5 4 3 2 1
5 4 3 2 1
UPCHB +3VALW_PCH
<40> PCIE_PRX_C_LANTX_N1 BG34 PERN1
LAN BJ34 E12 LID_SW_OUT# LID_SW_OUT# R206 1 2 10K_0402_5%
<40> PCIE_PRX_C_LANTX_P1 PERP1 SMBALERT# / GPIO11 LID_SW_OUT# <43>
C210 1 2 0.1U_0402_16V7K PCIE_PTX_LANRX_N1 AV32
<40> PCIE_PTX_C_LANRX_N1 PETN1
C215 1 2 0.1U_0402_16V7K PCIE_PTX_LANRX_P1 AU32 H14 PCH_SMBCLK DRAMRST_CNTRL_PCH R207 1 2 1K_0402_5%
<40> PCIE_PTX_C_LANRX_P1 PETP1 SMBCLK
BE34 C9 PCH_SMBDATA PCH_GPIO74 R208 1 2 10K_0402_5%
<39> PCIE_PRX_WLANTX_N2 PERN2 SMBDATA
WLAN <39> PCIE_PRX_WLANTX_P2 BF34
PCIE_PTX_WLANRX_N2 BB32 PERP2 PCH_GPIO47
C211 1 2 0.1U_0402_16V7K R213 1 2 10K_0402_5%
<39> PCIE_PTX_C_WLANRX_N2 PETN2
C212 1 2 0.1U_0402_16V7K PCIE_PTX_WLANRX_P2 AY32
SMBUS
D <39> PCIE_PTX_C_WLANRX_P2 PETP2 D
A12 DRAMRST_CNTRL_PCH PCH_SML0CLK R209 1 2 10K_0402_5%
SML0ALERT# / GPIO60 DRAMRST_CNTRL_PCH <7>
BG36
PERN3 PCH_SML0CLK PCH_SML0DATA R210 1
BJ36 C8 2 10K_0402_5%
PERP3 SML0CLK
AV34
PETN3 PCH_SML0DATA PCH_SMBCLK R211 1
AU34
PETP3 SML0DATA
G12 2 2.2K_0402_5%
BF36 PCH_SMBDATA R212 1 2 2.2K_0402_5%
<45> PCIE_PRX_C_USB30TX_N4 PERN4
USB3.0 <45> PCIE_PRX_C_USB30TX_P4 BE36
PCIE_PTX_USB30RX_N4 AY34 PERP4 PCH_GPIO74
C213 1 2 0.1U_0402_16V7K C13
<45> PCIE_PTX_C_USB30RX_N4 PETN4 SML1ALERT# / PCHHOT# / GPIO74
C214 1 2 0.1U_0402_16V7K PCIE_PTX_USB30RX_P4 BB34
<45> PCIE_PTX_C_USB30RX_P4 PETP4 PCH_SML1CLK
E14 Close to PCH1
PCI-E*
SML1CLK / GPIO58
BG37 PERN5
BH37 M16 PCH_SML1DATA
PERP5 SML1DATA / GPIO75 PCH_CLK_DMI# RH10 10K_0402_5%
AY36 PETN5 1 2
BB36 PCH_CLK_DMI RH11 1 2 10K_0402_5%
PETP5
BJ38 CLKIN_DMI2# RH12 1 2 10K_0402_5%
PERN6 CLKIN_DMI2 RH13 10K_0402_5%
BG38 1 2
Controller
PERP6
AU36 PETN6 CL_CLK1 M7
+3VS AV36 CLK_DOT# RH14 1 2 10K_0402_5%
PETP6 CLK_DOT RH15 10K_0402_5%
1 2
Link
1 2 CLKREQ_WLAN# BG40 T11
R215 10K_0402_5% PERN7 CL_DATA1 CLK_SATA# RH16 10K_0402_5%
BJ40 PERP7 1 2
+3VALW_PCH AY40 CLK_SATA RH17 1 2 10K_0402_5%
CLKREQ_USB30# PETN7
1 2 BB40 P10
R217 10K_0402_5% PETP7 CL_RST1# CLK_14M_PCH RH18 10K_0402_5%
1 2
1 2 PCH_GPIO46 BE38
R219 10K_0402_5% PERN8
BC38 PERP8
1 2 CLKREQ_LAN# AW38
R220 10K_0402_5% PETN8
AY38 PETP8
1 2 CLK_REQ_VGA#
R221 10K_0402_5% M10 PCH_GPIO47
C PEG_A_CLKRQ# / GPIO47 C
Y40 CLKOUT_PCIE0N
Y39 CLKOUT_PCIE0P
CLKOUT_PEG_A_N AB37
CLOCKS
PUT ALL REQ# PU AT PCH SIDE +3VALW_PCH 1 2 PCH_GPIO73 J2 AB38
R223 10K_0402_5% PCIECLKRQ0# / GPIO73 CLKOUT_PEG_A_P
R225 1 2 0_0402_5% CLK_R_WLAN# AB49 AV22 CLK_CPU_DMI#
<39> CLK_WLAN# CLKOUT_PCIE1N CLKOUT_DMI_N CLK_CPU_DMI# <5>
WLAN R226 1 2 0_0402_5% CLK_R_WLAN AB47 AU22 CLK_CPU_DMI
<39> CLK_WLAN CLKOUT_PCIE1P CLKOUT_DMI_P CLK_CPU_DMI <5>
CLKREQ_WLAN# M1
<39> CLKREQ_WLAN# PCIECLKRQ1# / GPIO18
AM12 CLK_CPU_DPLL# @ PAD T23
CLKOUT_DP_N / CLKOUT_BCLK1_N CLK_CPU_DPLL @
AM13
R227 1 CLK_R_USB30# CLKOUT_DP_P / CLKOUT_BCLK1_P
<45> CLK_USB30# 2 0_0402_5% AA48
CLKOUT_PCIE2N
PAD T24
USB3.0 R228 1 2 0_0402_5% CLK_R_USB30 AA47
<45> CLK_USB30 CLKOUT_PCIE2P PCH_CLK_DMI# XTAL25_IN
BF18
CLKREQ_USB30# CLKIN_DMI_N PCH_CLK_DMI
<45> CLKREQ_USB30# V10 BE18
PCIECLKRQ2# / GPIO20 CLKIN_DMI_P XTAL25_OUT 1 2
R255 1M_0402_5%
R230 1 2 0_0402_5% CLK_R_LAN# Y37 BJ30 CLKIN_DMI2#
<40> CLK_LAN# CLK_R_LAN CLKOUT_PCIE3N CLKIN_DMI2_N CLKIN_DMI2
LAN R231 1 2 0_0402_5% Y36 BG30 Y3
<40> CLK_LAN CLKOUT_PCIE3P CLKIN_DMI2_P
2 1
<40> CLKREQ_LAN# A8
PCIECLKRQ3# / GPIO25 CLK_DOT#
CLKIN_DOT_96N
G24 1 25MHZ_20PF_7A25000012 1
E24 CLK_DOT
CLKIN_DOT_96P C288 C243
Y43
CLKOUT_PCIE4N 33P_0402_50V8K 27P_0402_50V8J
Y45
CLKOUT_PCIE4P CLK_SATA# 2 2
AK7
PCH_GPIO26 CLKIN_SATA_N / CKSSCD_N CLK_SATA
+3VALW_PCH 1 2 L12 AK5
R232 10K_0402_5% PCIECLKRQ4# / GPIO26 CLKIN_SATA_P / CKSSCD_P
V45 K45 CLK_14M_PCH
CLKOUT_PCIE5N REFCLK14IN
V46
B CLKOUT_PCIE5P B
1 2 PCH_GPIO44 L14 H45 CLK_PCILOOP FROM CLK GEN FOR: 133/100/96/14.318 MHZ
+3VALW_PCH PCIECLKRQ5# / GPIO44 CLKIN_PCILOOPBACK CLK_PCILOOP <33>
R233 10K_0402_5%
<14> CLK_PCIE_VGA# CLK_PCIE_VGA# R234 1 2 0_0402_5% CLK_VGA# AB42 V47 XTAL25_IN
CLK_PCIE_VGA R235 CLK_VGA CLKOUT_PEG_B_N XTAL25_IN XTAL25_OUT PCH_SMBCLK
<14> CLK_PCIE_VGA 1 2 0_0402_5% AB40 V49 Q34A 1 2
CLKOUT_PEG_B_P XTAL25_OUT 2N7002DW T/R7_SOT-363-6 R236 0_0402_5%
<14> CLK_REQ_VGA# CLK_REQ_VGA# E6 PM_SMBCLK 1 6
PEG_B_CLKRQ# / GPIO56 <12,13,39> PM_SMBCLK
Y47 XCLK_RCOMP 1 2 +1.05VS_VCCDIFFCLKN
XCLK_RCOMP
V40 +3VS 2 1
2
CLKOUT_PCIE6N R237 90.9_0402_1% 4.7K_0402_5% R238
V42 +3VS
CLKOUT_PCIE6P
2 1
5
1 2 PCH_GPIO45 T13 4.7K_0402_5% R239 1 2 PCH_SMBDATA
+3VALW_PCH PCIECLKRQ6# / GPIO45
R240 10K_0402_5% R241 0_0402_5%
V38 K43 CLK_FLEX0 @ PAD T25 PM_SMBDATA 4 3
CLKOUT_PCIE7N CLKOUTFLEX0 / GPIO64 <12,13,39> PM_SMBDATA
FLEX CLOCKS
V37
CLKOUT_PCIE7P CLK_FLEX1 @ PAD T66 2N7002DW T/R7_SOT-363-6
F47
PCH_GPIO46 K12 CLKOUTFLEX1 / GPIO65 Q34B
PCIECLKRQ7# / GPIO46 CLK_FLEX2 @ PAD T67
H47
@ RH19
@RH19 CLK_BCLK_ITP# AK14 CLKOUTFLEX2 / GPIO66
<5,10> CLK_RES_ITP# 2 1 0_0402_5%
@RH20
@ RH20 CLK_BCLK_ITP CLKOUT_BCLK0_N / CLKOUT_PCIE8N CLK_FLEX3
<5,10> CLK_RES_ITP 2 1 0_0402_5% AK13
CLKOUT_BCLK0_P / CLKOUT_PCIE8P CLKOUTFLEX3 / GPIO67
K49 @ PAD T68
Q33A COUGARPOINT_FCBGA989~D
+3VALW_PCH 2N7002DW T/R7_SOT-363-6 HM65@
PCH_SML1CLK 6 1 EC_SMB_CK2 EC_SMB_CK2 <15,43>
2 1
R245 2.2K_0402_5% PU AT EC SIDE, +3VS AND 4.7K
2
+3VS
5
A A
2 1
R246 2.2K_0402_5%
PCH_SML1DATA
3 4 EC_SMB_DA2 EC_SMB_DA2 <15,43>
2N7002DW T/R7_SOT-363-6
Q33B
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2010/12/03 Deciphered Date 2011/12/03 Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Cougar Point(2/9)-PCI-E/SMBUS/CLK
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
WWW.AliSaler.Com
Custom 0.3
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
PBL80 LA-7441P M/B
Date: Monday, April 11, 2011 Sheet 30 of 59
5 4 3 2 1
5 4 3 2 1
D UPCHC D
DMI_CTX_PRX_N0 BC24 BJ14 FDI_CTX_PRX_N0
<6> DMI_CTX_PRX_N0 DMI0RXN FDI_RXN0 FDI_CTX_PRX_N0 <6>
DMI_CTX_PRX_N1 BE20 AY14 FDI_CTX_PRX_N1
<6> DMI_CTX_PRX_N1 DMI1RXN FDI_RXN1 FDI_CTX_PRX_N1 <6>
<6> DMI_CTX_PRX_N2 DMI_CTX_PRX_N2 BG18 BE14 FDI_CTX_PRX_N2
DMI2RXN FDI_RXN2 FDI_CTX_PRX_N2 <6>
<6> DMI_CTX_PRX_N3 DMI_CTX_PRX_N3 BG20 BH13 FDI_CTX_PRX_N3
DMI3RXN FDI_RXN3 FDI_CTX_PRX_N4 FDI_CTX_PRX_N3 <6>
BC12 FDI_CTX_PRX_N4 <6>
DMI_CTX_PRX_P0 FDI_RXN4 FDI_CTX_PRX_N5
<6> DMI_CTX_PRX_P0 BE24 BJ12 FDI_CTX_PRX_N5 <6>
DMI_CTX_PRX_P1 DMI0RXP FDI_RXN5 FDI_CTX_PRX_N6
<6> DMI_CTX_PRX_P1 BC20 BG10 FDI_CTX_PRX_N6 <6>
DMI_CTX_PRX_P2 DMI1RXP FDI_RXN6 FDI_CTX_PRX_N7
<6> DMI_CTX_PRX_P2 BJ18 BG9 FDI_CTX_PRX_N7 <6>
DMI_CTX_PRX_P3 DMI2RXP FDI_RXN7
<6> DMI_CTX_PRX_P3 BJ20
DMI3RXP FDI_CTX_PRX_P0
FDI_RXP0 BG14 FDI_CTX_PRX_P0 <6>
DMI_PTX_CRX_N0 AW24 BB14 FDI_CTX_PRX_P1
<6> DMI_PTX_CRX_N0 DMI0TXN FDI_RXP1 FDI_CTX_PRX_P1 <6>
DMI_PTX_CRX_N1 AW20 BF14 FDI_CTX_PRX_P2
<6> DMI_PTX_CRX_N1 DMI_PTX_CRX_N2 DMI1TXN FDI_RXP2 FDI_CTX_PRX_P3 FDI_CTX_PRX_P2 <6>
<6> DMI_PTX_CRX_N2 BB18 DMI2TXN FDI_RXP3 BG13 FDI_CTX_PRX_P3 <6>
DMI_PTX_CRX_N3 AV18 BE12 FDI_CTX_PRX_P4
DMI
FDI
<6> DMI_PTX_CRX_N3 DMI3TXN FDI_RXP4 FDI_CTX_PRX_P5 FDI_CTX_PRX_P4 <6>
FDI_RXP5 BG12 FDI_CTX_PRX_P5 <6>
DMI_PTX_CRX_P0 AY24 BJ10 FDI_CTX_PRX_P6
<6> DMI_PTX_CRX_P0 DMI_PTX_CRX_P1 DMI0TXP FDI_RXP6 FDI_CTX_PRX_P7 FDI_CTX_PRX_P6 <6>
<6> DMI_PTX_CRX_P1 AY20 DMI1TXP FDI_RXP7 BH9 FDI_CTX_PRX_P7 <6>
DMI_PTX_CRX_P2 AY18
<6> DMI_PTX_CRX_P2 DMI2TXP
DMI_PTX_CRX_P3 AU18
PCH_RSMRST# <6> DMI_PTX_CRX_P3 DMI3TXP FDI_INT
2 1 AW16 FDI_INT <6>
R247 10K_0402_5% FDI_INT
2 1 PM_PWROK 1 2 DMI_COMP BJ24 AV12 FDI_FSYNC0
+1.05VS_PCH DMI_ZCOMP FDI_FSYNC0 FDI_FSYNC0 <6>
R248 10K_0402_5% R249 49.9_0402_1%
2 1 PWROK BG25 BC10 FDI_FSYNC1
DMI_IRCOMP FDI_FSYNC1 FDI_FSYNC1 <6>
R250 10K_0402_5%
1 2 RBIAS_CPY BH21 AV14 FDI_LSYNC0
DMI2RBIAS FDI_LSYNC0 FDI_LSYNC0 <6>
RH21 750_0402_1%
4mil width and place FDI_LSYNC1 BB10 FDI_LSYNC1
FDI_LSYNC1 <6>
within 500mil of the PCH
C C
A18 DSWODVREN
DSWVRMEN RH22
System Power Management
0_0402_5%
<5> PWROK
<43> SUSACK# 1 @ 2 SUSACK#_R C12 SUSACK# DPWROK E22 PCH_DPWROK 1 2 PCH_RSMRST#
RH23 0_0402_5%
+3VS
XDP_DBRESET# 1 2 XDP_DBRESET#_PCH_R K3 B9 EC_SWI# If strap is sampled high, the
<5,29> XDP_DBRESET# SYS_RESET# WAKE# EC_SWI# <40,45>
5
U6 R251 0_0402_5% Integrated Deep S4/S5 Well (DSW) +RTCVCC
2 On-Die VR mode is enabled.
P
<5,43,55> VGATE B
4 PWROK P12 N3 PCH_GPIO32
Y SYS_PWROK CLKRUN# / GPIO32 DSWODVREN RH25
<43> PM_PWROK 1 2 1 330K_0402_5%
A
G
NC7SZ08P5X_NL_SC70-5 PM_PWROK R253 0_0402_5% L22 G8 SUS_STAT# @ T69 PAD RH26 2 @ 1 330K_0402_5%
3
PWROK SUS_STAT# / GPIO61
1 2
DSWODVREN - On Die DSW VR Enable
APWROK L10 SUSCLK
APWROK SUSCLK / GPIO62
N14 SUSCLK <43> * H：Enable
L：Disable
2 1 VGATE <5> DRAMPWROK
DRAMPWROK B13
DRAMPWROK SLP_S5# / GPIO63
D10 PM_SLP_S5#
PM_SLP_S5# <43>
C220 @ 180P_0402_50V8J
0608 CHANGE PM_CLKRUN# FROM NOT PD OR PU TO PU +3VS
PCH_RSMRST# C21 H4 PM_SLP_S4#
<29,43> PCH_RSMRST# RSMRST# SLP_S4# PM_SLP_S4# <43>
PCH_GPIO32 R256 1 2 8.2K_0402_5%
1 2 SUSWARN#_R K16 F4 PM_SLP_S3#
<43> SUSWARN# SUSWARN# / SUS_PWR_DN_ACK / GPIO30 SLP_S3# PM_SLP_S3# <43>
R257 0_0402_5%
RH28
0_0402_5% E20 G10 +3VALW_PCH
<5,29,43> PBTN_OUT# PWRBTN# SLP_A#
SUSACK#_R 2 1 SUSWARN#_R
@ D8 EC_SWI# R259 1 2 10K_0402_5%
1 2 PCH_ACIN H20 G16 PM_SLP_SUS#
B <43,48> ACIN ACPRESENT / GPIO31 SLP_SUS# PM_SLP_SUS# <43> B
PCH_GPIO29 R260 1 @ 2 10K_0402_5%
+3VALW_PCH RB751V-40 SOD-323
PCH_GPIO72 E10 AP14 H_PM_SYNC
DRAMPWROK BATLOW# / GPIO72 PMSYNCH H_PM_SYNC <5>
2 1
R261 200_0402_5%
2 1 SUSWARN#_R RI# A10 K14 PCH_GPIO29 Muxed with SLP_LAN#:PU--> DISABLE
R262 10K_0402_5% RI# SLP_LAN# / GPIO29
2 1 PCH_ACIN
R263 330K_0402_5% COUGARPOINT_FCBGA989~D
2 1 RI# HM65@
R264 10K_0402_5%
2 1 PCH_GPIO72
R265 10K_0402_5%
A A
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2010/12/03 Deciphered Date 2011/12/03 Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Cougar Point(3/9)-DMI/FDI/PWM
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom 0.3
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
PBL80 LA-7441P M/B
Date: Monday, April 11, 2011 Sheet 31 of 59
5 4 3 2 1
5 4 3 2 1
D D
ENBKL
<43> ENBKL
2
R362
100K_0402_5%
1
Pull high at LVDS conn side.
UPCHD
ENBKL J47 AP43
+3VS L_BKLTEN SDVO_TVCLKINN
<27> VGA_ENVDD M45 L_VDD_EN SDVO_TVCLKINP AP45
R363 1 2 2.2K_0402_5% CTRL_CLK P45 AM42
<27> VGA_BL_PWM L_BKLTCTL SDVO_STALLN
SDVO_STALLP AM40
R364 1 2 2.2K_0402_5% CTRL_DATA T40
<27> LCD_EDID_CLK L_DDC_CLK
<27> LCD_EDID_DATA K47 L_DDC_DATA SDVO_INTN AP39
R373 1 2 2.2K_0402_5% LCD_EDID_CLK AP40
CTRL_CLK SDVO_INTP
T45 L_CTRL_CLK
R376 1 2 2.2K_0402_5% LCD_EDID_DATA CTRL_DATA P39
2.37K_0402_1% L_CTRL_DATA
RH244 2 1 LVDS_IBG AF37 P38
LVD_IBG SDVO_CTRLCLK
AF36 LVD_VBG SDVO_CTRLDATA M39
0_0402_5% LVD_VREF AE48
RH290 LVD_VREFH
2 1 AE47 LVD_VREFL DDPB_AUXN AT49
C R266 @ 100K_0402_5% C
DDPB_AUXP AT47
DDPB_HPD AT40 1 2
LCD_TXCLK- AK39
LVDS
<27> LCD_TXCLK- LCD_TXCLK+ LVDSA_CLK#
<27> LCD_TXCLK+ AK40 LVDSA_CLK DDPB_0N AV42
+3VS AV40
LCD_TXOUT0- DDPB_0P
<27> LCD_TXOUT0- AN48 LVDSA_DATA#0 DDPB_1N AV45
RH291 1 2 2.2K_0402_5% VGA_CRT_CLK LCD_TXOUT1- AM47 AV46
Digital Display Interface
<27> LCD_TXOUT1- LVDSA_DATA#1 DDPB_1P
LCD_TXOUT2- AK47 AU48
VGA_CRT_DATA <27> LCD_TXOUT2- LVDSA_DATA#2 DDPB_2N
RH292 1 2 2.2K_0402_5% AJ48 AU47
LVDSA_DATA#3 DDPB_2P
AV47
LCD_TXOUT0+ DDPB_3N
<27> LCD_TXOUT0+ AN47 AV49
LCD_TXOUT1+ LVDSA_DATA0 DDPB_3P
<27> LCD_TXOUT1+ AM49
RH131 VGA_CRT_B LCD_TXOUT2+ LVDSA_DATA1
1 2 150_0402_1% <27> LCD_TXOUT2+ AK49
LVDSA_DATA2
AJ47 P46
RH132 VGA_CRT_G LVDSA_DATA3 DDPC_CTRLCLK
1 2 150_0402_1% DDPC_CTRLDATA
P42
RH133 1 2 150_0402_1% VGA_CRT_R LCD_TZCLK- AF40
<27> LCD_TZCLK- LVDSB_CLK#
LCD_TZCLK+ AF39 AP47
<27> LCD_TZCLK+ LVDSB_CLK DDPC_AUXN
AP49 R267 100K_0402_5%
LCD_TZOUT0- DDPC_AUXP @
<27> LCD_TZOUT0- AH45 AT38 1 2
LCD_TZOUT1- LVDSB_DATA#0 DDPC_HPD
<27> LCD_TZOUT1- AH47
LCD_TZOUT2- LVDSB_DATA#1
<27> LCD_TZOUT2- AF49 AY47
LVDSB_DATA#2 DDPC_0N
AF45 AY49
LVDSB_DATA#3 DDPC_0P
AY43
LCD_TZOUT0+ DDPC_1N
<27> LCD_TZOUT0+ AH43 AY45
LCD_TZOUT1+ LVDSB_DATA0 DDPC_1P
<27> LCD_TZOUT1+ AH49 BA47
LCD_TZOUT2+ LVDSB_DATA1 DDPC_2N
<27> LCD_TZOUT2+ AF47 BA48
LVDSB_DATA2 DDPC_2P
AF43 BB47
LVDSB_DATA3 DDPC_3N
BB49
DDPC_3P
VGA_CRT_B N48 M43
B <26> VGA_CRT_B CRT_BLUE DDPD_CTRLCLK B
VGA_CRT_G P49 M36
<26> VGA_CRT_G CRT_GREEN DDPD_CTRLDATA
VGA_CRT_R T49
<26> VGA_CRT_R CRT_RED
AT45
CRT
VGA_CRT_CLK DDPD_AUXN 100K_0402_5%
<26> VGA_CRT_CLK T39 AT43
VGA_CRT_DATA CRT_DDC_CLK DDPD_AUXP R268
<26> VGA_CRT_DATA M40 BH41 2 1
CRT_DDC_DATA DDPD_HPD @
BB43
VGA_CRT_HSYNC DDPD_0N
<26> VGA_CRT_HSYNC M47 BB45
VGA_CRT_VSYNC CRT_HSYNC DDPD_0P
<26> VGA_CRT_VSYNC M49 BF44
CRT_VSYNC DDPD_1N
BE44
DDPD_1P
BF42
DDPD_2N
2 1CRT_IREF T43
DAC_IREF DDPD_2P
BE42
R1250 1K_0402_1% T42 BJ42
CRT_IRTN DDPD_3N
BG42
DDPD_3P
COUGARPOINT_FCBGA989~D
HM65@
A A
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2010/12/03 Deciphered Date 2011/12/03 Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Cougar Point(4/9)-CRT/LVDS/HDMI/DP
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
WWW.AliSaler.Com
Custom 0.3
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
PBL80 LA-7441P M/B
Date: Monday, April 11, 2011 Sheet 32 of 59
5 4 3 2 1
5 4 3 2 1
PLT_RST#
+3VS
1
RP1 R533 +3VS
8 1 PCH_GPIO4 0_0402_5%
7 2 PCI_PIRQC# 1 2
6 3 PCI_PIRQA# UPCHE C508 0.1U_0402_16V4Z
5
5 4 PCH_GPIO2 AY7 @ U20
NV_CE#0
AV7 2 1 1
P
NV_CE#1 <14,34,46,57> VGA_PWROK IN1
8.2K_0804_8P4R_5% BG26 AU3 R531 0_0402_5% 4 2 1
TP1 NV_CE#2 DGPU_RST# O PLTRST_VGA# <14>
BJ26 BG4 2 R528 0_0402_5%
TP2 NV_CE#3 IN2
G
RP2 BH25
TP3
1
8 1 PCH_GPIO52 BJ16 AT10 SN74AHC1G08DCKR_SC70-5
3
TP4 NV_DQS0
2
D PCH_GPIO53 D
7 2 BG16 BC8
ODD_DA#_R TP5 NV_DQS1 R532 R530
6 3 AH38
TP6
5 4 PCH_GPIO51 AH37 AU2 1K_0402_5% 100K_0402_5%
TP7 NV_DQ0 / NV_IO0
AK43 AT4
2
8.2K_0804_8P4R_5% TP8 NV_DQ1 / NV_IO1
AK45 AT3
1
TP9 NV_DQ2 / NV_IO2
C18 AT1
RP3 TP10 NV_DQ3 / NV_IO3
N30 AY3
PCH_GPIO5 TP11 NV_DQ4 / NV_IO4
8 1 H3
TP12 NV_DQ5 / NV_IO5
AT5
7 2 PCI_PIRQB# AH12 AV3
NVRAM
PCI_PIRQD# TP13 NV_DQ6 / NV_IO6
6 3 AM4 AV1
PCH_GPIO55 TP14 NV_DQ7 / NV_IO7
5 4 AM5
TP15 NV_DQ8 / NV_IO8
BB1
Y13 TP16 NV_DQ9 / NV_IO9 BA3
8.2K_0804_8P4R_5% K24 BB5 +1.8VS
TP17 NV_DQ10 / NV_IO10
L24 TP18 NV_DQ11 / NV_IO11 BB3
1 @ 2 DGPU_RST# AB46 BB7
TP19 NV_DQ12 / NV_IO12
1
R271 8.2K_0402_5% AB45 BE8
RSVD
@ DGPU_PWR_EN TP20 NV_DQ13 / NV_IO13 R270
1 2 NV_DQ14 / NV_IO14 BD4
R273 8.2K_0402_5% BF6 2.2K_0402_5%
NV_DQ15 / NV_IO15
1 2 DGPU_PWR_EN B21 AV5
2
R399 1K_0402_5% TP21 NV_ALE NV_CLE
M20 TP22 NV_CLE AY1 2 1 H_SNB_IVB# <5>
AY16 R272 1K_0402_5%
TP23
BG46 TP24 NV_RCOMP AV10
NV_RB# AT8
R275
BE28 TP25 NV_RE#_WRB0 AY5
PLT_RST# 1 2 BC30 BA2
TP26 NV_RE#_WRB1
BE32 TP27
BJ32 TP28 NV_WE#_CK0 AT12
100K_0402_5%
BC28 TP29 NV_WE#_CK1 BF3
BE30 TP30
C C
BF32 TP31
BG32 C24 USB20_N0
TP32 USBP0N USB20_P0 USB20_N0 <39>
1 2 AV26 TP33 USBP0P A24
USB20_N1 USB20_P0 <39> R-CONN
R395 0_0402_5% BB26 C25
TP34 USBP1N USB20_P1 USB20_N1 <39>
+3VS
AU28 TP35 USBP1P B25
USB20_N2 USB20_P1 <39> R-CONN
AY30 TP36 USBP2N C26 USB20_N2 <39>
AU26 A26 USB20_P2 R-CONN
TP37 USBP2P USB20_P2 <39>
AY26 K28
TP38 USBP3N
5
AV28 H28
PLT_RST# TP39 USBP3P USB20_N4
2 AW30 E28
P
B PCH_PLT_RST# TP40 USBP4N USB20_P4 USB20_N4 <45>
Y
4 PCH_PLT_RST# <40,43,45> USBP4P
D28 USB20_P4 <45> L-CONN
1 C28
A USBP5N
G
A28
USBP5P
2
C29
3
U11 @ R396 USBP6N
B29
100K_0402_5% PCI_PIRQA# K40
USBP6P
N28
USB port6 and port7 are disabled on HM65
NC7SZ08P5X_NL_SC70-5 @ PCI_PIRQB# PIRQA# USBP7N
K38 M28
PCI
PCI_PIRQC# PIRQB# USBP7P
H38 L30
1
PCI_PIRQD# PIRQC# USBP8N
G38 K30
PIRQD# USBP8P +3VALW_PCH
G30
DGPU_RST# USBP9N
C46 E30
USB
PCH_GPIO52 REQ1# / GPIO50 USBP9P USB20_N10 USB_OC0#
C44 C30 USB20_N10 <27> 1 2
DGPU_PWR_EN REQ2# / GPIO52 USBP10N USB20_P10 R276 10K_0402_5%
<14,17,57> DGPU_PWR_EN E40
REQ3# / GPIO54 USBP10P
A30
USB20_N11
USB20_P10 <27> Int. Camera USB_OC1#
L32 USB20_N11 <39> 1 2
PCH_GPIO51 USBP11N USB20_P11 R277 10K_0402_5%
PCH_GPIO53
D47
GNT1# / GPIO51 USBP11P
K32 USB20_P11 <39> Card Reader PCH_GPIO9
E42 G32 1 2
GNT2# / GPIO53 USBP12N
For ESD request PCH_GPIO55 F46
GNT3# / GPIO55 USBP12P
E32 R278 10K_0402_5%
C32 USB20_N13 PCH_GPIO14 1 2
USBP13N USB20_P13 USB20_N13 <39>
A32 BT IN WLAN R279 10K_0402_5%
PCH_GPIO2 USBP13P USB20_P13 <39> PCH_GPIO10
@ R397 G42 1 2
ODD_DA#_R PIRQE# / GPIO2 R280 10K_0402_5%
<38> ODD_DA# 1 2 G40
0_0402_5% PCH_GPIO4 PIRQF# / GPIO3 USBBIAS USB_OC2#
2 C42 C33 1 2 1 2
B @ PCH_GPIO5 PIRQG# / GPIO4 USBRBIAS# R281 22.6_0402_1% R282 10K_0402_5% B
D44
C509 PIRQH# / GPIO5 PCH_GPIO43
Within 1 2
0.1U_0402_16V4Z B33 R283 10K_0402_5%
1 @ USBRBIAS 500 mils PCH_GPIO42
T26 PAD K10 1 2
PME# R284 10K_0402_5%
PLT_RST# C6 A14 USB_OC0#
<5,39> PLT_RST# PLTRST# OC0# / GPIO59 USB_OC1# USB_OC0# <39>
K20 USB_OC1# <39>
OC1# / GPIO40 USB_OC2#
B17 USB_OC2# <45>
22_0402_5% 2 R285 CLK_PCH OC2# / GPIO41 PCH_GPIO42
<30> CLK_PCILOOP 1 H49 C16
33_0402_5% 2 R286 1 CLK_PCI_EC_R CLKOUT_PCI0 OC3# / GPIO42 PCH_GPIO43
<43> CLK_PCI_EC H43 L16
CLK_PCI2 CLKOUT_PCI1 OC4# / GPIO43 PCH_GPIO9
T65 PAD J48 A16
@T27 PAD CLK_PCI3 CLKOUT_PCI2 OC5# / GPIO9 PCH_GPIO10
K42 D14
@T28 PAD CLK_PCI4 CLKOUT_PCI3 OC6# / GPIO10 PCH_GPIO14
H40 C14
@ CLKOUT_PCI4 OC7# / GPIO14
COUGARPOINT_FCBGA989~D
HM65@
Boot BIOS Strap bit1 BBS1
Boot BIOS
Destination
Bit11 Bit10
0 1 Reserved
GNT1#/
GPIO51 1 0 PCI
A A
1 1 SPI
0 0 LPC
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2010/12/03 Deciphered Date 2011/12/03 Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Cougar Point(5/9)-USB/PCI/NAND/STRAP
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom 0.3
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
PBL80 LA-7441P M/B
Date: Monday, April 11, 2011 Sheet 33 of 59
5 4 3 2 1
5 4 3 2 1
+3VALW_PCH
2 1 USB30_SMI#
1K_0402_5% R288
2 1 PCH_GPIO57 UPCHF
10K_0402_5% R289
2 1 EC_SMI# PCH_GPIO0 T7 C40 ODD_EN#
BMBUSY# / GPIO0 TACH4 / GPIO68 ODD_EN# <38>
10K_0402_5% R294
2 1 PCH_GPIO12 PCH_GPIO1 A42 B41 PCH_GPIO69 @ T29 PAD
10K_0402_5% R290 TACH1 / GPIO1 TACH5 / GPIO69 +3VS
1 2 PCH_GPIO28 DGPU_HPD_INT# H36 C41 PCH_GPIO70 @ T31 PAD
<28> DGPU_HPD_INT# TACH2 / GPIO6 TACH6 / GPIO70
10K_0402_5% R295
1
<43> EC_SCI# EC_SCI# E38 A40 PCH_GPIO71 @ T30 PAD
TACH3 / GPIO7 TACH7 / GPIO71 R291
D EC_SMI# D
<43> EC_SMI# C10 10K_0402_5%
GPIO8
+3VS PCH_GPIO12 C4
2
LAN_PHY_PWR_CTRL / GPIO12
2 1 PCH_GPIO0 <45> USB30_SMI# USB30_SMI# G2 P4
GPIO15 A20GATE GATEA20 <43>
10K_0402_5% R292
2 1 PCH_GPIO1 AU16 PCH_PECI_R 1 @ 2
CPU/MISC
PCH_GPIO16 PECI H_PECI <5,43>
10K_0402_5% R296 U2 0_0402_5% RH29
KB_RST# SATA4GP / GPIO16 KB_RST#
2 1 RCIN#
P5 KB_RST# <43>
10K_0402_5% R297
GPIO
2 1 ODD_EN# D40 AY11 H_PWRGOOD
<14,33,46,57> VGA_PWROK TACH0 / GPIO17 PROCPWRGD H_PWRGOOD <5>
10K_0402_5% R293
1 2 PCH_GPIO22 PCH_GPIO22 T5 AY10 PCH_THRMTRIP# 1 2
SCLOCK / GPIO22 THRMTRIP# H_THERMTRIP# <5>
10K_0402_5% R298 R299 390_0402_5%
1 2 PCH_GPIO34 PCH_GPIO24 E8 T14
10K_0402_5% R300 GPIO24 / MEM_LED INIT3_3V#
2 1 PCH_GPIO16 PCH_GPIO27 E16 INIT3_3V
10K_0402_5% R301 GPIO27
1 2 ODD_DETECT# PCH_GPIO28 P8 GPIO28
This signal has weak internal
10K_0402_5% R302 AH8 PU, can't pull low
DGPU_HPD_INT# PCH_GPIO34 NC_1
2 1 K1 STP_PCI# / GPIO34
10K_0402_5% R303 AK11
PCH_GPIO24 PAD T70 @ PCH_GPIO35 NC_2
1 2 K4 GPIO35
10K_0402_5% R305 AH10
PCH_GPIO38 ODD_DETECT# NC_3
2 1 <38> ODD_DETECT# V8 SATA2GP / GPIO36
10K_0402_5% R306
NC_4 AK10 Intel schematic review recommand.
2 1 EC_SCI# PCH_GPIO37 M5
10K_0402_5% R307 SATA3GP / GPIO37
NC_5 P37
2 1 PCH_GPIO39 PCH_GPIO38 N2
10K_0402_5% R308 SLOAD / GPIO38
1 2 PCH_GPIO48 PCH_GPIO39 M3
10K_0402_5% R309 SDATAOUT0 / GPIO39
C PCH_GPIO49 PCH_GPIO48 C
1 2 V13 SDATAOUT1 / GPIO48 VSS_NCTF_15 BG2
10K_0402_5% R310
1 @ 2 VGA_PWROK PCH_GPIO49 V3 BG48
10K_0402_5% R311 SATA5GP / GPIO49 VSS_NCTF_16
PCH_GPIO57 D6 BH3
GPIO57 VSS_NCTF_17
VSS_NCTF_18 BH47
1 2 PCH_GPIO27
10K_0402_5% R314 A4 BJ4
PCH_GPIO37 VSS_NCTF_1 VSS_NCTF_19
2 1
10K_0402_5% R313 A44 BJ44
VSS_NCTF_2 VSS_NCTF_20
A45 BJ45
VSS_NCTF_3 VSS_NCTF_21
NCTF
A46 BJ46
VSS_NCTF_4 VSS_NCTF_22
A5 BJ5
VSS_NCTF_5 VSS_NCTF_23
A6 BJ6
VSS_NCTF_6 VSS_NCTF_24
B3 C2
VSS_NCTF_7 VSS_NCTF_25
B47 C48
GPIO28 VSS_NCTF_8 VSS_NCTF_26
On-Die PLL Voltage Regulator BD1
VSS_NCTF_9 VSS_NCTF_27
D1
This signal has a weak internal pull up
BD49 D49
H：On-Die voltage regulator enable VSS_NCTF_10 VSS_NCTF_28
* L：On-Die PLL Voltage Regulator disable BE1
VSS_NCTF_11 VSS_NCTF_29
E1
R315 1 @ 2 1K_0402_5% PCH_GPIO28 BE49 E49
VSS_NCTF_12 VSS_NCTF_30
B B
BF1 F1
VSS_NCTF_13 VSS_NCTF_31
BF49 F49
VSS_NCTF_14 VSS_NCTF_32
GPIO8 COUGARPOINT_FCBGA989~D
Integrated Clock Chip Enable HM65@
H ; Disable
L ; Enable
*
R316 1 @ 2 1K_0402_5% EC_SMI#
Reserve for ICC enable.
A A
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2010/12/03 Deciphered Date 2011/12/03 Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Cougar Point(6/9)-CPU/GPIO/MISC
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
WWW.AliSaler.Com
Custom 0.3
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
PBL80 LA-7441P M/B
Date: Monday, April 11, 2011 Sheet 34 of 59
5 4 3 2 1
5 4 3 2 1
+1.05VS_VCCP +1.05VS_PCH UPCHG POWER +3VS
L12
@JP2
@ JP2 1300mA MBK1608221YZF_2P
2 1 +1.05VS_PCH AA23 U48 +VCCADAC 2 1
VCCCORE[1] 1mA VCCADAC
AC23 1 1 1
VCCCORE[2]
10U_0603_6.3V6M
C221
1U_0402_6.3V6K
C224
1U_0402_6.3V6K
C222
1U_0402_6.3V6K
C223
0.01U_0402_16V7K
C287
0.1U_0402_10V7K
C294
CRT
AD21
PAD-OPEN 4x4m 1 1 1 1 VCCCORE[3]
D
AD23
VCCCORE[4] VSSADAC
U47 C289
10U_0603_6.3V6M
PCH Power Rail Table D
VCC CORE
AF21
VCCCORE[5] 2 2 2
AF23
VCCCORE[6]
S0 Iccmax
2 2 2 2 AG21 R332 +3VS Voltage Rail Voltage
VCCCORE[7] Current (A)
AG23 0_0603_5%
VCCCORE[8] +VCCALVDS
AG24 1mA VCCALVDS AK36 1 2
VCCCORE[9]
AG26
VCCCORE[10]
V_PROC_IO 1.05 0.001
AG27 AK37
VCCCORE[11] VSSALVDS
AG29
VCCCORE[12]
AJ23 V5REF 5 0.001
LVDS
VCCCORE[13]
AJ26 AM37
VCCCORE[14] VCCTX_LVDS[1] +1.8VS
AJ27
VCCCORE[15]
AJ29 VCCCORE[16] VCCTX_LVDS[2] AM38 L21 V5REF_Sus 5 0.001
AJ31 0.1UH_MLF1608DR10KT_10%_1608
VCCCORE[17] +VCCTX_LVDS
60mA VCCTX_LVDS[3] AP36 2 1
+1.05VS_PCH 1 1 1 0.1uH inductor, 200mA Vcc3_3 3.3 0.266
22U_0805_6.3V6M
VCCTX_LVDS[4] AP37
R317 2 1 0_0603_5% +1.05VS_VCCDPLLEXP AN19 C296 C297
VCCIO[28]
C295
0.01U_0402_16V7K 0.01U_0402_16V7K VccADAC 3.3 0.001
2 2 2
PAD T64 @ +VCCAPLLEXP BJ22 VCCAPLLEXP
VccADPLLA 1.05 0.08
This pin can be left as no connect in V33 +3VS_VCC3_3_6 1 R318 2 +3VS
HVCMOS
VCC3_3[6] 0_0805_5%
AN16 VCCIO[15]
On-Die VR enabled mode (default). 1 VccADPLLB 1.05 0.08
AN17 VCCIO[16]
V34 C226
VCC3_3[7]
0.1U_0402_10V7K VccCore 1.05 1.3
AN21 2
VCCIO[17]
AN26 VCCIO[18]
R319 VccDMI 1.05 0.042
+VCCAFDI_VRM 0_0603_5%
AN27 2925mA AT16 +VCCAFDI_VRM 1 2
C VCCIO[19] VCCVRM[3] +1.5VS C
VccIO 1.05 2.925
+1.05VS_PCH R320 AP21 R321
0_0805_5% VCCIO[20] +VCCP_VCCDMI 0_0805_5%
1 2 +1.05VS_VCC_EXP AP23 AT20 +VCCP_VCCDMI 1 2 +1.05VS_PCH VccASW 1.05 1.01
VCCIO[21] VCCDMI[1]
1
DMI
10U_0603_6.3V6M
C227
1U_0402_6.3V6K
C228
1U_0402_6.3V6K
C229
1U_0402_6.3V6K
C230
1U_0402_6.3V6K
C231
AP24 R322 +1.05VS_PCH
1 1 1 1 1
VCCIO
VCCIO[22] 0_0805_5% C232 VccSPI 3.3 0.02
AP26 20mA AB36 +1.05VS_VCC_DMI_CCI 1 2 1U_0402_6.3V6K
VCCIO[23] VCCIO[1] 2
2 2 2 2 2 1
AT24
VCCIO[24]
VccDSW 3.3 0.003
C233
1U_0402_6.3V6K
AN33 2 VccpNAND 1.8 0.19
VCCIO[25]
AN34 AG16
+3VS VCCIO[26] VCCPNAND[1]
R323 R324 VccRTC 3.3 6 uA
0_0805_5% 0_0805_5%
NAND / SPI
1 2 +3VS_VCCA3GBG BH29 AG17 +VCCPNAND 1 2
VCC3_3[3] 190mA VCCPNAND[2] +1.8VS
1 VccSus3_3 3.3 0.119
C234
0.1U_0402_10V7K AJ16 1
VCCPNAND[3] C235 VccSusHDA 3.3 / 1.5 0.01
2 0.1U_0402_10V7K
+VCCAFDI_VRM AP16
+1.05VS_PCH @ R325 VCCVRM[2]
AJ17
VCCPNAND[4] 2
0_0603_5% VccVRM 1.8 / 1.5 0.16
2 1 +1.05VS_VCCAPLL_FDI BG6
VCCFDIPLL
+1.05VS_PCH R327 R326 VccCLKDMI 1.05 0.02
1
1 2 +1.05VS_VCCDPLL_FDI AP17 0_0805_5%
VCCIO[27]
FDI
@ C236 0_0805_5% V1 +3V_VCCPSPI 1 2
20mA VCCSPI +3VS
1U_0402_6.3V6K VccSSC 1.05 0.095
2
+VCCP_VCCDMI AU20 1
B VCCDMI[2] B
C237 VccDIFFCLKN 1.05 0.055
COUGARPOINT_FCBGA989~D 1U_0402_6.3V6K
HM65@ 2
VccALVDS 3.3 0.001
VccTX_LVDS 1.8 0.06
A A
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2010/12/03 Deciphered Date 2011/12/03 Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Cougar Point(7/9)-PWR1
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom 0.3
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
PBL80 LA-7441P M/B
Date: Monday, April 11, 2011 Sheet 35 of 59
5 4 3 2 1
5 4 3 2 1
VCC3_3 = 266mA detal waiting for newest spec
Have internal VRM
+3VS +1.05VS_PCH @ R329
VCCDMI = 42mA detal waiting for newest spec
@ R328
0_0805_5% 0_0603_5%
1 2 2 1 +VCCACLK
L13
10UH_LB2012T100MR_20%
+3VS_VCC_CLKF33 +3VALW_PCH R378
1 2
1 1 0_0603_5% UPCHJ POWER R331 +1.05VS_PCH
+5VALW +5VALW_PCH
10U_0603_6.3V6M
C238
1U_0402_6.3V6K
C239
1 2 +VCCPDSW 0_0603_5% JUMP_43X39
AD49 N26 +1.05VS_VCCUSBCORE 2 1 @ PJ334
1 VCCACLK VCCIO[29]
1 2 1
2 2 C240 2 1
P26
D 0.1U_0402_10V7K VCCIO[30] C241 D
T16 3mA 1
@ C242 2 VCCDSW3_3 1U_0402_6.3V6K C305
P28
0.1U_0402_10V7K VCCIO[31] 2
2 1 +PCH_VCCDSW V12 T27 0.1U_0402_10V7K
DCPSUSBYP VCCIO[32] 2
T29
+3VS_VCC_CLKF33 VCCIO[33] R336 +3VALW_PCH
T38
+1.05VS_PCH @R335
@ R335 @ L14 VCC3_3[5] 0_0603_5%
0_0603_5% 10UH_LB2012T100MR_20% T23 +3V_VCCPUSB 2 1
1 2 +VCCAPLL_CPY 1 2 +VCCAPLL_CPY_PCH BH23
119mA VCCSUS3_3[7]
VCCAPLLDMI2 +3VALW_PCH
0.1U_0402_10V7K
C244
T24 1 R337
R338 +VCCDPLL_CPY VCCSUS3_3[8] +5VALW_PCH +3VALW_PCH
1 +1.05VS_PCH 1 2 0_0603_5% AL29 VCCIO[14]
0_0603_5%
V23 +3V_VCCAUBG 2 1
USB
@ C245 VCCSUS3_3[9]
1
2
10U_0603_6.3V6M +VCCSUS1 2 C246
AL24 DCPSUS[3] VCCSUS3_3[10] V24
2 0.1U_0402_10V7K R339 D9
1
P24 100_0402_5% RB751V-40 SOD-323
@ C247 VCCSUS3_3[6] 2 R340 +1.05VS_PCH
1U_0402_6.3V6K AA19 0_0603_5%
1
2 VCCASW[1] +1.05VS_VCCAUPLL +PCH_V5REF_SUS
VCCIO[34] T26 2 1
+1.05VS_PCH R341 AA21 1010mA
VCCASW[2] 1
0_0805_5%
1 2 +1.05VM_VCCASW AA24 M26 +PCH_V5REF_SUS C248
VCCASW[3] 1mA V5REF_SUS 0.1U_0603_25V7K
1 1 2
22U_0805_6.3V6M
C249
22U_0805_6.3V6M
C250
Clock and Miscellaneous
AA26 @
VCCASW[4] +VCCA_USBSUS C251
DCPSUS[4] AN23 1 2 1U_0402_6.3V6K
AA27 VCCASW[5]
2 2 AN24 +3V_VCCPSUS
VCCSUS3_3[1]
AA29 VCCASW[6]
+5VS +3VS
AA31 VCCASW[7]
C
AC26 P34 +PCH_V5REF_RUN R342 +3VALW_PCH C
VCCASW[8] 1mA V5REF
2
1 1 1 0_0603_5%
1U_0402_6.3V6K
C252
1U_0402_6.3V6K
C253
1U_0402_6.3V6K
C254
AC27 2 1 R343 D10
VCCASW[9] +3V_VCCPSUS 100_0402_5% RB751V-40 SOD-323
N20 1
PCI/GPIO/LPC
VCCSUS3_3[2] C255
AC29 VCCASW[10]
2 2 2 N22 1U_0402_6.3V4Z
1
+1.05VS_PCH VCCSUS3_3[3] +PCH_V5REF_RUN
AC31 VCCASW[11]
R344 L15 P20 2 R345 +3VS
VCCSUS3_3[4] 1
0_0805_5% 10UH_LB2012T100MR_20% AD29 0_0805_5%
+VCCA_DPLL_L +1.05VS_VCCA_A_DPL VCCASW[12] C256
1 2 1 2 P22 2 1
VCCSUS3_3[5] 1U_0603_10V6K
AD31 1
VCCASW[13] C257 2
1 2 +1.05VS_VCCA_B_DPL W21 AA16 +3VS_VCCPCORE 0.1U_0402_10V7K
L16 VCCASW[14] VCC3_3[1]
2 +3VS
220U_B2_2.5VM_R35
C258
1U_0402_6.3V6K
C259
220U_B2_2.5VM_R35
C260
1U_0402_6.3V6K
C261
10UH_LB2012T100MR_20% 1 1 W23 W16 R346
VCCASW[15] VCC3_3[8] 0_0603_5%
1 1
+ + W24 T34 +3VS_VCCPPCI 2 1
VCCASW[16] VCC3_3[4]
1
W26 C262
2 2 2 2 VCCASW[17] 0.1U_0402_10V7K
W29 R347 +3VS
VCCASW[18] 0_0603_5% 2
W31 AJ2 +VCC3_3_2 2 1
+1.05VS_PCH R348 VCCASW[19] VCC3_3[2] R349 +1.05VS_PCH
1
0_0603_5% W33 0.1U_0402_10V7K C263 0_0805_5%
+VCCDIFFCLK VCCASW[20]
2 1 AF13 2 1
VCCIO[5]
2 1
+VCCRTCEXT N16 +1.05VS_SATA3
1 DCPRTC
C264 1 AH13 C265
1U_0402_6.3V6K C266 VCCIO[12] 1U_0402_6.3V6K
0.1U_0402_10V7K Y49 AH14 +1.05VS_SATA3 2
+1.05VS_PCH 2 +VCCAFDI_VRM VCCVRM[4] VCCIO[13]
R350
B 0_0603_5% +1.05VS_VCCDIFFCLKN 2 B
2 1 AF14 @ L17 @ R351
@R351 +1.05VS_PCH
+1.05VS_VCCA_A_DPL VCCIO[6] 10UH_LB2012T100MR_20% 0_0805_5%
1 BD47
SATA
VCCADPLLA 80mA +VCCSATAPLL +VCCSATAPLL_R
AK1 1 2 2 1
C267 +1.05VS_VCCA_B_DPL VCCAPLLSATA
BF47
1U_0402_6.3V6K VCCADPLLB 80mA
2 1
AF11 +VCCAFDI_VRM +VCCAFDI_VRM @ C268
+1.05VS_PCH R352 +VCCDIFFCLK VCCVRM[1] R353 +1.05VS_PCH 10U_0603_6.3V6M
AF17
VCCIO[7] +1.05VS_VCC_SATA
0_0603_5% AF33
VCCIO[8]
0_0805_5% Place C296 Near AK1 pin
2 1 +1.05VS_SSCVCC AF34 55mA AC16 +1.05VS_VCC_SATA 2 1 2
VCCIO[9] VCCIO[2]
1 +1.05VS_VCCDIFFCLKN AG34
VCCIO[11]
AC17 1
C269 VCCIO[3] C270
1U_0402_6.3V6K +1.05VS_SSCVCC AG33 AD17 1U_0402_6.3V6K
2 VCCIO[10] 95mA VCCIO[4]
+1.05VS_PCH @ R354 2
0_0603_5% +VCCSST V16 +1.05VS_PCH
+1.05VM_VCCSUS DCPSST
2 1 1
1 C271 +1.05VM_VCCSUS T17 T21 +VCCME_22 R355 2 1 0_0603_5%
0.1U_0402_10V7K DCPSUS[1] VCCASW[22]
V19
DCPSUS[2]
MISC
C272 2
1U_0402_6.3V6K +1.05VS_VCCP R357 V21 +VCCME_23 R356 2 1 0_0603_5%
2 0_0603_5% VCCASW[23]
CPU
1 2 +V_CPU_IO BJ8
V_PROC_IO 1mA +VCCME_21 R358
T19 2 1 0_0603_5%
VCCASW[21]
1 1 1
+RTCVCC +3VALW_PCH
4.7U_0603_6.3V6K
C273
0.1U_0402_10V7K
C274
0.1U_0402_10V7K
C275
RTC
A22 P32 +VCCSUSHDA R359 2 1 0_0603_5%
10mA VCCSUSHDA
HDA
2 2 2 VCCRTC
1U_0402_6.3V6K
C276
0.1U_0402_10V7K
C277
0.1U_0402_10V7K
C278
A
1 1 1 1 A
COUGARPOINT_FCBGA989~D C279
HM65@ 0.1U_0402_16V4Z
2 2 2 2
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2010/12/03 Deciphered Date 2011/12/03 Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Cougar Point(8/9)-PWR2
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
WWW.AliSaler.Com
Custom 0.3
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
PBL80 LA-7441P M/B
Date: Monday, April 11, 2011 Sheet 36 of 59
5 4 3 2 1
5 4 3 2 1
UPCHI
AY4 VSS[159] VSS[259] H46
AY42 VSS[160] VSS[260] K18
AY46 VSS[161] VSS[261] K26
AY8 VSS[162] VSS[262] K39
B11 VSS[163] VSS[263] K46
UPCHH B15 K7
VSS[164] VSS[264]
H5 VSS[0] B19 VSS[165] VSS[265] L18
B23 L2
VSS[166] VSS[266]
AA17 AK38 B27 L20
VSS[1] VSS[80] VSS[167] VSS[267]
AA2 AK4 B31 L26
D VSS[2] VSS[81] VSS[168] VSS[268] D
AA3 AK42 B35 L28
VSS[3] VSS[82] VSS[169] VSS[269]
AA33 AK46 B39 L36
VSS[4] VSS[83] VSS[170] VSS[270]
AA34 AK8 B7 L48
VSS[5] VSS[84] VSS[171] VSS[271]
AB11 AL16 F45 M12
VSS[6] VSS[85] VSS[172] VSS[272]
AB14 AL17 BB12 P16
VSS[7] VSS[86] VSS[173] VSS[273]
AB39 AL19 BB16 M18
VSS[8] VSS[87] VSS[174] VSS[274]
AB4 AL2 BB20 M22
VSS[9] VSS[88] VSS[175] VSS[275]
AB43 AL21 BB22 M24
VSS[10] VSS[89] VSS[176] VSS[276]
AB5 AL23 BB24 M30
VSS[11] VSS[90] VSS[177] VSS[277]
AB7 AL26 BB28 M32
VSS[12] VSS[91] VSS[178] VSS[278]
AC19 AL27 BB30 M34
VSS[13] VSS[92] VSS[179] VSS[279]
AC2 VSS[14] VSS[93] AL31 BB38 VSS[180] VSS[280] M38
AC21 VSS[15] VSS[94] AL33 BB4 VSS[181] VSS[281] M4
AC24 VSS[16] VSS[95] AL34 BB46 VSS[182] VSS[282] M42
AC33 VSS[17] VSS[96] AL48 BC14 VSS[183] VSS[283] M46
AC34 VSS[18] VSS[97] AM11 BC18 VSS[184] VSS[284] M8
AC48 VSS[19] VSS[98] AM14 BC2 VSS[185] VSS[285] N18
AD10 VSS[20] VSS[99] AM36 BC22 VSS[186] VSS[286] P30
AD11 VSS[21] VSS[100] AM39 BC26 VSS[187] VSS[287] N47
AD12 VSS[22] VSS[101] AM43 BC32 VSS[188] VSS[288] P11
AD13 VSS[23] VSS[102] AM45 BC34 VSS[189] VSS[289] P18
AD19 VSS[24] VSS[103] AM46 BC36 VSS[190] VSS[290] T33
AD24 VSS[25] VSS[104] AM7 BC40 VSS[191] VSS[291] P40
AD26 VSS[26] VSS[105] AN2 BC42 VSS[192] VSS[292] P43
AD27 VSS[27] VSS[106] AN29 BC48 VSS[193] VSS[293] P47
AD33 VSS[28] VSS[107] AN3 BD46 VSS[194] VSS[294] P7
AD34 VSS[29] VSS[108] AN31 BD5 VSS[195] VSS[295] R2
AD36 VSS[30] VSS[109] AP12 BE22 VSS[196] VSS[296] R48
AD37 VSS[31] VSS[110] AP19 BE26 VSS[197] VSS[297] T12
AD38 VSS[32] VSS[111] AP28 BE40 VSS[198] VSS[298] T31
AD39 VSS[33] VSS[112] AP30 BF10 VSS[199] VSS[299] T37
AD4 VSS[34] VSS[113] AP32 BF12 VSS[200] VSS[300] T4
C C
AD40 VSS[35] VSS[114] AP38 BF16 VSS[201] VSS[301] W34
AD42 VSS[36] VSS[115] AP4 BF20 VSS[202] VSS[302] T46
AD43 VSS[37] VSS[116] AP42 BF22 VSS[203] VSS[303] T47
AD45 VSS[38] VSS[117] AP46 BF24 VSS[204] VSS[304] T8
AD46 VSS[39] VSS[118] AP8 BF26 VSS[205] VSS[305] V11
AD8 VSS[40] VSS[119] AR2 BF28 VSS[206] VSS[306] V17
AE2 VSS[41] VSS[120] AR48 BD3 VSS[207] VSS[307] V26
AE3 AT11 BF30 V27
VSS[42] VSS[121] VSS[208] VSS[308]
AF10 AT13 BF38 V29
VSS[43] VSS[122] VSS[209] VSS[309]
AF12 AT18 BF40 V31
VSS[44] VSS[123] VSS[210] VSS[310]
AD14 AT22 BF8 V36
VSS[45] VSS[124] VSS[211] VSS[311]
AD16 AT26 BG17 V39
VSS[46] VSS[125] VSS[212] VSS[312]
AF16 AT28 BG21 V43
VSS[47] VSS[126] VSS[213] VSS[313]
AF19 AT30 BG33 V7
VSS[48] VSS[127] VSS[214] VSS[314]
AF24 AT32 BG44 W17
VSS[49] VSS[128] VSS[215] VSS[315]
AF26 AT34 BG8 W19
VSS[50] VSS[129] VSS[216] VSS[316]
AF27 AT39 BH11 W2
VSS[51] VSS[130] VSS[217] VSS[317]
AF29 AT42 BH15 W27
VSS[52] VSS[131] VSS[218] VSS[318]
AF31 AT46 BH17 W48
VSS[53] VSS[132] VSS[219] VSS[319]
AF38 AT7 BH19 Y12
VSS[54] VSS[133] VSS[220] VSS[320]
AF4 AU24 H10 Y38
VSS[55] VSS[134] VSS[221] VSS[321]
AF42 AU30 BH27 Y4
VSS[56] VSS[135] VSS[222] VSS[322]
AF46 AV16 BH31 Y42
VSS[57] VSS[136] VSS[223] VSS[323]
AF5 AV20 BH33 Y46
VSS[58] VSS[137] VSS[224] VSS[324]
AF7 AV24 BH35 Y8
VSS[59] VSS[138] VSS[225] VSS[325]
AF8 AV30 BH39 BG29
VSS[60] VSS[139] VSS[226] VSS[328]
AG19 AV38 BH43 N24
VSS[61] VSS[140] VSS[227] VSS[329]
AG2 AV4 BH7 AJ3
VSS[62] VSS[141] VSS[228] VSS[330]
AG31 AV43 D3 AD47
VSS[63] VSS[142] VSS[229] VSS[331]
AG48 AV8 D12 B43
VSS[64] VSS[143] VSS[230] VSS[333]
AH11 AW14 D16 BE10
VSS[65] VSS[144] VSS[231] VSS[334]
AH3 AW18 D18 BG41
B VSS[66] VSS[145] VSS[232] VSS[335] B
AH36 AW2 D22 G14
VSS[67] VSS[146] VSS[233] VSS[337]
AH39 AW22 D24 H16
VSS[68] VSS[147] VSS[234] VSS[338]
AH40 AW26 D26 T36
VSS[69] VSS[148] VSS[235] VSS[340]
AH42 AW28 D30 BG22
VSS[70] VSS[149] VSS[236] VSS[342]
AH46 AW32 D32 BG24
VSS[71] VSS[150] VSS[237] VSS[343]
AH7 AW34 D34 C22
VSS[72] VSS[151] VSS[238] VSS[344]
AJ19 AW36 D38 AP13
VSS[73] VSS[152] VSS[239] VSS[345]
AJ21 AW40 D42 M14
VSS[74] VSS[153] VSS[240] VSS[346]
AJ24 AW48 D8 AP3
VSS[75] VSS[154] VSS[241] VSS[347]
AJ33 AV11 E18 AP1
VSS[76] VSS[155] VSS[242] VSS[348]
AJ34 AY12 E26 BE16
VSS[77] VSS[156] VSS[243] VSS[349]
AK12 AY22 G18 BC16
VSS[78] VSS[157] VSS[244] VSS[350]
AK3 AY28 G20 BG28
VSS[79] VSS[158] VSS[245] VSS[351]
G26 BJ28
COUGARPOINT_FCBGA989~D VSS[246] VSS[352]
G28
HM65@ VSS[247]
G36
VSS[248]
G48
VSS[249]
H12
VSS[250]
H18
VSS[251]
H22
VSS[252]
H24
VSS[253]
H26
VSS[254]
H30
VSS[255]
H32
VSS[256]
H34
VSS[257]
F3
VSS[258]
COUGARPOINT_FCBGA989~D
HM65@
A A
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2010/12/03 Deciphered Date 2011/12/03 Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Cougar Point(9/9)-GND
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom 0.3
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
PBL80 LA-7441P M/B
Date: Monday, April 11, 2011 Sheet 37 of 59
5 4 3 2 1
5 4 3 2 1
+5VS +5VS_ODD
SATA HDD 2.5" Conn. ODD small board conn R388
0_0805_5%
+VSB 1 2
+5VS
60mil Place component's closely HDD CONN. 80mil
D
6
S
2
0.1U_0402_16V4Z
CS1
1 1 1 1 1 5 4
C298 C299 C300 C301 +5VS_ODD R383 2
10U_0805_10V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z JODD 470K_0402_5% @ 1 Q15
1 SI3456BDV-T1-E3 1N TSOP6
G
2 2 2 2 1 2 @
2
3
2
3
D
HDD 4
5
3
4 ODD_EN D
JHDD2 5
<29> SATA_PTX_DRX_P2 6
6
2
D
1.5M_0402_5%
R380
0.1U_0402_16V4Z
C304
1 7 @ 1
GND SATA_PTX_C_DRX_P1 <29> SATA_PTX_DRX_N2 7
2 C290 1 2 0.01U_0402_25V7K 8 2 Q16
A+ SATA_PTX_C_DRX_N1 SATA_PTX_DRX_P1 <29> 8 <34> ODD_EN#
3 C291 1 2 0.01U_0402_25V7K 9 G SSM3K7002FU_SC70-3 @
A- SATA_PTX_DRX_N1 <29> <29> SATA_PRX_C_DTX_N2 9
4 10 S @
3
GND SATA_PRX_DTX_N1 <29> SATA_PRX_C_DTX_P2 10 2
5 C292 1 2 0.01U_0402_25V7K 11
1
B- SATA_PRX_DTX_P1 SATA_PRX_C_DTX_N1 <29> 11
6 C293 1 2 0.01U_0402_25V7K 12
B+ SATA_PRX_C_DTX_P1 <29> <34> ODD_DETECT# 12
7 <33> ODD_DA# 13 15
GND 13 GND1
14 16
14 GND2
8 E-T_6905-Q14N-00R
V33 @
V33 9
V33 10
GND 11
GND 12
GND 13
V5 14 +5VS
V5 15 60mil
V5 16
GND 17
Reserved 18
GND 19
V12 20
24 GND V12 21
23 GND V12 22
OCTEK_SAT-22ABAB
@
C C
+3VS
SATA HDD 3.5" Conn. MAXIM@: MAX4951BECTP+TGH7 (Defult) MAXIM@ MAXIM@
TI@: SN75LVCP601TJR
2
DEN@ DEN@
2
0_0402_5%
R493
0_0402_5%
R494
0_0402_5%
R504
0_0402_5%
R503
0_0402_5%
R496
0_0402_5%
R495
DEN@: Preemphasis Enable (Defult)
+5VS +12VS 20mil
60mil Place component's closely HDD CONN. 80mil NDEN@: Standard SATA putput
EQ@: Equalization maximum +3VS
1
1 1 1 1 1 1 1 1 NEQ@: Equalization normal (Defult)
1
C280 C281 C282 C283 C500 C303 C501 C302 NEQ@ NEQ@
10U_0805_10V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 1U_0603_10V6K 10U_0805_10V4Z 1U_0603_10V6K 0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.01U_0402_25V7K
2 2 2 2 2 2 2 2 +HDD_EQ1
1 2
C309
C417
+HDD_EQ2
+HDD_DEW1
HDD Repeater 2 1
+HDD_DEW2
DE1
DE2
All close to JHDD1
HDD
2
TI@ TI@ EQ@ EQ@
0_0402_5%
R499
0_0402_5%
R500
10K_0402_5%
R334
10K_0402_5%
R361
0_0402_5%
R502
R
0_0402_5%
R501
R
U25
502
501
JHDD1 7 6 +HDD_DEW2
B EN VCC B
1 18 10
GND SATA_PTX_C_DRX_P0 C398 1 PSATA_PTX_DRX_P0_RP CAD VCC +HDD_DEW1
2 2 0.01U_0402_25V7K 0.01U_0402_25V7K 16
1
A+ SATA_PTX_C_DRX_N0 C344 1 PSATA_PTX_DRX_N0_RP PSATA_PTX_DRX_P0 1 VCC
A-
3 2 0.01U_0402_25V7K <29> SATA_PTX_DRX_P0
C418 1 2 SATARP@ AINP VCC
20
4 C391 1 2 SATARP@ PSATA_PTX_DRX_N0 2
GND <29> SATA_PTX_DRX_N0 AINM
5 SATA_PRX_DTX_N0 C339 1 2 0.01U_0402_25V7K PSATA_PRX_DTX_N0_RP 0.01U_0402_25V7K 9 DE1 NDEN@ NDEN@
B- SATA_PRX_DTX_P0 C348 1 PSATA_PRX_DTX_P0_RP PSATA_PRX_DTX_N0 4 PA DE2
6 2 0.01U_0402_25V7K <29> SATA_PRX_C_DTX_N0
C389 1 2 0.01U_0402_25V7K 8
B+ PSATA_PRX_DTX_P0 5 BOUTM PB
7 <29> SATA_PRX_C_DTX_P0 1 2 SATARP@
GND C392 SATARP@ BOUTP PSATA_PTX_DRX_P0_RP
15
0.01U_0402_25V7K AOUTP PSATA_PTX_DRX_N0_RP
3 14
GND AOUTM
8 13
V33 +HDD_EQ1 GND PSATA_PRX_DTX_P0_RP
9 17 11
V33 +HDD_EQ2 GND BINP PSATA_PRX_DTX_N0_RP
10 19 12
V33 GND BINM
11 21
GND EP
12
GND MAX4951BECTP+TGH7_TQFN20_4X4~D
13
GND MAXIM@
14
V5
V5
15 +5VS 60mil
16
V5
17
GND
18
Reserved U25
19
GND
V12
20 Note: +HDD_DEW1, +HDD_DEW2, +HDD_EQ1, +HDD_EQ2 need to route
24
GND V12
21 +12VS 80mil 10 mils
23 22
GND V12
OCTEK_SAT-22ABAB
@ SN75LVCP601RTJR_QFN20_4X4
TI@
PSATA_PTX_DRX_P0_RP 2 R505 1 SATA@ 0_0402_5%
SATA_PTX_DRX_P0 <29>
PSATA_PTX_DRX_N0_RP 2 R506 1 SATA@ 0_0402_5%
SATA_PTX_DRX_N0 <29>
PSATA_PRX_DTX_N0_RP 2 R507 1 SATA@ 0_0402_5%
A PSATA_PRX_DTX_P0_RP SATA_PRX_C_DTX_N0 <29> A
2 R508 1 SATA@ 0_0402_5%
SATA_PRX_C_DTX_P0 <29>
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2010/12/03 Deciphered Date 2011/12/03 Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SATA-HDD&ODD/B
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
WWW.AliSaler.Com
0.3
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
PBL80 LA-7441P M/B
Date: Monday, April 11, 2011 Sheet 38 of 59
5 4 3 2 1
5 4 3 2 1
Touch pad & LID & Slot 1 Half PCIe Mini Card-WLAN & BT3.0
Card Reader & LED small board Connector WLAN/ WiFi +1.5VS +3VS
JWLAN
W=60mils
1 2
COMBO@ 1 2
3 4
D 3 4 D
<43> BT_PWRON 1 2 BT_PWRON_R 5 6
RH31 0_0402_5% 5 6
<30> CLKREQ_WLAN# 7 8
JFUN 7 8
9 10
9 10
+5VALW 1 <30> CLK_WLAN# 11 12
1 11 12
+5VS 2 <30> CLK_WLAN 13 14
2 13 14
3 15 16
3 15 16
<43> TP_CLK 4 17 18
4 17 18
<43> TP_DATA 5 19 20 WL_OFF# <43>
5 19 20 PLT_RST#
1 1 +3VS 6 21 22 PLT_RST# <5,33>
@ @ 6 21 22
7 <30> PCIE_PRX_WLANTX_N2 23 24
7 23 24
C404
100P_0402_50V8J
C403
100P_0402_50V8J
8 <30> PCIE_PRX_WLANTX_P2 25 26 1 2
8 25 26 RH32 0_0402_5%
9 9 27 27 28 28
2 2 10 29 30
<33> USB20_N11 10 29 30 PM_SMBCLK <12,13,30>
<33> USB20_P11 11 11 <30> PCIE_PTX_C_WLANRX_N2 31 31 32 32 PM_SMBDATA <12,13,30>
12 12 <30> PCIE_PTX_C_WLANRX_P2 33 33 34 34
<43,44> PWR_ON_LED# 13 13 35 35 36 36 USB20_N13 <33>
<43> BATT_CHG_LOW_LED# 14 14 37 37 38 38 USB20_P13 <33> Bluetooth 3.0
<43> BATT_FULL_LED# 15 15 +3VS 39 39 40 40
<43> WL_BT_LED# 16 16 41 41 42 42
<29> SATA_LED# 17 17 43 43 44 44
<43> NUM_LED# 18 18 45 45 46 46
<43> CAPS_LED# 19 19 47 47 48 48
20 20 49 49 50 50
21 G1 51 51 52 52
22 G2 R366 Debug@ 53 54
0_0402_5% GND1 GND2
ACES_85201-2005N 1 2 BELLW_80003-1121
<43> E51_TXD
@ 1 2 @
<43> E51_RXD
R365
Debug card using 0_0402_5%
C C
1
BT_PWRON 1 BT@ 2
+3VS +1.5VS
100K_0402_5% RW3 1K_0402_1%
R367 0.1U_0402_16V4Z 0.1U_0402_16V4Z
1 1 1 1
1
Support Intel rainbow peak combo module. CM1 CM2 CM3 CM4 CM5 CM6
Defult is BT@, COMBO@ is no stuff.
2
2 2 2 2
47P_0402_50V8J 4.7U_0805_10V4Z 47P_0402_50V8J 4.7U_0805_10V4Z
For SED request For SED request
B B
USB & LID/B
Right USB X 3
+5VALW
W=120mils ACES_85203-2002
21 1
21 1
22 2
22 2
23 3
23 3
24 4
24 4
25 5
25 5
+3VALW 26 6
26 6
<33> USB_OC1# 27 7
27 7
<33> USB_OC0# 28 8
USB_EN# 28 8
<43,45> USB_EN# 29 9
LID_SW# 29 9
<43> LID_SW# 30 10
30 10
31 11
31 11
<33> USB20_N2 32 12
32 12
<33> USB20_P2 33 13
33 13
34 14
34 14
<33> USB20_N1 35 15
35 15
<33> USB20_P1 36 16
36 16
37 17
37 17
<33> USB20_N0 38 18
38 18
<33> USB20_P0 39 19
39 19
40 20
40 20
A @ JUSB A
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2010/12/03 Deciphered Date 2011/12/03 Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
USB/LID/B&TP/LED/CR/B&PCIe-WLAN
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
0.3
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
PBL80 LA-7441P M/B
Date: Monday, April 11, 2011 Sheet 39 of 59
5 4 3 2 1
A B C D E
UL1 8111EVB@
+LAN_VDD10
Close to Pin 27,39,12,47,48,42
0.1U_0402_16V7K
<30> PCIE_PRX_C_LANTX_P1 CL1 1 2 PCIE_PRX_LANTX_P1 22 31 CL5,CL6,CL7,CL8,CL9
0.1U_0402_16V7K HSOP LED3/EEDO LL1
37
CL2 1 2 PCIE_PRX_LANTX_N1 23 LED1/EESK
40 +LAN_REGOUT 1 2 close to Pin 27,39,42,47,48
+3V_LAN <30> PCIE_PRX_C_LANTX_N1 HSON LED0 2.2UH +-5% NLC252018T-2R2J-N
@ PCIE_PTX_C_LANRX_P1 17 30 RL1 2 1 10K_0402_5% +3V_LAN
<30> PCIE_PTX_C_LANRX_P1 HSIP EECS/SCL 1 2
1 2 EC_SWI# PCIE_PTX_C_LANRX_N1 18 32 RL2 2 1 10K_0402_5%
<30> PCIE_PTX_C_LANRX_N1 HSIN EEDI/SDA Layout Note: LL1 must be
RL4 100K_0402_5% CL3 CL4
within 200mil to Pin36, 4.7U_0603_6.3V6K 0.1U_0402_16V4Z 1 2
RL3 0_0402_5% 16 1 LAN_MDI0+ CL3,CL4 must be within 2 1 0.1U_0402_16V4Z CL5
<30> CLKREQ_LAN# CLKREQB MDIP0 200mil to LL1
RTL8105E RTL8111E 2 LAN_MDI0- 1 2
1 MDIN0 LAN_MDI1+ 0.1U_0402_16V4Z CL6 1
<33,43,45> PCH_PLT_RST# 25 4
PERSTB MDIP1 LAN_MDI1-
Pin14 NC NC MDIN1
5 1 2
CLK_LAN 19 7 LAN_MDI2+ 0.1U_0402_16V4Z CL7
<30> CLK_LAN CLK_LAN# REFCLK_P NC/MDIP2 LAN_MDI2-
Pin15 NC 10K ohm PD <30> CLK_LAN# 20
REFCLK_N NC/MDIN2
8 1 2
10 LAN_MDI3+ Close to Pin 21 0.1U_0402_16V4Z CL8
NC/MDIP3 LAN_MDI3-
Pin38 1K ohm Pull-high NC/MDIN3
11 1 2
LAN_X1 43 0.1U_0402_16V4Z CL9
CKXTAL1
1 2
YL1 LAN_X2 44 13 +LAN_VDD10 +LAN_EVDD10 0.1U_0402_16V4Z CL21 8111E@
CKXTAL2 DVDD10 +LAN_VDD10
LAN_X1 1 2 LAN_X2 29
DVDD10
41 2 1
25MHZ_20PF_7A25000012 EC_SWI# DVDD10 0_0603_5% LL2
<31,45> EC_SWI# 28 LANWAKEB 1 2
1 1
ISOLATEB 26 27 +3V_LAN CL10 CL11
ISOLATEB DVDD33
CL22 CL23
DVDD33 39 1U_0402_6.3V4Z
2 1
0.1U_0402_16V4Z Close to Pin 3,6,9,13,29,41,45
33P_0402_50V8K 33P_0402_50V8K
2 2 14 NC/SMBCLK AVDD33 12 +3V_LAN CL12,CL13,CL14,CL15
RL7 2 8111E@ 1 10K_0402_5% 15 42
+3VS RL8 1 8111E@ 2 1K_0402_5% 38
NC/SMBDATA AVDD33
47 close to Pin 3,13,29,45
+3V_LAN GPO/SMBALERT AVDD33
AVDD33 48
1
ENSWREG 33 Using Switch Regulator +LAN_VDD10
RL5 ENSWREG
EVDD10 21 +LAN_EVDD10
1K_0402_1% +LAN_VDDREG 34 1 2
VDDREG +3V_LAN +LAN_VDDREG 0.1U_0402_16V4Z CL12
35 VDDREG AVDD10 3 +LAN_VDD10
6 1 2
2
ISOLATEB AVDD10 0.1U_0402_16V4Z CL13
AVDD10 9 2 1
1 2 46 45 0_0603_5% LL3 1 2 1 2
RL9 2.49K_0402_1% RSET AVDD10 0.1U_0402_16V4Z CL14
24 36 +LAN_REGOUT CL18 CL19 1 2
GND REGOUT
RL6 49 PGND 60 mils 4.7U_0603_6.3V6K
2 1
0.1U_0402_16V4Z 0.1U_0402_16V4Z CL15
15K_0402_5% 1 2
2 0.1U_0402_16V4Z CL16 8111E@ 2
RTL8111E-GR_QFN48_6X6 1 2
0.1U_0402_16V4Z CL17 8111E@
1 2
0.1U_0402_16V4Z CL20 8111E@
+3V_LAN
+3VALW TO +3V_LAN
+3VALW RL12
0_0402_5%
+3VALW
ENSWREG
1
2
RL147 CL483
100K_0402_5% UL2 8111E@ RL13
0.1U_0402_16V7K CL24 1000P_0402_50V7K 0_0402_5%
2
1 1 24 2 1 1 8111E@ 2 @
2
TCT1 MCT1
3
S
RL432 QL51 PJ4 LAN_MDI3- 2 23 RJ45_MIDI3- 8111E@ RL14 75_0402_1%
2
G
LAN_MDI3+ TD1+ MX1+ RJ45_MIDI3+
<43> WOL_EN# 1 2 2 JUMP_43X79 3 22
@ TD1- MX1- CL25 1000P_0402_50V7K
+3V_LAN LAN Conn.
1
47K_0402_5% 2 AO3413_SOT23 D 4 21 2 1 1 8111E@ 2
1
LAN_MDI2- TCT2 MCT2 RJ45_MIDI2- 8111E@ RL15 75_0402_1%
5 20
1
CL482 LAN_MDI2+ TD2+ MX2+ RJ45_MIDI2+
6 19
TD2- MX2- CL26 1000P_0402_50V7K
0.01U_0402_25V7K
Vgs=-4.5V,Id=3A,Rds<97mohm 1 7 18 2 1 1 2
1 TCT3 MCT3
1 LAN_MDI1- 8 17 RJ45_MIDI1- RL16 75_0402_1% JLAN
CL682 LAN_MDI1+ TD3+ MX3+ RJ45_MIDI1+
9 16
CL681 1U_0402_6.3V6K TD3- MX3- CL27 1000P_0402_50V7K
4.7U_0805_10V4Z 2
10 15 2 1 1 2
3 2 LAN_MDI0- TCT4 MCT4 RJ45_MIDI0- RL17 75_0402_1% 3
11 14
LAN_MDI0+ TD4+ MX4+ RJ45_MIDI0+ RJ45_MIDI3-
12 13 8
TD4- MX4- PR4-
0.1U_0402_25V4K 1 RJ45_MIDI3+ 7
CL31 RJ45_GND PR4+
+3V_LAN rising time (10%~90%) need > 1ms and <100ms. RJ45_MIDI1- 6
Place CL31 close SUPERWORLD_SWG150401 PR2-
1
to LAN chip 2 RJ45_MIDI2- 5 DL7 AZC199-02SPR7G_SOT23-3
PR3-
1
RJ45_MIDI2+ 4
PR3+
3
DL1 RJ45_MIDI1+ 3
LAN_MDI1+ LAN_MDI0+ PR2+
6 3
3
I/O4 I/O2 RJ45_MIDI0- 2
PR1-
10
RJ45_MIDI0+ SHLD2
1 9
PR1+ SHLD1
For P/N and footprint +LAN_IO 5
VDD GND
2
3
Please place them to ISPD page
3
@
UL1 LAN_MDI1- 4 1 LAN_MDI0-
I/O3 I/O1
1
SANTA_130452-0F1
AZC099-04S.R7G_SOT23-6 @ DL8 AZC199-02SPR7G_SOT23-3
1
8111E_VL 1000P_1808_3KV7K
8111EVL@ DL2 RJ45_GND 1 2 LANGND
LAN_MDI3+ 6 3 LAN_MDI2+ CL28 1 1
I/O4 I/O2
UL1
CL29 CL30
4
5 2 2 2 4
+LAN_IO VDD GND
0.1U_0402_16V4Z
4.7U_0603_6.3V6K
8105E 10/100M LAN_MDI3- 4 1 LAN_MDI2-
8105E@ I/O3 I/O1
AZC099-04S.R7G_SOT23-6
UL2
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2010/12/03 Deciphered Date 2011/12/03 Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
PCIe-LAN-RTL8105E/8111E
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
WWW.AliSaler.Com
10/100M transformer Custom 0.3
8105E@
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
PBL80 LA-7441P M/B
Date: Monday, April 11, 2011 Sheet 40 of 59
A B C D E
5 4 3 2 1
BIOS Bus switch
SPI ROM For Basic ME ROM size
4MByte
D D
1. When Flash EC ROM. 3.When normal operation.
KSO2 to Low (Test mode) EC_ON->High , BUS_EN#->Low.
KSO3 to Low (ISP mode)---------FDA mode U11 : Y->A0, PCH direct to BIOS ROM.
EC_ON->Low, BUS_EN#->Low +3V_SPI from +3VS.
U11 : Y->A0, PCH to BIOS ROM.
KSI4,5,6,7 direct to EC_SPI 4. When enter S3,4
EC_ON->High, BUS_EN#->Low.
U11 : Y->A1, PCH direct to BIOS ROM.
But +3V_SPI from +3VS is no power.
2. When Flash BIOS ROM.
KSO2 to High ** BUS_EN# only high when test mode.
KSO3 to Low (ISP mode) And must make sure it's low when FDA mode.
EC_ON->High, BUS_EN#->High. Or HW use 10K pull down to GND.
U11 : Y->A1, KSI4,5,6,7 to BIOS ROM.
+3V_SPI from +3VALW
Set EC pin KSI4,5,6,7 to HiZ.
<29> PCH_SPI_CLK 2 R1553 1 33_0402_5%PCH_SPI_R_CLK
+3VALW
+3V_SPI
@ C421 @ R433 U12
2 1 2 1 PCH_SPI_R_CLK 1
C VDD FLASH_EN C
4 VDD SEL 12
6P_0402_25V 10_0402_5% 9 VDD
19 VDD YA 2
For EMI resuest. YB 5 PCH_SPI_CS0#_R
24 6 PCH_SPI_CLK_R 1
+3VS A0 YC
PCH_SPI_CS0# 22 C419
<29> PCH_SPI_CS0# B0
PCH_SPI_R_CLK 18 8 PCH_SPI_MOSI_R 0.1U_0402_16V4Z
PCH_SPI_MOSI C0 YD PCH_SPI_MISO_R
<29> PCH_SPI_MOSI 17 11
PCH_SPI_MISO D0 YE 2
<29> PCH_SPI_MISO 14
E0
+3VALW 23 3
KSI4 A1 GND
<43,44> KSI4 21 7
KSI5 B1 GND
<43,44> KSI5 16 10
KSI6 C1 GND
<43,44> KSI6 15 20
KSI7 D1 GND
<43,44> KSI7 13
E1 +3VALW
PI3V512QE_QSOP24
2
100K_0402_5%
@
R439
+3VALW
1
FLASH
5
U8
R31 2 1 10K_0402_5% FLASH_EN EC_ON 2 Q27
P
<43,44,49> EC_ON B
1
FLASH_EN D
4
Y
2N7002_SOT23-3
FLASH 1 2
A <43,45,46,51,58> SYSON
G
G
@ S
3
NC7SZ08P5X_NL_SC70-5 @
B FLASH_EN B
<43> BUS_EN# 2 R1552 1 0_0402_5%
BIOS SPI Flash (4MByte*1)
U59
PCH_SPI_MOSI_R 5
SI SO
2 PCH_SPI_MISO_R For EMI resuest.
PCH_SPI_CLK_R 6
SCLK
PCH_SPI_CS0#_R 1
CS @ C361 @ R419
7 2 1 2 1 PCH_SPI_CLK_R
HOLD
3 6P_0402_25V 10_0402_5%
WP
+3V_SPI 8 4 1 2
VCC GND C402 12P_0402_50V8J
A MX25L3205AZMC-20G_SON8 A
1
C405
0.1U_0402_16V4Z
2
P/N: SA00003K800
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2010/12/03 Deciphered Date 2011/12/03 Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Bus switch&BIOSROM
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
0.3
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
PBL80 LA-7441P M/B
Date: Monday, April 11, 2011 Sheet 41 of 59
5 4 3 2 1
5 4 3 2 1
Sense Pin Impedance Codec Signals Function
39.2K PORT-I (PIN 32, 33) Headphone out
SENSE A RA1
+PVDD1 600 mA 0.1U_0402_16V4Z 2 1 0.1U_0402_16V4Z +5VS
0_0603_5% RA3 20K PORT-B (PIN 21, 22) 0_0603_1%
1 2 +DVDD_IO Ext. MIC CA1
1 1
CA3
1 1
+3VS
CA2 CA4
2
1 1 2 2 2 2
JA1
2
CA9 CA7 JUMP_43X39 10U_0805_10V4Z 10U_0805_10V4Z
10U_0805_10V4Z 0.1U_0402_16V4Z
2 2
1
D
@ place close to chip D
place close to chip
1
+PVDD2 +AVDD
68 mA RA8 RA4
+PVDD1 0.1U_0402_16V4Z 2 1 +PVDD2 2 1 0.1U_0402_16V4Z
+3VS_DVDD +5VS +5VS
0_0603_5% RA2 0_0603_1% 1 1 0_0603_1% 1 1
1 2 35 mA 0.1U_0402_16V4Z CA10 @ CA11 CA12
+3VS
1 1 1 1 1 CA8 @ @ @
CA15 CA20 CA17
CA5 CA6 2 2 2 2
10U_0805_10V4Z 0.1U_0402_16V4Z 10U_0805_10V4Z 10U_0805_10V4Z
2 2 2 2 2
39
46
25
38
1
9
U7 10U_0805_10V4Z 0.1U_0402_16V4Z
place close to chip
DVDD_IO
PVDD1
PVDD2
AVDD1
AVDD2
DVDD
place close to chip
placement near Audio Codec
23 40 SPKL+
LINE1_L SPK_OUT_L+ SPKL- RA9
24 LINE1_R SPK_OUT_L- 41
AZ_BITCLK_HD SPKL+ 2 1 SPK_L1
14 45 SPKR+ 0_0603_1% 1
LINE2_L SPK_OUT_R+ SPKR- CA21
15 LINE2_R SPK_OUT_R- 44
1
MIC1_LINE1_R_L CA14 1 2 4.7U_0603_6.3V6K MIC1_C_L 21 32 RA15 75_0402_1% HP_L R370 @ 10U_0805_10V4Z 2
MIC1_LINE1_R_R CA13 1 MIC1_C_R MIC1_L HP_OUT_L HP_R 2
2 4.7U_0603_6.3V6K 22 33 RA14 75_0402_1% 10_0402_5% CA22
MIC1_R HP_OUT_R 1U_0402_6.3V4Z
1
16 CA23 @
2
MIC2_L 1
17 MIC2_R
10 AZ_SYNC_HD @ 10U_0805_10V4Z
SYNC AZ_SYNC_HD <29> 2
1 SPKL- 2 1 SPK_L2
DMIC_DATA R1543 1 2 0_0402_5% DMIC_DATA_CODEC 2 6 AZ_BITCLK_HD RA12
<27> DMIC_DATA GPIO0/DMIC_DATA BCLK AZ_BITCLK_HD <29>
C310 0_0603_1%
C DMIC_CLK C
<27> DMIC_CLK R1544 1 2 0_0402_5% DMIC_CLK_CODEC 3 GPIO1/DMIC_CLK 10P_0402_50V8J SPKR+ 2 1 SPK_R1
AZ_SDOUT_HD 2 RA13
SDATA_OUT 5 AZ_SDOUT_HD <29> 1
0_0603_1% CA25
EC_MUTE# 4 8 AZ_SDIN0_HD_R 2 1
<43> EC_MUTE# PD# SDATA_IN AZ_SDIN0_HD <29>
RA16 33_0402_5% @ 10U_0805_10V4Z 2
2 CA26
AZ_RST_HD# 11 47 EAPD 1 1U_0402_6.3V4Z
<29> AZ_RST_HD# RESET# EAPD EAPD <43>
place close to chip 48
CA27
1
@
SPDIFO @ 10U_0805_10V4Z
12
PCBEEP SPKR- 2 SPK_R2
20 2 1
RA19 20K_0402_1% MONO_OUT RA18
MIC_PLUG# 1 2 SENSE_A 13 0_0603_1%
HP_PLUG# SENSE A
1 2 29
RA20 39.2K_0402_1% MIC2_VREFO
18
SENSE B
30 +MIC1_VREFO_R
MIC1_VREFO_R DA1
36 28
CBP LDO_CAP
2
+3VS 2 1 35 27 AC97_VREF 0.1U_0402_16V7K 1
CA32 2.2U_0603_16V6K CBN VREF
1 3
31 19 AC_JDREF 1 RA17 2 1 1 CA28
+MIC1_VREFO_L MIC1_VREFO_L JDREF
1
20K_0402_1% @ PESD5V0U2BT_SOT23-3
R125 43 34 1 2 CA29 CA31 10U_0805_10V6K JSPK @
PVSS2 CPVEE CA30 2 SPK_L1
42 4
4.7K_0402_5%
49
7
PVSS1
DVSS2 AVSS1
26
37
2.2U_0603_16V6K 2 2
SPEAKER CONN SPK_L2
SPK_R1
3
2
4
3
2
AZ_RST_HD# DVSS1 AVSS2 10U_0805_10V6K SPK_R2 2
1
ALC269Q-VB5-GR_QFN48_7X7 1
1
DA2 ACES_85205-0400
C196 2
0.1U_0402_16V4Z ESD 1
2 DGND AGND 3
B B
PESD5V0U2BT_SOT23-3
JHP
1
HP_L 1 R451 2 HP_L_1 2
0_0603_5% 6
HP_R 1 R452 2 HP_R_1 3
0_0603_5%
68P_0402_50V8J
68P_0402_50V8J
4 GND 7
@ @
1 1
Ext.MIC/LINE IN JACK
3
HP_PLUG# 5 GND 8
C311 C399 CA34 1 2 0.1U_0603_50V7K
D21 SUYIN_010188FR006G109ZL 1 RA25 2 +MIC1_VREFO_R
SM05T1G_SOT23-3 2 2 @ 2.2K_0402_5% CA35 1 2 0.1U_0603_50V7K
MIC1_LINE1_R_R 1 RA27 2 MIC1_R
1K_0402_5% CA36 1 2 0.1U_0603_50V7K
1
MIC1_LINE1_R_L 1 RA29 2 MIC1_L CA37 1 2 0.1U_0603_50V7K
1K_0402_5%
JMIC 1 RA30 2 +MIC1_VREFO_L 1 2
1 2.2K_0402_5% RA28 0_0603_5%
MIC1_L 1 R453 2 MIC1_L_L 2
0_0603_5% 6
MIC1_R 1 R454 2
0_0603_5%
MIC1_R_L 3 HP CONN & MIC CONN
100P_0402_50V8J
100P_0402_50V8J
@ 4 GND 7
@ 1 1
3
C401 MIC_PLUG# 5 GND 8
A C400 A
D25 SUYIN_010188FR006G109ZL
SM05T1G_SOT23-3 2 2 @
1
DA3 Security Classification Compal Secret Data Compal Electronics, Inc.
2 HP_PLUG# 2010/12/03 2011/12/03 Title
Issued Date Deciphered Date
1
3 MIC_PLUG#
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
HD CODEC ALC269
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
WWW.AliSaler.Com
PESD5V0U2BT_SOT23-3 0.3
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
PBL80 LA-7441P M/B
Date: Monday, April 11, 2011 Sheet 42 of 59
5 4 3 2 1
5 4 3 2 1
ID BRD ID Ra Rb Vab
@ C406 @R431
@ R431
+3V_EC
0 R01 SR 100K 0 0V
2 1 2 1 CLK_PCI_EC
+3V_EC
6P_0402_25V 10_0402_5% 0.1U_0402_16V4Z 0.1U_0402_16V4Z 1 R02 ER 100K 8.2K 0.25V
For EMI 1 1 C314 1 1 2 2 C312 0.1U_0402_16V4Z
C313 1 2
C315 C316 C317 C318 2 R03 PR 100K 18K 0.5V
1000P_0402_50V7K1000P_0402_50V7K
2 2 2 2 1 1
C308
111
125
0.1U_0402_16V4Z 0.1U_0402_16V4Z 3 R10 MP 100K 33K 0.82V
22
33
96
67
UE1
9
@
1 2 SUSP#
VCC
VCC
VCC
VCC
VCC
VCC
AVCC
D D
0.1U_0402_16V4Z +3VALW
GATEA20 1 21 CPU1.5V_S3_GATE Ra
<34> GATEA20 GA20/GPIO00 INVT_PWM/PWM1/GPIO0F CPU1.5V_S3_GATE <9>
For ESD request, near U9. <34> KB_RST#
KB_RST# 2
KBRST#/GPIO01 BEEP#/PWM2/GPIO10
23
SERIRQ 3 26 BRDID R1603 1 2 100K_0402_5%
<29> SERIRQ LPC_FRAME# 4 SERIRQ# FANPWM1/GPIO12
<29> LPC_FRAME# 27
LPC_AD3 LFRAME# ACOFF/FANPWM2/GPIO13 ACOFF <47> R1606 2
C323 <29> LPC_AD3 5
LAD3 1 18K_0402_5%
LPC_AD2 7 PWM Output
<29> LPC_AD2 LAD2
LPC_AD1 8 63 BATT_TEMP Rb
GATEA20 <29> LPC_AD1 LPC_AD0 LAD1 BATT_TEMP/AD0/GPIO38 BATT_TEMP <47>
1 2 LAD0 LPC & MISC
<29> LPC_AD0 10 64
BATT_OVP/AD1/GPIO39 ADP_I
ADP_I/AD2/GPIO3A 65 ADP_I <47,48>
CLK_PCI_EC 12 AD Input 66 ADAPTER_ID
0.1U_0402_16V4Z <33> CLK_PCI_EC PCICLK AD3/GPIO3B
PCH_PLT_RST# 13 75 BRDID
<33,40,45> PCH_PLT_RST# ECRST# PCIRST#/GPIO05 AD4/GPIO42
37 ECRST# SELIO2#/AD5/GPIO43 76 1 2 +3V_EC
For ESD request <34> EC_SCI# EC_SCI# 20 SCI#/GPIO0E
R19 100K_0402_5%
38 120W@
CLKRUN#/GPIO1D ADAPTER_ID
DAC_BRIG/DA0/GPIO3C 68
70 EN_DFAN1
+3V_EC EN_DFAN1/DA1/GPIO3D EN_DFAN1 <5>
DA Output IREF/DA2/GPIO3E 71 1 2
R379 47K_0402_5% KSI0 55 72 R29 100K_0402_5%
ECRST# KSI1 KSI0/GPIO30 DA3/GPIO3F 90W@
2 1 56
KSI2 KSI1/GPIO31
57 KSI2/GPIO32
2 1 KSI3 58 83 EC_MUTE#
KSI4 KSI3/GPIO33 PSCLK1/GPIO4A USB_EN# EC_MUTE# <42>
C320 0.1U_0402_16V4Z 59 84
KSI5 KSI4/GPIO34 PSDAT1/GPIO4B USB_EN# <39,45>
60 KSI5/GPIO35 PSCLK2/GPIO4C 85
+3V_EC KSI6 61 PS2 Interface 86 WOL_EN#
KSI7 KSI6/GPIO36 PSDAT2/GPIO4D TP_CLK WOL_EN# <40>
62 87 R371
KSO3 KSO0 KSI7/GPIO37 TP_CLK/PSCLK3/GPIO4E TP_DATA TP_CLK <39>
1 @ 2 39 88 0_0402_5%
KSO0/GPIO20 TP_DATA/PSDAT3/GPIO4F TP_DATA <39>
R381 47K_0402_5% KSO1 40 VR_HOT# 2 1 H_PROCHOT# <5>
KSO2 KSO2 KSO1/GPIO21 <47,55> VR_HOT#
1 @ 2 41
R382 47K_0402_5% KSO3 KSO2/GPIO22 SUSACK#
42 KSO3/GPIO23 SDICS#/GPXOA00 97 SUSACK# <31>
1
C KSO4 WL_OFF# D C
43 KSO4/GPIO24 SDICLK/GPXOA01 98 WL_OFF# <39>
KSO5 AZ_SDO H_PROCHOT#_EC
44 KSO5/GPIO25 Int. K/B 99 AZ_SDO <29> 2
KSO6 SDIDO/GPXOA02 VGATE
to avoid EC entry ENE test mode 45 KSO6/GPIO26 Matrix SDIDI/GPXID0 109 VGATE <5,31,55>
G
KSO7 46 SPI Device Interface Q17 S
3
KSO8 KSO7/GPIO27 2N7002_SOT23
47 KSO8/GPIO28
KSI[0..7] KSO9 48 119 EC_SI_SPI_SO EC_SI_SPI_SO <44>
<41,44> KSI[0..7] KSO9/GPIO29 SPIDI/RD#
KSO10 49 120 EC_SO_SPI_SI
KSO[0..15] KSO10/GPIO2A SPIDO/WR# EC_SO_SPI_SI <44> +3VS
KSO11 50 SPI Flash ROM 126 SPI_CLK
<44> KSO[0..15] KSO12 KSO11/GPIO2B SPICLK/GPIO58 SPI_CS# SPI_CLK <44>
51 128 SPI_CS# <44>
KSO13 KSO12/GPIO2C SPICS#
52
KSO14 KSO13/GPIO2D
53
KSO15 KSO14/GPIO2E PM_PWROK BKOFF# R372
54 73 PM_PWROK <31> 1 2 10K_0402_5%
R384 2.2K_0402_5% KSO15/GPIO2F CIR_RX/GPIO40 EC_PECI RE2
81
KSO16/GPIO48 CIR_RLC_TX/GPIO41
74 1 2 43_0402_1% H_PECI <5,34>
+3V_EC 1 2 EC_SMB_CK1 82 89
R385 2.2K_0402_5% KSO17/GPIO49 FSTCHG/SELIO#/GPIO50 BATT_FULL_LED# +5VS
90 BATT_FULL_LED# <39>
BATT_CHGI_LED#/GPIO52
1 2 EC_SMB_DA1 91 CAPS_LED#
CAPS_LED# <39>
R386 2.2K_0402_5% EC_SMB_CK1 CAPS_LED#/GPIO53 BATT_CHG_LOW_LED# TP_CLK
<47,48> EC_SMB_CK1 77
SCL1/GPIO44 GPIO BATT_LOW_LED#/GPIO54
92 BATT_CHG_LOW_LED# <39>
R374 1 2 4.7K_0402_5%
+3VS 1 2 EC_SMB_CK2 <47,48> EC_SMB_DA1
EC_SMB_DA1 78
SDA1/GPIO45 SUSP_LED#/GPIO55
93 PWR_ON_LED#
PWR_ON_LED# <39,44>
R387 2.2K_0402_5% EC_SMB_CK2 79 SM Bus 95 SYSON
<15,30> EC_SMB_CK2 SCL2/GPIO46 SYSON/GPIO56 SYSON <41,45,46,51,58>
1 2 EC_SMB_DA2 <15,30> EC_SMB_DA2
EC_SMB_DA2 80
SDA2/GPIO47 VR_ON/XCLK32K/GPIO57
121 VR_ON
VR_ON <55>
TP_DATA R375 1 2 4.7K_0402_5%
127 PM_SLP_S4#
AC_IN/GPIO59 PM_SLP_S4# <31>
+3V_EC
PM_SLP_S3# 6 100 PCH_RSMRST#
<31> PM_SLP_S3# PM_SLP_S5# PM_SLP_S3#/GPIO04 EC_RSMRST#/GPXO03 LID_SW_OUT# PCH_RSMRST# <29,31> LID_SW#
<31> PM_SLP_S5# 14 101 LID_SW_OUT# <30> 1 2 R377
EC_SMI# PM_SLP_S5#/GPIO07 EC_LID_OUT#/GPXO04 47K_0402_5%
<34> EC_SMI# 15 102
BUS_EN# EC_SMI#/GPIO08 EC_ON/GPXO05 BT_PWRON
<41> BUS_EN# 16 103 BT_PWRON <39>
WL_BT_LED# LID_SW#/GPIO0A EC_SWI#/GPXO06 H_PROCHOT#_EC
<39> WL_BT_LED# 17 104
PM_SLP_SUS# SUSP#/GPIO0B ICH_PWROK/GPXO06 BKOFF#
<31> PM_SLP_SUS# 18
PBTN_OUT#/GPIO0C GPO BKOFF#/GPXO08
105 BKOFF# <27>
SUSWARN# 19 GPIO 106 ENBKL
<31> SUSWARN# INVT_PWM EC_PME#/GPIO0D WL_OFF#/GPXO09 ENBKL <32> BATT_TEMP
<27> INVT_PWM 25 107 1 2
FAN_SPEED1 EC_THERM#/GPIO11 GPXO10 SA_PGOOD C321 100P_0402_50V8J
<5> FAN_SPEED1 28 108 SA_PGOOD <54>
B FAN_SPEED1/FANFB1/GPIO14 GPXO11 B
29
E51_TXD FANFB2/GPIO15
<39> E51_TXD 30
E51_RXD EC_TX/GPIO16 ACIN_D ACIN_D
<39> E51_RXD 31 110 1 2
EAPD EC_RX/GPIO17 PM_SLP_S4#/GPXID1 EC_ON C322 100P_0402_50V8J
<42> EAPD 32 112 EC_ON <41,44,49>
ON_OFF/GPIO18 ENBKL/GPXID2 ON/OFFBTN#
34 114 ON/OFFBTN# <44>
NUM_LED# PWR_LED#/GPIO19 GPXID3 LID_SW#
<39> NUM_LED# 36
NUMLED#/GPIO1A GPI GPXID4
115 LID_SW# <39>
116 SUSP#
GPXID5 PBTN_OUT# SUSP# <9,46,50,52,54,57,58> PCH_PLT_RST# 2
117 PBTN_OUT# <5,29,31> 1
GPXID6 C325 0.1U_0402_16V4Z
118
GPXID7
122
XCLK1
<31> SUSCLK 1 2 CRY2 123
XCLK0 V18R
124 +EC_V18R
R389 0_0402_5%
AGND
+3V_EC
GND
GND
GND
GND
GND
C326
1
1 4.7U_0805_10V4Z
C1206 R390 KB930QF A1 LQFP 128P 1 2
11
24
35
94
113
69
20P_0402_50V8J 100K_0402_5% R392 330K_0402_5%
D14
2 ACIN_D 2 1
2
ACIN <31,48>
RB751V-40 SOD-323
+3V_EC
+3V_EC
R715
0_0805_5% 3VALW@
1 2 +3VALW
USB_EN# R391 1 2 10K_0402_5%
R714
A 0_0805_5% 3VL@ A
1 2 +3VL
EC Power : +3VALW(default)
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2010/12/03 Deciphered Date 2011/12/03 Title
ENE-KB930
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
0.3
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
PBL80 LA-7441P M/B
Date: Monday, April 11, 2011 Sheet 43 of 59
5 4 3 2 1
5 4 3 2 1
SPI Flash (1MByte*1) Power Button/ PWR/B
+3VALW
+3VALW +3VL
2
1 20mils @
C330 U9 R407 R408
8 4
0.1U_0402_16V4Z VCC VSS 100K_0402_5% 100K_0402_5%
2 D15
3
1
D W D
2 ON/OFFBTN# <43>
7 2 1 ON/OFFBTN#_R 1
HOLD R410 @ 10K_0603_5% 51_ON#
3 51_ON# <47>
<43> SPI_CS# 1
S Bottom Side ROW BAV70W 3P C/C SOT-323 PANJIT
<43> SPI_CLK 6
C
<43> EC_SO_SPI_SI 5 2 EC_SI_SPI_SO <43>
D Q
1
MX25L1005AMC-12G SOP 8P D
2 Q18
<41,43,49> EC_ON G 2N7002_SOT23-3
P/N :SA00002C100
2
@ C366 S
3
2 1 PWR_ON_LED# R411
10K_0402_5%
220P_0402_25V8J
1
For ESD Request
JPWR
6 G2
R1584 120_0402_5% 5 G1 PWR_ON_LED#
+5VALW 1 2 4 3
PWR_ON_LED# 4 3
<39,43> PWR_ON_LED# 3 3 1 1
ON/OFFBTN#_R 2 2 ON/OFFBTN#_R
2 2
1 1 D18
ACES_85201-0405N YSOT24C 3P C/A SOT23
@
C KEYBOARD CONN. C
For EMC
KSO10 1 2
KSO11
C334
1
100P_0402_50V8J
2
Screw Hole
C335 100P_0402_50V8J
KSO12 1 2
C336 100P_0402_50V8J H1 H2 H3 H4 H5 H6 H7 H8 H9 H10 H15 H21 H22
KSO15 1 2
C337 100P_0402_50V8J
KSI7 1 2 H_3P0 H_3P0 H_3P0 H_3P0 H_3P0 H_3P0 H_3P0 H_3P0 H_3P0 H_3P0 H_3P0N H_3P0X3P5N H_3P0X3P5N
1
C340 100P_0402_50V8J
KSI2 1 2
C341 100P_0402_50V8J @ @ @ @ @ @ @ @ @ @ @ @ @
KSI3 1 2
C338 100P_0402_50V8J
KSI4 1 2 JKB
C342 100P_0402_50V8J KSO7 1 +3VALW +5VALW +5VS
KSI0 1
C343
2
100P_0402_50V8J
KSO0
KSI1
2
3
1
2 CPU 1 1 1
KSI5 KSI7 3
1 2 4
4
C362 Close to H3 C407 Close to PC1201. C420 Close to JFUN.
C345 100P_0402_50V8J KSO9 5
KSI6 KSI6 5 H12 H11 H13 H14 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z
1 2 6
6
C346 100P_0402_50V8J KSI5 7 @ 2 2 2
KSI1 KSO3 7
1 2 8
C347 100P_0402_50V8J KSI4 8 H_4P7 H_4P2 H_4P2X4P7 H_4P2X4P7
9
1
KSO2 KSI2 9
1 2 10
C349 100P_0402_50V8J KSO1 10 +5VALW +5VALW
11
B KSO1 KSI3 11 @ @ @ @ +5VS B
1 2 12
12
C350 100P_0402_50V8J KSI0 13 1 1 Close to JUSB
KSO0 KSO13 13
1 2 14
14 1 C408 Close to JFUN.
C351 100P_0402_50V8J KSO5 15 C363 Close to H5 C307
KSO4 KSO2 15 0.1U_0402_16V4Z 1U_0603_10V6K
1 2 16
KSO3
C352
1
100P_0402_50V8J
2
KSO4
KSO8
17
18
16
17 VGA 0.1U_0402_16V4Z
2
2 2
C353 100P_0402_50V8J KSO6 18
19
KSO5 KSO11 19
1 2 20
C354 100P_0402_50V8J KSO10 20 H20 H19 H18 +5VS +5VALW
21
KSO14 KSO12 21
1 2 22
22
+1.5V Close to JUSB
C355 100P_0402_50V8J KSO14 23 1 1
KSO6 KSO15 23
1 2 24 H_2P9 H_2P9X3P9 H_2P9X3P9 1 C409 Close to PC603.
1
1
24
C356 100P_0402_50V8J C397 Close to H1 C324
KSO7 1 2 0.1U_0402_16V4Z 1U_0603_10V6K
C357 100P_0402_50V8J @ @ @ 0.1U_0402_16V4Z 2 2
KSO13 1 2 25 @ 2
C358 100P_0402_50V8J GND1
26
KSO8 GND2
1 2
C359 100P_0402_50V8J ACES_85201-24051
KSO9 1
C360
2
100P_0402_50V8J
@ WLAN
ESD
H17 H16
H_3P3 H_3P3
1
KSI[0..7]
KSI[0..7] <41,43> @ @
PCB Fedical Mark PAD ISPD
A KSO[0..15] FD1 FD2 FD3 FD4 ZZZ A
KSO[0..15] <43>
@ @ @ @ PCB
1
PCB LA-7441P REV01
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2010/12/03 Deciphered Date 2011/12/03 Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
ECROM/KB/PWR/B/SCREW
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
WWW.AliSaler.Com
0.3
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
PBL80 LA-7441P M/B
Date: Monday, April 11, 2011 Sheet 44 of 59
5 4 3 2 1
5 4 3 2 1
+5VALW 2.5A +USB_VCCB
UU3 W=80mils
+1.5V to +1.05V Transfer +5VALW 1 RU1
4.7K_0402_5%
2 USB30_POK
Close to U102.D7 Close to U102.P13 USB3@
1
2
GND VOUT 8
7 1
0.1U_0402_16V4Z
0_0402_5% VIN VOUT
USB3@ 3 VIN VOUT 6 1 1 1
+5VALW +1.5V +5VALW +1.5V +1.05V +3VA +3VA USB30PWRON 1 2 4 5 C368 + C369 C370
EN FLG 1
1U_0603_10V6K
10U_0603_6.3V6M
UU1 1A RU24 CU32
CU1
CU2
1 1 5 3 AP2301SG-13 4.7U_0805_10V4Z 4.7U_0805_10V4Z
VIN VOUT USB2@ @ 2 2 2 2
9 VIN VOUT 4
6 8P_0402_50V8D 8P_0402_50V8D 2 C367
USB30_POK VCNTL CU5 CU8 USB2@ 150U_B_6.3VM_R40M 1000P_0402_50V7K
7 POK FB 2 2 1
2 2 RU2 USB30_PS_EN
1 1 1 @ 1 1 1 @ <39,43> USB_EN# 1 2 UU3 USB2@
10U_0603_6.3V6M
8 1 10K_0402_1% 0.1U_0402_16V7K 0.1U_0402_16V7K RT9715AGS_SO8 1 2
+3V EN GND USB_OC2# <33>
CU9
USB3@ USB3@ CU3 CU6 RU26 USB3@ R446 0_0402_5%
USB3@ 1
APL5930KAI-TRG_SO8 USB3@ RU3 0_0402_5% 1 2 OCL1#
D USB3@ USB3@ 2 CU4 2 2 2 CU7 2 2 R447 0_0402_5% D
32.4K_0402_1%
Vout=0.8(1+10K/32.4K) 0.01U_0402_25V7K 0.01U_0402_25V7K USB3@
2
2 USB3@ USB3@ USB3@ USB3@
1.042 ~ 1.0469 ~ 1.0519V
Spec: 0.9975 ~ 1.05 ~ 1.1025
+3VALW to +3V Transfer +3VALW +3VS +3V
+3VALW Follow Vendor recommend.
1
RU22 RU23
2
2 USB3@ 47K_0402_5% 10K_0402_5%
1
RU4 USB3@ CU11 +3V +1.05V USB3@ USB3@
USB3@ 100K_0402_5% CU10 0.1U_0402_16V4Z @ JP3 +3VA
2
0.1U_0402_16V7K PAD-OPEN 2x2m 35mA
3
S
1 UU4 CU34 USB3@
1
G
1 USB3@ 2 2 QU1 SPI_CS_USB# 1 8 USB3@ 1 2 0.1U_0402_16V7K
RU6 47K_0402_5% 2 AO3413_SOT23 SPI_SO_USB CS# VCC
2 7 1 RU27 210K_0402_5%
2
CU12 USB3@ SO HOLD# SPI_CLK_USB
D 3 6 1 RU28 20_0402_5%
1
WP# SCK
1
D 0.01U_0402_25V7K USB3@ SPI_SI_USB
4 5
USB3@ GND SI
<41,43,46,51,58> SYSON 2
G 1 +3V MX25L5121EMC-20G SOP 8P
+3V
QU2 S 2N7002_SOT23-3 USB3@
3
D10
H11
E11
E12
K11
K12
P13
F13
F14
L10
L13
L14
G3
G4
N4
N5
N6
C4
C5
C6
C7
D5
C8
C9
D8
D9
H3
H4
D7
USB3@ UU2
P3
E3
E4
F3
L9
L5
L8
+3V & +1.05V has power sequence timing:
0.1*VDD(+3V) ~ 0.9*VDD(+1.05V) < 100ms SPI_CLK_USB 1 RU25 2
VDD33
VDD33
VDD33
VDD33
VDD33
VDD33
VDD33
VDD33
VDD33
VDD33
VDD33
VDD33
VDD33
VDD33
VDD10
VDD10
VDD10
VDD10
VDD10
VDD10
VDD10
VDD10
VDD10
VDD10
VDD10
VDD10
VDD10
VDD10
VDD10
VDD10
VDD10
VDD10
VDD10
VDD10
U3AVDO33
U2AVDD10
0_0402_5%
@ 2
<30> CLK_USB30 B2
PECLKP Close to UU4.6 CU33
<30> CLK_USB30# B1 0.1U_0402_16V7K
+3V +3VA USB3@ PECLKN 1
+3V:200mA U3TXDP2
B6 @
<30> PCIE_PRX_C_USB30TX_P4 CU15 2 1 0.1U_0402_16V7K PCIE_PRX_USBTX_P4 D2
PETXP
<30> PCIE_PRX_C_USB30TX_N4 CU13 2 1 0.1U_0402_16V7K PCIE_PRX_USBTX_N4 D1
PETXN +1.05V:800mA U3TXDN2
A6
USB3@ USB3@ N8
LU1 U2DM2
<30> PCIE_PTX_C_USB30RX_P4 F2
PERXP
1 2 <30> PCIE_PTX_C_USB30RX_N4 F1
PERXN U2DP2
P8
C BLM18AG601SN1D_2P C
B8
U3RXDP2
1
USB3@ A8
CU14 U3RXDN2
10U_0805_6.3V6K <33,40,43> PCH_PLT_RST# USB3@ H2 RU13
2 USB30_WAKE#
RU12 10_0402_5%2 PERSTB OCL2#
<31,40> EC_SWI# K1 G14 1 USB3@ 2 10K_0402_5% +3V
PEWAKEB OCI2B USB30_OCL1#
<30> CLKREQ_USB30# K2 H13 1 USB3@ 2 +3V
RU9 PECREQB OCI1B
+3V 1 USB3@ 2 10K_0402_5% RU30 10K_0402_5%
1 @ RU14
2 100_0402_1% J2 2 1 OCL1#
RU10 AUXDET
+3V 1 USB3@ 2 10K_0402_5% J1 PSEL PPON2
H14 USB3@
USB30_SMI_R H1 J14 USB30PWRON DU2 RB751V-40 SOD-323
USB30_SMI#_IC SMI PPON1
1 USB3@ 2 USB30_SMI#_R P4 U2D_DP1_R_L R413 2 @ 1 U2DP2_L
RU29 10K_0402_5% SMIB 0_0402_5%
+1.05V 1 USB3@ 2 P5 USB3@
+3V PONRSTB
RU15 10K_0402_5% B10 U3TX_C_DP1 CU16 2 1 0.1U_0402_16V4Z U3TXDP1 3 4
USB3@ USB3@ USB3@ USB3@ 1SS355TE-17_SOD323-2 U3TXDP1 3 4
1 1 2 2 SPI_CLK_USB M2 A10 U3TX_C_DN1 CU17 2 1 0.1U_0402_16V4Z U3TXDN1 KINGCORE WCM-2012-900T
SPISCK U3TXDN1
1U_0603_10V6K
USB3@ DU1 SPI_CS_USB# N2 N10 U2D_DN1_R USB3@ 2 1
SPISCB U2DM1 2 1
CU35 0.1U_0402_16V7K
CU18 0.01U_0402_25V7K
CU19 0.1U_0402_16V7K
CU20 0.01U_0402_25V7K
CU21 0.01U_0402_25V7K
CU36 0.1U_0402_16V7K
CU22 0.01U_0402_25V7K
CU23 0.01U_0402_25V7K
CU24 0.01U_0402_25V7K
CU37
SPI_SI_USB N1
1 2 1 2 2 1 2 2 2 1
SPI_SO_USB M1
SPISI
P10 U2D_DP1_R must to close to JUSB30 L18
SPISO U2DP1 U3RXDP1_R U2D_DN1_R_L R414 2 U2DN2_L
B12 1
USB3@ U3RXDP1 0_0402_5% @
2 1 2 1 1 2 1 1 1 2 K13 A12 U3RXDN1_R
GND U3RXDN1
K14
GND
J13
GND
U3RXDP1_R 1 @ 2 R415 U3RXDP1_R_L U3TXDP1 1 @ 2 R417 U3TXDP1_L
P12 RU18 1 USB3@ 2 1.6K_0402_1% 0_0402_5% 0_0402_5%
RREF WCM-2012-121T_0805 WCM-2012-121T_0805
N12
USB3@ USB3@ USB3@ USB3@ USB3@ U2AVSS
C14 4
3 3
4
GND 4 4 3 3
N11
U2PVSS USB3@ USB3@
+3V D6 1 2 1 2
U3AVSS 1 2 1 2
N14
USB3@ USB3@ USB3@ CLK_48M_USB XT1 L19 L20
M14
XT2 U3RXDN1_R U3RXDN1_R_L U3TXDN1 U3TXDN1_L
1 2 R416 1 2 R418
@ 0_0402_5% @ 0_0402_5%
1
CU38 0.01U_0402_25V7K
CU25 0.01U_0402_25V7K
CU26 0.01U_0402_25V7K
CU27 0.01U_0402_25V7K
CU28 0.1U_0402_16V7K
CU29 0.01U_0402_25V7K
2 2 2 2 1 2
RU19
100_0402_5%
P6
CSEL ：24MHz XTAL
CSEL=0：
B B
1 1 1 1 2 1 USB3@
USB3@
：48MHz Clock
CSEL=1： P14 U3TXDP1_L 9
JUSB2
2
YU1 GND SSTX+
A1 P11 +USB_VCCB 1
GND GND VBUS
2
0_0402_5%
1 2 A2 P9 U3TXDN1_L 8
GND GND U2DP2_L SSTX-
A3 P7 3
24MHZ_12PF_X5H024000DC1H GND GND D+
A4 P2 7
GND GND GND
12P_0402_50V8J
12P_0402_50V8J
USB3@ A5 P1 U2DN2_L 2 10 USB30_GND
GND GND D- GND
2
1 1 A7 N13 U3RXDP1_R_L 6 11 USB30_GND
RU201
GND GND SSRX+ GND
0_0402_5%
RU21
USB3@ USB3@ USB3@ A9 N9 4 12 USB30_GND
GND GND GND GND
CU31
CU39
USB3@ A11 N7 U3RXDN1_R_L 5 13 USB30_GND
GND GND SSRX- GND
A13 N3
GND GND
2
@ 2 2 A14 M13 ACON_TAR20-9V1393
1
GND GND @ R1512
B3 M12
GND GND 0_0603_5%
B4 M11
USB3@ GND GND
B5 M10
GND GND R881
B7 M9
1
GND GND U2D_DN1_R U2D_DN1_R_L
B9 M8 1 USB3@ 2 0_0402_5%
GND GND R883
B11 M7
GND GND U2D_DP1_R U2D_DP1_R_L
B13 M6 1 USB3@ 2 0_0402_5%
GND GND
B14 M5
GND GND
Place as close as possibile to C1
C2
GND
GND
GND
GND
M4
M3 <33> USB20_N4
R882
1 USB2@ 2 0_0402_5%
R884
UU2.N14 and UU2.M14 C3
C10
GND
GND
GND
GND
L12
L11 <33> USB20_P4 1 USB2@ 2 0_0402_5%
C11 L7
GND GND
L6
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
USB3@
C12
C13
D3
D4
D11
D12
D13
D14
E1
E2
E13
E14
F4
F6
F7
F8
F9
F11
F12
G1
G2
G6
G7
G8
G9
G11
G12
G13
H6
H7
H8
H9
H12
J3
J4
J6
J7
J8
J9
J11
J12
K3
K4
L1
L2
L3
L4
D23
U3RXDN1_R_L 1 1 109 U3RXDN1_R_L
U3RXDP1_R_L 2 2 98 U3RXDP1_R_L
D7
UPD720200AF1-DAP-A FBGA USB3.0
+3V U3TXDN1_L 4 4 77 U3TXDN1_L U2DN2_L 2
1
U3TXDP1_L 5 5 66 U3TXDP1_L U2DP2_L 3
A USB3@ A
10K_0402_5% 3 3
YSDA0502C 3P C/A SOT-23
+3V 2 RT43 1 2N7002_SOT23-3 UPD720200A:
2
G
QU4 SMIB Low active USB30_SMI#_IC For UPD720200: 8
SMI high active
USB30_SMI#_IC 3 1 L15ESDL5V0NA-4 SLP2510P8
USB30_SMI# <34>
1
D
S
USB3@
USB3@ QU3 2 1 @ 2 USB30_SMI_R
@ G RU16 0_0402_5%
1 @ 2 S 2N7002_SOT23-3
3
RU31 0_0402_5% 1 @ 2 USB30_SMI#_R
RU17 0_0402_5%
2010/09/17 Add Level shift to avoid +3V leakage from +3VALW_PCH
Security
Security Classification
Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2010/12/03 Deciphered Date 2011/12/03 Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
PCIe-USB3.0
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
0.3
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
PBL80 LA-7441P M/B
Date: Monday, April 11, 2011 Sheet 45 of 59
5 4 3 2 1
5 4 3 2 1
+5VALW
+3VALW TO +3VS +1.5V to +VRAM_1.5VS
2
Vgs=-0V,Id=9A,Rds=18.5mohm +1.5V R420
+VRAM_1.5VS 100K_0402_5%
+3VALW +3VS 0.1U_0402_16V7K
0.1U_0402_16V7K Vgs=10V,Id=16A,Rds=3.8 mohm
1
TPCA8059-H 1N PPAK56-8
1 1 2 2 Q20 1 1 VGA_PWROK#
Q19 C371 C372 4.7U_0805_10V4Z C373 C374 C375
470_0805_5%
470_0805_5%
8 1 1 C376
D S
2
7 2 2 4.7U_0805_10V4Z
D S
1
2 2 R421 1 1 2 2 R422 D
6 3 5 3
D D S Q21 D
5 4 <14,33,34,57> VGA_PWROK 2
D 1U_0402_6.3V4Z G 1U_0402_6.3V4Z G 2N7002_SOT23-3
4.7U_0805_10V4Z
AP4800BGM-HF 1N SO-8 1 R423 2 +VSB 1 1 R424 2 +VSB S
3 1
3 1
3
0.022U_0402_25V7K
4.7U_0805_10V4Z
2 1 1 47K_0402_5% 220K_0402_5%
6
C377 C380 C379
C378 R425 Q40A 1
1
2
0.1U_0402_25V6
330K_0402_5% Q40B Q36A Q36B
1 2 2 +3VALW
C381
2 SUSP 5 R426 2 VGA_PWROK# 5
2N7002DW-T/R7_SOT363-6 820K_0402_5%
2
2N7002DW-T/R7_SOT363-6 2 2N7002DW-T/R7_SOT363-6
4
2
1
0.1U_0402_16V7K
R1443
+5VALW TO +5VS 100K_0402_5%
+1.05VS_VCCP to +1.05VS_DGPU
2
+5VALW +5VS
<53> 0.75VR_EN#
3
Q207B
+1.05VS_VCCP +5VALW 2N7002DW-T/R7_SOT363-6
1 1
Q22 C382 C383
470_0805_5%
8 1 1U_0402_6.3V4Z 4.7U_0805_10V4Z +1.05VS_DGPU <52,54> VTTPWRGOOD 2 10.75VR_EN 5
D S
2
C385
C384
7 D S 2 2 2 Vgs=4.5V,Id=3A,Rds<22mohm
2 2 R428 R457 R1442
6 3
4
D S
2
5 4 47K_0402_5% 100K_0402_5%
D G
1
0.1U_0402_16V7K
0.1U_0402_16V7K
Q56 R460
6
1 1 D
C386
AP4800BGM-HF 1N SO-8 RUN_ON 1 R429 2 PJ33 470_0805_5% Q207A
1
+VSB
3 1
1
0.1U_0603_25V7K
4.7U_0805_10V4Z
2 1 1 47K_0402_5% JUMP_43X118 2 2N7002DW-T/R7_SOT363-6
1
@ G
1
2
C387 C388 R430 Q37A S 1 SUSP 2
0.1U_0402_25V6
0.1U_0402_16V7K
330K_0402_5% Q37B AO3416_SOT23-3
3
1 2 2 2 SUSP 5 C493
1
C 2N7002DW-T/R7_SOT363-6 Q209A C
2
2N7002DW-T/R7_SOT363-6 2 Q209B
1
2DGPU_PWR_EN# 5 +5VALW
+1.05VS_DGPU 2N7002DW-T/R7_SOT363-6 2N7002DW-T/R7_SOT363-6
+5VALW
2
100K_0402_5%
1 1
C685 C686
+1.5V to +1.5VS
2
4.7U_0603_6.3V6K 1U_0402_6.3V6K R434
Vgs=10V,Id=14.5A,Rds=6mohm @ R427
2 2
1
+1.5V +1.5VS DGPU_PWR_EN# <17> 100K_0402_5% <5,53> SUSP SUSP
1
SYSON#
SYSON# Q26
1 1
1
D
Q25
470_0805_5%
2N7002_SOT23-3
8 1 C393 C394 Q24 2
D S <9,43,50,52,54,57,58> SUSP#
2
1
1U_0402_6.3V4Z 4.7U_0805_10V4Z D G
7 2
D S 2 2
6 3 2 S
3
D S <41,43,45,51,58> SYSON
2
5 4 R435 G
D G
1
S R438
3
SI4856ADY_SO8 1 R436 2 +VSB R432 2N7002_SOT23-3 4.7K_0402_5%
3 1
4.7U_0805_10V4Z
1 220K_0402_5% 10K_0402_5%
1
6
0.1U_0603_25V7K
FDS6676AS 1
1
C395 R437 Q39A
2
C396 820K_0402_5% Q39B
2 2 SUSP 5
2 2N7002DW-T/R7_SOT363-6
2
2N7002DW-T/R7_SOT363-6
1
B B
+3VALW TO +3VALW(PCH AUX Power) +1.5V
+0.75VS +1.8VS
+1.05VS_VCCP
Short J1 for PCH VCCSUS3.3
1
+3VS_DGPU +VGA_CORE
1
R442 R443
R440 R441 22_0603_5% 22_0603_5%
2
+3VALW
+1.05VS_VCCP_R
+3VALW_PCH 470_0805_5% 470_0805_5%
2N7002_SOT23-3
2N7002_SOT23-3
2N7002_SOT23-3
2N7002_SOT23-3
JUMP_43X39 R458 R459
2
@ J1 470_0805_5% 470_0805_5%
40mil
+0.75VS_R
+0.75VS_R
2 2
1 1
+1.5V_R
3 1
1
1 1
10U_0603_6.3V6M
C390
C687
1
1U_0402_6.3V6K Q206B D Q55
1
2 2 2N7002DW-T/R7_SOT363-6 DGPU_PWR_EN# 2N7002_SOT23-3 D D D D
5 2
G SUSP 2 SYSON# 2 SUSP 2 SUSP 2
S G G G G
4
3
Q28 S Q29 S Q30 S Q38 S
3
A A
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2010/12/03 Deciphered Date 2011/12/03 Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
DC-DC INTERFACE
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
WWW.AliSaler.Com
0.3
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
PBL80 LA-7441P M/B
Date: Monday, April 11, 2011 Sheet 46 of 59
5 4 3 2 1
A B C D
PL1
DCIN jack P/N:DC301008L00, HCB2012KF-121T50_0805
PH1 under CPU botten side :
need doble confirm P/N with ME 1 2
VIN CPU thermal protection at 93 +-3 degree C
PL2
HCB2012KF-121T50_0805
Recovery at 56 +-3 degree C
ADPIN 1 2 VL
PJPDC1
1000P_0402_50V7K
1000P_0402_50V7K
<43,48> ADP_I
100P_0402_50V8J
100P_0402_50V8J
4 4
21.5K_0402_1%
3 3
1
PC1
PC2
PC3
PC4
1
2 2 1
PR1
1 PC5 PR26
2
1 0.1U_0603_16V7K 47.5K_0402_1%
2
@ SINGA_4TRJWT-R2513
X7R type
2
PU1
1 8 OTP_N_001
VCC TMSNS1
VL 2 7 OTP_N_002 2 1
GND RHYST1
2
ADP_OCP_3 PR2 10K_0402_1%
100K_0402_1%
<43,55> VR_HOT# 3 OT1 TMSNS2 6
PR23
1
ADP_OCP_2
need confirm: ME give us battery 4 OT2 RHYST2 5 1 2
OTP_N_003
2
connector P/N is DC040000800 G718TM1U_SOT23-8 PR24 422K_0402_1% PH1
1
1
D PR25 100K_0402_1%_NCP15WF104F03RC
PQ4 2 ADP_OCP_1 100K_0402_1%
2
SSM3K7002FU_SC70-3 G 2 1
S EN0 <49>
1
PR3 @0_0402_5%
PL3
@SUYIN_200275MR009G10PZR HCB2012KF-121T50_0805 2 1
1 2 VS_ON <49>
PR4 0_0402_5%
VMB If EC use 3VL and can not detect VGATE,
PL4 must connect EN0
1 HCB2012KF-121T50_0805
1
2 2 1 2 BATT+
3 3
4 B/I
4 EC_SMCA +VSBP
5 5 B+ 3 1
1
6 EC_SMDA
6
2
TS_A PC6 PC7
100K_0402_1%
0.1U_0603_25V7K
2 2
0.22U_0603_25V7K
7 7
1
11 GND 8 8 1000P_0402_50V7K 0.01U_0402_25V7K
1
PC8
PC9
PR10
10 GND 9 9
@PJSOT24CW_SOT323-3
PR27
1K_0402_1%
1
PJP2 PD1
1
2
2
2
PQ1
VL PR12 TP0610K-T1-E3_SOT23-3
22K_0402_1%
1 2 VSB_N_001
2
1VSB_N_003
PR13
100K_0402_1%
PR16
1
PD2 0_0402_5% D
2 <49> POK 1 2VSB_N_002 2 PQ2
1 G SSM3K7002FU_SC70-3
.1U_0402_16V7K
3 S
3
1
PC10
PR28
100_0402_1% @PJSOT24CW_SOT323-3
1 2
Reserve when EC use +3VL.
EC_SMB_CK1 <43,48>
2
Install when EC use +3VALW.
1 2 EC_SMB_DA1 <43,48>
PR31
100_0402_1%
PR29
1 2 +3VALW
+3VL PJ2
100K_0402_5%
PR30 +VSBP 2 1 +VSB
2 1
1 2
3
BATT_TEMP <43> PJ3 3.3V JUMP_43X39
3
1K_0402_1% 2 1
+CHGRTC 2 1
(120mA,40mils ,Via NO.= 1)
JUMP_43X39
VIN
@ Pre-charge
2
PD3
RLS4148_LL34-2
Pre_chg PQ7
VS_N_001
1
VIN PR6 LL4148_LL34-2 TP0610K-T1-E3_SOT23-3
1K_1206_5% PD5 B+
1 2 2 1 3 1
100K_0402_5%
@ @ @ 2 1
0.1U_0402_25V6
0.1U_0402_25V6
0.1U_0402_25V6
100K_0402_5%
PR7 BATT+
1
1
1K_1206_5% PD4
PR8
PR9
1
1 2 RLS4148_LL34-2 PQ3 PR17 PR18
PC80
PC81
PC128
TP0610K-T1-E3_SOT23-3 68_1206_5% 68_1206_5%
PR11
2
1K_1206_5%
2
2
1 2 N1 3 1 VS
2
PR14
1
1
1K_1206_5%
1
1 2 PR15 PC12
100K_0402_5% PR21 PC11 0.1U_0603_25V7K
100K_0402_1% 0.22U_0603_25V7K
2
12
2
1
4
0_0402_5% PQ6 1 2 VS_N_002 4
<44> 51_ON#
PR19 PD20 PDTC115EU_SOT323-3 PR22
<43> ACOFF 2 1 2 22K_0402_1%
1 2 2
+5VALW 3
BAS40CW_SOT323-3
PQ5 Security Classification Compal Secret Data Compal Electronics, Inc.
3
PDTC115EU_SOT323-3
Issued Date 2009/01/23 Deciphered Date 2011/12/03 Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
DCIN / BATT CONN / OTP
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
0.3
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS NCL61 LA-6321P M/B
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Monday, April 11, 2011 Sheet 47 of 59
A B C D
A B C D
for reverse input protection
PQ106 D
1
2
G SI1304BDL-T1-E3_SC70-3
S
3
PR103 PR104
1 2 1 2
1 1M_0402_5% 3M_0402_5% 1
VIN P1 P2 PR101 B+
P_AO4466L_SO8 P_AO4466L_SO8 0.015_2512_1% P_AO4466L_SO8
PQ101 PQ102 PL102 PQ103
8 1 1 8 1 2 1 4 8 1
0.1U_0402_25V6
7 2 2 7 7 2
10U_0805_25V6K
10U_0805_25V6K
@0.1U_0402_25V6
10U_0805_25V6K
10U_0805_25V6K
6 3 @ 3 6 1UH_10.3A_20% 2 3 6 3
2200P_0402_50V7K
0.1U_0402_25V6
1
10U_0805_25V6K
10U_0805_25V6K
0_0402_5%
5 5 5 @
0.01U_0402_50V7K
PC111
PC104
PC101
1
1
PC130
PC105
PC103
0_0402_5%
PR105
PC102
1
1
VIN
PC129
PC110
PR106
4
PC114
2
1
PC112
2
1
2
0.1U_0402_25V6
PD101
2
BQ24725_ACDRV_1 BAS40CW_SOT323-3
1
BQ24725_BATDRV 1 2 BQ24725_BATDRV_1
PC115
0.047U_0402_25V7K PR107
1 1
4.12K_0603_1%
4.12K_0603_1%
10_1206_1%
1 2 4.12K_0603_1%
PC116
PR110
1
PC113 1 2
PR108
PR109
0.1U_0402_25V6
5
0_0603_5%
PR111
PQ104
0.1U_0603_25V7K
BQ24725_VCC2
1
MDV1660URH
2
2 PD102 2
1
RB751V-40_SOD323-2
PC117
BQ24725_BST 2
BQ24725_ACP
2DH_CHG1
BQ24725_REGN
1 4
PC118 PR125
BQ24725_LX
2
2
1 2 DH_CHG BATT+
0_0402_5%
DH_CHG
PL101
1U_0603_25V6K PC119 10UH_PCMB104T-100MS_6A_20% PR102
3
2
1
0.01_1206_1%
BQ24725_ACN
1 2
BQ24725_LX 1 2 CHG 1 4
1U_0603_25V6K
5
6
7
8
4.7_1206_5%
20
19
18
17
16
2 3
CSOP1
PU101
2200P_0402_50V7K
0.01U_0402_50V7K
CSON1
1
PQ105
VCC
REGN
PHASE
HIDRV
BTST
PR114
10U_0805_25V6K
10U_0805_25V6K
21 AO4468L_SO8
0.1U_0402_25V6
0.1U_0402_25V6
PAD
PC108
PC109
PC106
PC107
1
1
1 15 DL_CHG 4 @
ACN LODRV
PC121
PC122
2
2
2 14
680P_0402_50V7K
ACP GND PR115
3
2
1
2
1
BQ24725RGRR_VQFN20_3P5X3P5 P_R
PC123
BQ24725_CMSRC 3 <BOM Structure> 13 SRP1 2 CSOP1
CMSRC SRP
1
PR116
2
P_R
BQ24725_ACDRV 4 12 SRN 1 2 CSON1 @
2
ACDRV SRN
0.1U_0603_16V7K
PR117
PC124
+3VALW 1 2BQ24725_ACOK 5 ACOK BATDRV 11 BQ24725_BATDRV
ACDET
10K_0402_1% Remember to change PC124 from SE000006S80
IOUT
3 3
SDA
SCL
ILIM
to SE025104K80 (2011-02-22)
PR118 Pre_chg +3VALW
6
10
1 2
<31,43> ACIN PR119
1
10K_0402_1% BQ24725_ILIM 1 2
0.01U_0402_25V7K
PD7
100K_0402_1%
PR120 P_RB751V-40_SOD323-2 316K_0402_1%
1
VIN
PC125
PR121
1
2
BQ24725_ACDET
1 2
2
154K_0402_1%
255K_0402_1%
1
PR122
Vin Dectector
Min. Typ Max.
2
H-->L 17.23V
0.1U_0402_25V6
66.5K_0402_1%
L--> H 17.63V EC_SMB_CK1 <43,47>
1
PC126
PR123
ILIM and external DPM
2
EC_SMB_DA1 <43,47>
3.97A PC127
PR124
@100P_0402_50V8J
2
4 2 1 1 2 ADP_I <43,47> Please locate the RC 4
1
Near EC chip
PC131
100P_0402_50V8J 0_0402_5% 2011-02-22
2
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2010/01/25 Deciphered Date 2011/12/03 Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
PWR DCIN / Pre-charge
Size Document Number Rev
WWW.AliSaler.Com
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom 0.3
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
LA-7221P
Date: Monday, April 11, 2011 Sheet 48 of 59
A B C D
A B C D E
2VREF_8205
1
1 1
PC308
1U_0603_16V6K
2
PR301 PR305
13.7K_0402_1% 30.9K_0402_1%
1 2 1 2
PR302 PR306
B+ B++
20K_0402_1% 20K_0402_1%
B++
PL301 1 2 FB_3V FB_5V 1 2
HCB2012KF-121T50_0805
1 2 +3VLP
ENTRIP2
ENTRIP1
PR303 PR307
2200P_0402_50V7K
2200P_0402_50V7K
10U_0805_25V6K
0.1U_0402_25V6
0.1U_0402_25V6
137K_0402_1% 137K_0402_1%
1
1
4.7U_0805_25V6-K
1 2 1 2
1
1
PC309
PC310
PC311
PC312
PC304
PC306
PQ303
2
2
6
1
MDV1660URH PU301
2
5
ENTRIP2
FB2
TONSEL
FB1
ENTRIP1
REF
1
PC313 PQ305
4 10U_0805_6.3V6M 25 MDV1660URH
P PAD
2
7 VO2 VO1 24 4
2 2
1
2
3
PC314 8 23 PR309 PC315
0.1U_0402_10V7K PR308 VREG3 PGOOD 2.2_0402_5% 0.1U_0402_10V7K
1 2 BST1_3V 1 2 BST_3V 9 22 BST_5V 1 2 BST1_5V 1 2
3
2
1
0_0402_5% BOOT2 BOOT1
PL303 UG_3V 10 21 UG_5V PL305
4.7UH_VMPI0703AR-4R7M-Z01_5.5A_20% UGATE2 UGATE1 4.7UH_VMPI0703AR-4R7M-Z01_5.5A_20%
2 1 LX_3V 11 20 LX_5V 1 2 +5VALWP
+3VALWP PHASE2 PHASE1
1
8
7
6
5
5
6
7
8
1
@4.7_1206_5%
@4.7_1206_5%
LG_3V 12 19 LG_5V
LGATE2 LGATE1
PR312
PQ304
SKIPSEL
VREG5
1
PR313
PR314 1
GND
VIN
+
NC
PC303 499K_0402_1%
EN
2
2
4 1 2 4 + PC305
B++ POK <47>
220U_6.3VM_R15 220U_6.3VM_R15
SNUB_3V
SNUB_5V
13
14
15
16
17
18
2 PQ306
S IC RT8205EGQW WQFN 24P PWM FDS6690AS_G 1N SO8 2
<47> EN0
@680P_0402_50V7K
AO4468L_SO8
1
2
3
3
2
1
@680P_0402_50V7K
VL
1
1
PC316
PC317
PR315
95.3K_0402_1% PC320
2
1U_0603_10V6K
2
1
PC318
4.7U_0805_10V6K
2
1
B++
PC319
2
3 0.1U_0603_25V7K 3
2VREF_8205
ENTRIP1
ENTRIP2
PJP306
6
PQ307A D D PQ307B 1 2
SSM6N7002FU_US6 2 N_3_5V_001 5 SSM6N7002FU_US6
G G PAD-OPEN 4x4m +3VLP +3VL
PJP302
S S PJP305 2 1
1
+5VALWP 1 2 +5VALW (ipeak=10A imax=7A,400mils ,Via NO.= 20)
PAD-OPEN 2x2m
PAD-OPEN 4x4m
1 2 VL
PR318 PJP303
@10K_0402_1% PR317
+3VALWP
1 2 +3VALW (ipeak=6A imax=4.2A,240mils ,Via NO.= 12) VL +5VL
1 2 100K_0402_5%
<41,43,44> EC_ON
1
PJP301
PAD-OPEN 4x4m
2 1
PQ308
<47> VS_ON DTC115EUA_SC70-3 PAD-OPEN 2x2m
1 2 2
VS
402K_0402_1%
4.7U_0805_25V6-K
PR319
1
316K_0402_1%
1
PR320
PC321
PD301 PR322
2
2 1 1 2
VIN
2
4 4
P_LL4148_LL34-2 P_R
EC:+3VL, reserve PR319, install PR318, PR320 100K
EC:+3VALW, reserve PR318, install PR319, PR320 40.2K Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2007/08/02 Deciphered Date 2011/12/03 Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
3.3VALWP/5VALWP
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
Custom PBL21 LA6771P M/B 0.3
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Monday, April 11, 2011 Sheet 49 of 59
A B C D E
A B C D
1 1
PL402
PU401 PL401 <Vo=1.8V> VFB=0.6V
4
+5VALW HCB1608KF-121T30_0603 1UH_VMPI0703AR-1R0M-Z01_11A_20%
1 2 1.8VSP_VIN 10 2 1.8VSP_LX 1 2
Vo=VFB*(1+PR401/PR402)=0.6*(1+20K/10K)=1.8V
PG
PVIN LX +1.8VSP
68P_0402_50V8J
9 PVIN LX 3
1
4.7_1206_5%
1
1
PC404
PC403 8 SVIN
PR403
22U_0805_6.3VAM PR401
6 1.8VSP_FB 20K_0402_1%
2
2
FB
22U_0805_6.3VAM
22U_0805_6.3VAM
5
2
EN
1
NC
NC
TP
PC401
PC402
<9,43,46,52,54,57,58> SUSP#
11
2
SNUB_1.8VSP
2
1 2 EN_1.8VSP 2
1
1
PR404 0_0402_5%
@0.1U_0402_10V7K
PC405
SY8033BDBC_DFN10_3X3 PR402
1
PR405 10K_0402_1%
@47K_0402_5%
2
2
680P_0402_50V7K
PC406
2
PJP401
+1.8VSP 1 2 +1.8VS (2A, 80mils, Via NO.= 4)
PAD-OPEN 3x3m
3 3
4 4
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2009/01/23 Deciphered Date 2011/12/03 Title
+1.8VSP
WWW.AliSaler.Com
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS NCL61 LA-6321P M/B 0.3
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Monday, April 11, 2011 Sheet 50 of 59
A B C D
5 4 3 2 1
D D
1.5V_B+
PR503 PL502 B+
2 1 EN_1.5V HCB1608KF-121T30_0603
<41,43,45,46,58> SYSON 2 1
0_0402_5% PC505
1
@0.1U_0402_10V7K
10U_0805_25V6K
2200P_0402_50V7K
4.7U_0805_25V6-K
0.1U_0402_25V6
2
5
6
7
8
PC507
PQ501
PC503
PC504
PC506
PR504
2
2.2_0402_5% MDS1660URH
BST_1.5V 1 2BST1_1.5V 1 2
4
PC508
0.1U_0402_10V7K
15
14
1
PU501
PR506
EN/DEM
NC
BOOT
3
2
1
255K_0402_1% +1.5VP
1 2TON_1.5V 2 TON UGATE 13 UG_1.5V 0.68UH_PCMC063T-R68MN_15.5A_20%
C PL501 C
+1.5VP 3 12 LX_1.5V 1 2
VOUT PHASE
+5VALW 1 V5FILT_1.5V TRIP_1.5V 1 PR508 15K_0402_1%
+5VALW 2 4 VDD CS 11 2
PR507 PR501
5
6
7
8
1
+1.5VP 1 2 FB_1.5V 5 10 +5VALW +5VALW 1
100_0402_1% FB VDDP PQ502 PR509
220U_6.3VM_R15
1
1
2.21K_0402_1% LG_1.5V MDS2655URH 1N SO-8 4.7_1206_5% +
PC501
6 PGOOD LGATE 9
PGND
PC509 PC510
GND
1
4.7U_0603_10V6K 4.7U_0805_10V6K
2
2
PR502 2
4
2.15K_0402_1% RT8209BGQW_WQFN14_3P5X3P5
1SNUB_1.5V
7
8
2
3
2
1
PC511
680P_0402_50V7K
2
B B
PJP503
1 2
PAD-OPEN 4x4m
PJP502
1 2
PAD-OPEN 4x4m
PJP501
+1.5VP 1 2 +1.5V (Ipeak = 30A Imax= 21A , 1200mils ,Via NO.= 6
PAD-OPEN 4x4m
A A
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2007/05/29 Deciphered Date 2011/12/03 Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
+1.5VP
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS PBL21 LA6771P M/B 0.3
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Monday, April 11, 2011 Sheet 51 of 59
5 4 3 2 1
5 4 3 2 1
D D
VCCP_B+
PR703 PL702 B+
2 1 EN_VCCP HCB1608KF-121T30_0603
<9,43,46,50,54,57,58> SUSP# 2 1
0_0402_5% PC705
1
@0.1U_0402_10V7K
10U_0805_25V6K
2200P_0402_50V7K
4.7U_0805_25V6-K
0.1U_0402_25V6
2
5
6
7
8
PC707
PQ701
PC702
PC704
PC706
PR704
2
2.2_0402_5%
BST_VCCP 1 2BST1_VCCP 1 2
4
PC708
0.1U_0402_10V7K
15
14
1
PU701
PR705 MDS1660URH 1N SO8
EN/DEM
NC
BOOT
3
2
1
255K_0402_1% +1.05VS_VCCP
1 2TON_VCCP 2 TON UGATE 13 UG_VCCP PL701
0.68UH_PCMC063T-R68MN_15.5A_20%
+1.05VS_VCCP 3 12 LX_VCCP 1 2 (18A,340mils ,Via NO.= 17)
VOUT PHASE
+5VALW +5VALW 1 2 V5FILT_VCCP 4 11 TRIP_VCCP1 PR708 2
15K_0402_1%
C VDD CS C
PR707 PR701
5
6
7
8
1
1 2 FB_VCCP 5 10 +5VALW +5VALW 1
100_0402_1% FB VDDP PQ702 PR709
220U_6.3VM_R15
1
1
4.12K_0402_1% LG_VCCP MDS2655URH 1N SO-8 4.7_1206_5% +
PC701
6 PGOOD LGATE 9
PGND
PC709 PC710
GND
1
4.7U_0603_10V6K 4.7U_0805_10V6K
2
1SNUB_VCCP 2
PR702 2
4
FB_VCCP1
10.2K_0402_1% RT8209BGQW_WQFN14_3P5X3P5
8
2
3
2
1
PC711
680P_0402_50V7K
2
PR710
+3VS 1 2
VTTPWRGOOD <46,54>
2
10K_0402_5%
PR711
0_0402_5% PR712
10_0402_5%
1
B +1.05VS_VCCP B
VCCIO_SENSE <8>
VSSIO_SENSE connect to GND directly.
A A
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2009/12/01 Deciphered Date 2011/12/03 Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
PWR+1.05VSP/+VCCPP
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
WWW.AliSaler.Com
Custom 0.3
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
PBL21 LA6771P M/B
Date: Monday, April 11, 2011 Sheet 52 of 59
5 4 3 2 1
5 4 3 2 1
+1.5V
D PU601 D
1 VIN NC 8 +3VALW
2 GND NC 7
1
PC601 3 6
VREF VCNTL
1
4.7U_0805_6.3V6K
2
PR601 PC603
4 VOUT NC 5
PR605 1K_0402_1% 1U_0603_10V6K
2
2 1 9
2
<46> 0.75VR_EN# TP
APL5336KAI-TRL_SOP8P8
@0_0402_5% VREF_G2992
+0.75VSP
0.1U_0402_16V7K
1
PQ602
SSM3K7002FU_SC70-3
1
PR604 D
PR602
1
2 1 0.75VS_N_002 2 1K_0402_1%
<5,46> SUSP G PC605
2
10U_0805_6.3V6M
PC604
S
2
0_0402_5%
1
PC606
2
@0.1U_0402_10V7K
PJP601
C C
+0.75VSP 1 2 +0.75VS (2A,80mils ,Via NO.= 4)
PAD-OPEN 3x3m
B B
A A
Security Classification
Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2006/11/23 Deciphered Date 2011/12/03 Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
0.75VSP/1.2VSP
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS PBL21 LA6771P M/B 0.3
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Monday, April 11, 2011 Sheet 53 of 59
5 4 3 2 1
5 4 3 2 1
10K_0402_5%
<43> SA_PGOOD 2 1 +3VS
PR804
D D
PL802
PL801
4
+5VALW HCB1608KF-121T30_0603 PU801 1UH_VMPI0703AR-1R0M-Z01_11A_20%
1 2 VCCSA_B+ 10 PVIN 2 LX_VCCSA 1 2
PG
LX +VCCSAP
9 PVIN LX 3
1
PC803
4.7_1206_5%
8 SVIN
22U_0805_6.3VAM
FB_VCCSA
PR805
6
2
FB
5
22U_0805_6.3VAM
22U_0805_6.3VAM
EN
1
SS
TP
LX
2
SY8035DBC_DFN10_3X3
PC801
PC802
11
2
1 2 EN_VCCSA
<9,43,46,50,52,57,58> SUSP#
SNUB_VCCSA
1
PR806 0_0402_5%
@0.1U_0402_10V7K
PC804
@0.1U_0402_10V7K
PR801
1
PR807
PC808
1
1 2 @47K_0402_5% 2 1
<46,52> VTTPWRGOOD
2
PR815 @0_0402_5% 4.99K_0402_1%
680P_0402_50V7K
PC805
PC806
1
2 1
2
C PR802 C
FB_VCCSA_A
15K_0402_1% 68P_0402_50V8J
2
PR808 PR809
0_0402_5% 10_0402_5%
+3VS
1
2
PR810 +VCCSAP
10K_0402_5%
PR811 VCCSA_SENSE <9>
1
PQ802 VCCSA_SEL0 2 1 VCCSA_SEL1 PQ801
PMBT2222A_SOT23-3 10K_0402_5% SSM3K7002FU_SC70-3
PC807
CAP NP
2
G
@100K_0402_5%
VCCSA_SEL <9> 1
PR803
PR813
1
PR812 3 1FB_VCCSA2 1 2 FB_VCCSA
1VCCSA_SEL_0
D
2 2
2 29.4K_0402_1%
0_0402_5%
3
B B
2
1
PR814
@10K_0402_5%
2
PJP801
VCCSA_SEL VCCSA Vout +VCCSAP 1 2 +VCCSA(6A,240mils ,Via NO.= 12)
0 0.9V PAD-OPEN 4x4m
1 0.8V
A A
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2009/12/01 Deciphered Date 2011/12/03 Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
PWR+VCCSAP
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
WWW.AliSaler.Com
Custom 0.3
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
PBL21 LA6771P M/B
Date: Monday, April 11, 2011 Sheet 54 of 59
5 4 3 2 1
A B C D E F G H
2 PR202 1 CSP1
CSSUM P_R
PR203 P_R PR204 165K_0402_1%
CSCOMP 2 1 2 1 2 PR205 1 CSP2
P_R
PC216 PC217 220K_0402_5%_ERTJ0EV224J 2 1 1 2 2 PR206 1 CSP3
PR207 100P_0402_50V8J 3300P_0402_50V7K PH201 PC215 P_CAP NP P_R
1 2 1 2 1 2 1 2 2 1
24.9_0402_1% 6.04K_0402_1% PR209 34.8K_0402_1% 1 2
PR208
2
1 1
PC218 1200P_0402_50V7K
1K_0402_1%
4.7K_0402_1%
PR210
1 2 PC219
1
22P_0402_50V8J PR212 820P_0402_50V7K
2 1 1 2 2 1 CSN1
2 1
2 PR213 1 10_0402_1% PR214 10_0402_1%
1K_0402_1% 4700P_0402_25V7K PC220 2 1 CSN2
1 PR215 2 PR216 10_0402_1%
PR211
1 2
2
412_0402_1% PC221 2 PR217 1 2 1 CSN3
1
1 2 1 2 8.2K_0402_1% PR218 10_0402_1%
1
P_R 2K_0402_1% PC222
PR219 PC223 PR220 820P_0402_50V7K
4700P_0402_25V7K PC224
2
0.1U_0402_25V6K
1 2
DIFFOUT
1 2
PR221 24.3K_0402_1%
2
PC225
1000P_0402_50V8-J
CSREF 1
CSCOMP
DIFFOUT
CSSUM
0_0402_5%
53
52
51
50
49
48
47
46
45
44
43
42
41
40
PR223 PU201
1 2 CSN2 CSN2 <56>
GND
VSN
NC
NC
DIFFOUT
TRBST
IOUT
CSREF
FB
COMP
DROOP
CSCOMP
ILIM
CSSUM
<8> VSSSENSE
1
0.047U_0402_16V7K
PR224 0_0402_5% PC226 39 PC227
1000P_0402_50V8-J CSN2 CSP2 <56>
1 2 1 1 2 CSP2
2
2
<8> VCCSENSE VSP
38 PR225 6.98K_0402_1%
TSENSE CSP2 CSN3 CSN3 <56>
<43,47> VR_HOT# 2
1
TSENSE
+1.05VS_VCCP For VR_SVID_DAT and CLK PR227 130_0402_1%
CSN3
37 0.047U_0402_16V7K
1 2 3 PC228
PR229 110_0402_1% VRHOT# CSP3 CSP3 <56>
2 +1.05VS_VCCP 36 1 2 2
2
CSP3 PR228 6.98K_0402_1%
1 2 4
SDIO
1
PR230 54.9_0402_1% 35 CSN1 CSN1 <56>
+1.05VS_VCCP
1
TSENSE PC259 PC260 <8> VR_SVID_DAT CSN1 PC229
1 2 5
100K_0402_1%_NCP15WF104F03RC
1U_0402_16V6K
1U_0402_16V6K SCLK 0.047U_0402_16V7K
34
2
<8> VR_SVID_CLK CSP1
2
6 1 2 CSP1 CSP1 <56>
8.25K_0402_1%
0.1U_0402_25V6
2
1
<8> VR_SVID_ALRT# ALERT# PR233 6.98K_0402_1%
PR231
PC230
33
NCP6131S52MNR2G_QFN52_6X6 DRON DRVON <56>
PH203
1 2 7
PR234 10K_0402_1% VR_RDY
+3VS <5,31,43> VGATE 32
2
PWM1/ADDR PWM1 <56>
8
1
VR_RDYA
31
PWM3/VBOOT PWM3 <56>
1 2 9
<43> VR_ON PR201 0_0402_5% ENABLE
30
PWM2 PWM2 <56>
10
VCC IMAX
+5VALW 29
IMAX
1 2 1 2 11
PR236 9.09K_0402_1% ROSC
28
PR235 2.2_0603_5% PWMA/IMAXA PWMA <56>
1 2 12
VRMP
CSCOMPA
DIFFOUTA
TSENSEA 27 2 1
DROOPA
+5VALW
CSSUMA
VBOOTA
TRBSTA
TSENSEA
COMPA
PC231 1U_0603_6.3V6M 13
IOUTA
TSENSEA
CSNA
VSNA
CSPA
VSPA
ILIMA
1 2 @0_0402_5% PR237 PWM3 PWMA
100K_0402_1%_NCP15WF104F03RC
CPU_B+
FBA
2
PR238 1K_0402_1% 1 2 1 2
8.25K_0402_1%
0.1U_0402_25V6
1
PR241 PR240
PR239
PC233
14
15
16
DIFFOUTA 17
18
19
20
21
CSCOMOA 22
23
CSSUMA 24
25
26
PC232 0.01U_0402_50V7K @0_0402_5% 10K_0402_1% VCORE
PH204
1
1 2
10K_0402_1%
VBOOT
2
PC234 V_GT PR244
PR243
FBA
1
1000P_0402_50V8-J SET AT IMAX SET 26.1K_0402_1%
0.047U_0402_16V7K
1 2 PR246 0V
0_0402_5% AT 33A
2
1 2 CSNA <56>
1
PR247
2200P_0402_50V7K
1
1
0_0402_5% @0_0402_5%
PC235
1 2 PR248 PR249
<9> VSS_AXG_SENSE
1
2K_0402_1%
2
1
@0_0402_5% PC236 1 2 CSPA CSPA <56>
2
1
PR251 1000P_0402_50V8-J PR256 PR255 6.98K_0402_1%
PC237
@0_0402_5%
10P_0402_50V8J
2
24K_0402_1%
10P_0402_50V8J
2
3 3
1 2 2 1 PWM1 IMAX
<9> VCC_AXG_SENSE
2
2 2
PR252 PR258 PC239
412_0402_1% 4700P_0402_25V7K 2
1
0_0402_5% PC240
1 2 2 1
4.02K_0402_1%
.1U_0402_16V7K
PC238
2
1
PR259 2 VCORE
PR254
PR260
1
20K_0402_1%
PR263 1.82K_0402_1%
1
PWM IMAX SET PR265
1
8.06K_0402_1% PC243 PR264 73.2K_0402_1%
1K_0402_1% PC241
ADDRESS
2
PR266 3300P_0402_50V7K PR267 10K_0402_1% AT 94A
22
1
2 1 1 2 2 1CSNA
PR2611
2
PC242 FBA 10_0402_1% 10_0402_1%
PR262
4700P_0402_25V7K
2
PR268
PC244
P_CAP NP
1
2
2 1
1
6.19K_0402_1%
PR269 1K_0402_1%
1
2
2
CSCOMOA
1
PR271 PR273
75K_0402_1% PR272 51.1K_0603_1%
PR270
47_0402_1%
2 1 2 1 CSSUMA 2 1CSPA
1
165K_0402_1%
2 1
1 2 (CPU Ipeak=94A, Imax(TDP)=56A )
DIFFOUTA
220K_0402_5%_ERTJ0EV224J PC245
PH202 470P_0402_50V7K (CFX Ipeak=33A, Imax(TDP)=21.5 A)
1 2
PC246
1200P_0402_50V7K
PR275
1 2
@0_0402_5%
4 4
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2010/01/25 Deciphered Date 2011/12/03 Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
CPU_CORE_1
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
C 0.3
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
PCA60/70 LA-7001P M/B
Date: Monday, April 11, 2011 Sheet 55 of 59
A B C D E F G H
5 4 3 2 1
CPU_B+
CPU_B+
10U_0805_25V6K
10U_0805_25V6K
1U_0603_25V6K
PC247
1
PC204
PC205
10U_0805_25V6K
10U_0805_25V6K
D D
PC203
PQ201
1U_0603_25V6K
1 2 PC248
1
PC207
PC208
2
PC206
CSD17308Q3_SON8-5 1 2 PQ203
PR276 0.22U_0603_25V7K
2
4.7_0603_5% PU202 4 CSD17308Q3_SON8-5
PR296 PR277 0.22U_0603_25V7K
1 2 1 BST FLAG 9
2.2_0603_1% 4.7_0603_5% PU203 4
2 8 DH_CPU1
1 2 PL201 <55> PWM2 1 2 1 9 PR297
PWM1 PWM DRVH 0.36UH_PCMC104T-R36MN1R15_30A_20% BST FLAG 2.2_0603_1%
3
2
1
2 PR278 PWM1_EN
1 2K_0402_1% 3 7 LX_CPU1 1 4 2 8 DH_CPU2
1 2 PL202
EN SW +CPU_CORE PWM DRVH
1
+5VALW 0.36UH_PCMC104T-R36MN1R15_30A_20%
3
2
1
2 1 1 2 4 6 PR280 2 3 <55> DRVON 2 PWM2_EN
PR281 1 2K_0402_1% 3 7 LX_CPU2 1 4
VCC GND EN SW +CPU_CORE
1
4.7_1206_5%
PR279 0_0402_5% 5 DL_CPU1 2 1 1 2 4 6 PR283 2 3
DRVL VCC GND
5
2.2_0603_1% PR292 PQ202 +5VALW 4.7_1206_5%
2
NCP5911MNTBG_DFN8-9 TPCA8057-H_PPAK56-8-5 PR282 0_0402_5% 5 DL_CPU2
DRVL
1
2.2_0603_1% PR293 PQ204
2
1
DRVON <55> PC249 4 PC251 NCP5911MNTBG_DFN8-9 TPCA8057-H_PPAK56-8-5
1
1U_0603_25V6K 680P_0402_50V7K
2
1
PC250 4 PC252
2
<55> CSP1 1U_0603_25V6K 680P_0402_50V7K
2
3
2
1
2
<55> CSP2
<55> CSN1
3
2
1
<55> CSN2
C CPU_B+ C
10U_0805_25V6K
10U_0805_25V6K
1U_0603_25V6K
PC253
1
PC210
PC211
5
PC209
1 2
PQ205
2
PR284 0.22U_0603_25V7K CSD17308Q3_SON8-5
4.7_0603_5% PU204
1 2 1 9 PR298 4
55> PWM3 BST FLAG 2.2_0603_1%
2 8 DH_CPU3
1 2 PL203
PR285 PWM DRVH 0.36UH_PCMC104T-R36MN1R15_30A_20%
2 PWM3_EN
1 2K_0402_1% 3 7 LX_CPU3 1 4 +CPU_CORE
3
2
1
EN SW
1
+5VALW PR287
2 1 1 2 4 VCC GND 6 2 3
5
4.7_1206_5%
PR286 0_0402_5% 5 DL_CPU3
2.2_0603_1% PR294 DRVL PQ206
2
NCP5911MNTBG_DFN8-9 TPCA8057-H_PPAK56-8-5
1
DRVON <55> PC255 4 PC254
1U_0603_25V6K 680P_0402_50V7K
2
<55> CSP3
3
2
1
<55> CSN3
B B
CPU_B+
10U_0805_25V6K
10U_0805_25V6K
1U_0603_25V6K
PC256
5
1
PC213
PC214
PC212
1 2 PQ207
2
CSD17308Q3_SON8-5 PL205
PR288 0.22U_0603_25V7K HCB2012KF-121T50_0805
4.7_0603_5% PU205 4 2 1
1 2 1 9 PR299 B+
55> PWMA BST FLAG 2.2_0603_1% PL206
2 8 DH_GFX
1 2 PL204 HCB2012KF-121T50_0805
PR289 PWM DRVH 0.36UH_PCMC104T-R36MN1R15_30A_20% 2 1 CPU_B+
3
2
1
2 PWMA_EN
1 2K_0402_1% 3 7 LX_GFX 1 4 1 1
EN SW +GFX_CORE
1
+5VALW PR291 + +
2 1 1 2 4 VCC GND 6 2 3
5
4.7_1206_5% PC201 PC202
PR290 0_0402_5% 5 DL_GFX 100U_25V_M P_CAP WP
2.2_0603_1% PR295 DRVL PQ208 2 2
2
1
A NCP5911MNTBG_DFN8-9 TPCA8057-H_PPAK56-8-5 A
PC257
1
DRVON <55> 1U_0603_25V6K 4 PC258
2
680P_0402_50V7K
2
<55> CSPA
3
2
1
<55> CSNA Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2010/01/25 Deciphered Date 2011/12/03 Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
CPU_CORE_2
WWW.AliSaler.Com AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 0.3
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Monday, April 11, 2011 Sheet 56 of 59
5 4 3 2 1
A B C D
PL902
HCB2012KF-121T50_0805
B+ 1 2 VGA_B+
2200P_0402_50V7K
10U_0805_25V6K
10U_0805_25V6K
0.1U_0402_25V6
1
1
PC903
PC904
PC902
PC905
2
2
1 1
+3VALW
5
PQ901 PQ904
@CSD17308Q3_SON8-5
CSD17308Q3_SON8-5
PR906
10K_0402_5% 4 4
1
<14,33,34,46> VGA_PWROK
PR907 PC906
PU901 4.7_0603_5% 0.1U_0603_16V7K
3
2
1
3
2
1
PR905 1 10 BST_VGA1 2 BST_VGA1 1 2
76.8K_0402_1% PGOOD VBST
1 2 VGA_TRIP 2 9 DH_VGA 1 2 DH_VGA_1 PL901
TRIP DRVH 2.2_0603_5% PR909 0.36UH_PCMC104T-R36MN1R105_37A_20%
1 2 EN_VGA 3 8 LX_VGA 1 2 +VGA_CORE
<14,17,33> DGPU_PWR_EN EN SW
PR908
0_0402_5% 4 VFB V5IN 7 +5VALW
1
PQ902 1
0.1U_0402_10V7K
5
1 2 VGA_RF 5 6 DL_VGA PQ903 PR911
<9,43,46,50,52,54,58> SUSP# RF DRVL
1
4.7_1206_5% + PC901
FB_VGA
PR919
1
11 330U_D_2VM
TPCA8059-H_PPAK56-8-5
TPCA8059-H_PPAK56-8-5
@0_0402_5% TP
1
2
2SNUB_VGA2
PC907 PR910 RT8237CZQW(2) WDFN 10P PWM PC908 2
470K_0402_1% 1U_0603_10V6K 4 4
2
2
2 2
3
2
1
3
2
1
+3VS_DGPU @0.1U_0402_10V7K P_R
PC913 PR920 PC909
1
1 2 1 2 680P_0402_50V7K
1
PR912 PR903
PC910
10K_0402_1% 8.87K_0402_1%
GVID0-2 1 2 1 2 +VGA_COREP1 1 2 +VGA_CORE
PR901
2
D
6
PQ905A 1.8K_0402_1% 0.1U_0402_10V7K
1
2 1GVID0-12 SSM6N7002FU_US6
<14> GPU_VID0 PR913 G 1 2
VDD_SENSE <15>
1
10K_0402_1% PR902 PR914
1
PR915 S 10.5K_0402_1% 100_0402_1%
1
@10K_0402_5%
2
2
PC911
2
0.022U_0402_16V7K
2
PR904
54.9K_0402_1%
N12P-GS Ipeak=35.32A
GVID1-2
1
GPU_VID1 GPU_VID0 +VGA_CORE PR901 PR902 PR903 PR904 PL901
+3VS_DGPU
3
D 0 0 0.825V 3
3
PQ905B
SSM6N7002FU_US6
5
1.8K 10.5K 8.87K 54.9K 0.36uH
1
G
PR916
0 1 0.975V
@10K_0402_1% S
4
1 1 1.0V
2
2 1 GVID1-1
<14> GPU_VID1 PR917
1
12K_0402_1%
1
PR918
10K_0402_5%
PC912
2
0.022U_0402_16V7K
2
4 4
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2008/09/15 Deciphered Date 2011/12/03 Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
+VGA_COREP
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS PBL21 LA6771P M/B 0.3
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Monday, April 11, 2011 Sheet 57 of 59
A B C D
5 4 3 2 1
PC1215
PL1203 PL1201 10U_0805_25V6K
D HCB2012KF-121T50_0805 10UH_VMPI0703AR-100M-Z01_3.5A_20% PD1201 D
B+ 1 2 +12V_B+ 1 2 +12V_SW 1 2 +12V_SW1 2 1 +12VSP
PC1216 10U_0805_25V6K B540C-13-F_SMC2
10U_0805_25V6K
10U_0805_25V6K
1
1
1 2
PC1203
PC1220
2
2
PC1217 10U_0805_25V6K
1 2
2
@100P_0402_50V8J
PC1218 @10U_0805_25V6K PR1201 1 1
0.22U_0603_25V7K
2
1
48.7K_0402_1%
PC1219
1 2
PR1204 + PC1201 + PC1202
PC1205
+3VL 150K_0402_1% 100U_16V 100U_16V
1
PC1204 2 2
1
2 100P_0402_50V8J PU1201 must create part number
10UH_VMPI0703AR-100M-Z01_3.5A_20%
1 2 PQ1201
2
PR1213 PC1206 +12V_RC 1 10 PC1207 PL1202
0.1U_0402_25V6 RC VDD 1U_0402_16V6K
MDV1660URH
100K_0402_1% 1 2 +12V_SS 2 9 +12V_BP 1 2
1
SS BP
PQ1202 +12V_EN 3 8 +12V_GATE 1 PR1208 2+12V_GATE1 4
1
SSM3K7002FU_SC70-3 DIS/EN# GDRV 0_0402_5%
3.01K_0402_1%
D
1
2
+12V_COMP 4 7 +12V_ISNS
C COMP ISNS
PR1202
2 C
G +12V_FB 5 6
3
2
1
FB GND
2
S PC1208
3
2
PC1211 4700P_0402_25V7K 11 1 2 +12V_ISNS1
1
TP PR1210
2+12V_COMP1
1
@100P_0402_50V8J TPS40210DRCR_SON10_3X3 1K_0402_1%
1
100P_0402_50V8J
2
2
2
PC1212
PC1209
100P_0402_50V8J PR1203
1
0.01_1206_1%
1
1
2
PR1209
PR1211 PR1212
0_0402_5% @0_0402_5% 200K_0402_1%
1
1
,43,46,50,52,54,57> SUSP# SYSON <41,43,45,46,51>
B B
PJP121
+12VSP 1 2 +12VS (2A,80mils ,Via NO.= 4)
PAD-OPEN 4x4m
A A
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2009/12/01 Deciphered Date 2011/12/03 Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
PWR+12V_SEPIC
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
WWW.AliSaler.Com
Custom 0.3
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
PBL21 LA6771P M/B
Date: Monday, April 11, 2011 Sheet 58 of 59
5 4 3 2 1
5 4 3 2 1
PIR (Product Improve Record)
PBL80 LA-7441P SCHEMATIC CHANGE LIST
REVISION CHANGE:
Revision Change: 0.1 to 0.2
NO DATE PAGE MODIFICATION LIST PURPOSE
-----------------------------------------------------------------------------------------
D
1 02/18 43 Change R392 to 330K For Compal common design D
2 02/18 39 Delete U10,R400,R401,C331,C332 Change LID SW to USB small board.
3 02/24 45 Change D23 to D23 and D7
4 02/25 12 Add C202,C208,C216,C218 Add 0.1U X4 for EMI request.
5 02/25 43 Add R431,C406 Add RC for EMI request.
6 03/02 39 Add L22,L23,L23,R183,R214,R216,R218,R222,R224 For EMI request.
7 03/02 43 Add R391 For EC request.
8 03/02 28 Add C319 For ESD request.
9 03/02 28 Add C500,C501 For ESD request.
10 03/02 41 Add R433,C421 For EMI request.
11 03/02 41 Add R1553,C402 For HW test.
12 03/02 43 Add C308 For ESD request.
13 03/02 43 Delete R409 For HW no need.
14 03/02 44 Add C407,C408,C409,C420 For ESD request.
15 03/02 44 Delete C333,R406 For ESD request.
Revision Change: 0.2 to 0.3
C C
NO DATE PAGE MODIFICATION LIST PURPOSE
-----------------------------------------------------------------------------------------
1 03/21 5 Add C55 For ESD request.
2 03/21 43 Add C323 For ESD request.
3 03/31 44 Add C307,C324 For ESD request.
4 04/06 5 Add C56,C57 For ESD request.
5 04/06 5 Add C327 For ESD request.
B B
A A
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2010/12/03 Deciphered Date 2011/12/03 Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
HW-PIR
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
0.3
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
PBL80 LA-7441P M/B
Date: Monday, April 11, 2011 Sheet 59 of 59
5 4 3 2 1
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