Device Name ZU21DR ZU25DR ZU27DR ZU28DR ZU29DR ZU39DR ZU42DR ZU43DR ZU46DR ZU47DR ZU48DR ZU49DR

Gen 1 Gen 2 Gen 3

PS
Quad-core Arm® Cortex®-A53 MPCore™ up to 1.3GHz, Dual-core Arm Cortex-R5F MPCore up to 533MHz
12-bit RF-ADC # of ADCs 0 8 8 8 16 16 – – – – – –
w/DDC Max Rate (GSPS) 0 4.096 4.096 4.096 2.058 2.220 – – – – – –
RF Data Converter

14-bit RF-ADC # of ADCs – – – – – – 8 2 4 8 4 8 8 16

w/DDC Max Rate (GSPS) – – – – – – 2.5 5.0 5.0 2.5 5.0 5.0 5.0 2.5
14-bit RF-DAC # of DACs 0 8 8 8 16 16 8 4 12 8 8 16
w/DUC Max Rate (GSPS) 0 6.554 6.554 6.554 6.554 6.554 9.85(3) 9.85(3) 9.85(3) 9.85(3) 9.85(3) 9.85(3)
SD-FEC 8 0 0 8 0 0 0 0 8 0 8 0
Digital Front-End (DFE) – – – – – – – – – – – –
Number of DDCs per RF-ADC(1) 0 1 1 1 1 1 1 2 1 1 1 1
RF input Freq max. GHz 4 5 6

Zynq™ UltraScale+™ RFSoCs

Decimation / Interpolation 1x, 2x, 4x, 8x 1x, 2x, 4x, 8x 1x, 2x, 3x, 4x, 5x, 6x, 8x, 10x, 12x, 16x, 20x, 24x, 40x
System Logic Cells (K) 930 678 930 930 930 930 489 930 930 930 930 930
CLB LUTs (K) 425 310 425 425 425 425 224 425 425 425 425 425
Max. Dist. RAM (Mb) 13.0 9.6 13.0 13.0 13.0 13.0 6.8 13.0 13.0 13.0 13.0 13.0
Programmable Logic (PL)

Total Block RAM (Mb) 38.0 27.8 38.0 38.0 38.0 38.0 22.8 38.0 38.0 38.0 38.0 38.0
UltraRAM (Mb) 22.5 13.5 22.5 22.5 22.5 22.5 45.0 22.5 22.5 22.5 22.5 22.5
DSP Slices 4,272 3,145 4,272 4,272 4,272 4,272 1,872 4,272 4,272 4,272 4,272 4,272
GTY Transceivers 16 8 16 16 16 16 8 16 16 16 16 16
PCIe® Gen3 x16 2 1 2 2 2 2 – – – – – –
PCIe® Gen3 x16/Gen4 x8 / CCIX(2) – – – – – – 0 2 2 2 2 2
150G Interlaken 1 1 1 1 1 1 0 1 1 1 1 1
100G Ethernet MAC/PCS w/RS-FEC 2 1 2 2 2 2 0 2 2 2 2 2
System Monitor 2 2 2 2 2 2 2 2 2 2 2 2 2
-1E, -1I, -1LI, -1E, -1I, -1LI, -1E, -1I, -1LI, -1E, -1I, -1LI, -1E, -1I, -1LI,
-1E, -1I, -1LI, -1E, -1I, -1LI, -1E, -1I, -1LI, -1E, -1I, -1LI, -1E, -1I, -1LI, -1E, -1I, -1LI,
Speed Grades -2E, -2LE, -2I, -2E, -2LE, -2I, -2E, -2LE, -2I, -2E, -2LE, -2I, -2E, -2LE, -2I, -2I, -2LI
-2E, -2I, -2LI -2E, -2I, -2LI -2E, -2I, -2LI -2E, -2I, -2LI -2E, -2I, -2LI -2E, -2I, -2LI
-2LI -2LI -2LI -2LI -2LI
PSIO, HDIO, HPIO PSIO, HDIO, HPIO PSIO, HDIO, HPIO PSIO, HDIO, HPIO PSIO, HDIO, HPIO PSIO, HDIO, HPIO PSIO, HDIO, HPIO PSIO, HDIO, HPIO PSIO, HDIO, HPIO PSIO, HDIO, HPIO PSIO, HDIO, HPIO PSIO, HDIO, HPIO
Package
Package Dimensions GTR, GTY GTR, GTY GTR, GTY GTR, GTY GTR, GTY GTR, GTY GTR, GTY GTR, GTY GTR, GTY GTR, GTY GTR, GTY GTR, GTY
Footprint
RF-ADC, RF-DAC RF-ADC, RF-DAC RF-ADC, RF-DAC RF-ADC, RF-DAC RF-ADC, RF-DAC RF-ADC, RF-DAC RF-ADC, RF-DAC RF-ADC, RF-DAC RF-ADC, RF-DAC RF-ADC, RF-DAC RF-ADC, RF-DAC RF-ADC, RF-DAC
214, 72, 208
D1156 35x35 4, 16
0, 0
214, 48, 104 214, 48, 104 214, 48, 104 214, 24, 128 214, 48, 104 214, 48, 104 214, 48, 104
E1156 35x35 4, 8 4, 8 4, 8 4, 8 4, 8 4, 8 4, 8
8, 8 8, 8 8, 8 10, 8 4, 4 8, 8 8, 8
214, 48, 299 214, 48, 299 214, 48, 299 214, 48, 299 214, 48, 299 214, 48, 299
G1517 40x40 4, 8 4, 16 4, 16 4, 16 4, 16 4, 16
8, 8 8, 8 8, 8 4, 4 8, 8 8, 8
214, 96, 312 214, 96, 312 214, 96, 312
F1760 42.5x42.5 4, 16 4, 16 4, 16
16, 16 16, 16 16, 16
214, 48, 312
H1760 42.5x42.5 4, 16
2 | 12, 12
1. This value applies when all RF I/O of an RF-ADC tile are used. 2. Operates in compatibility mode for 16.0GT/s (Gen4) operation. See PG213. 3. For operation up to 10GSPS, contact your local Xilinx Sales Representative.
 Device Name ZU63DR ZU64DR ZU65DR ZU67DR
DFE
RF Data Converter PS

Quad-core Arm® Cortex®-A53 MPCore™ up to 1.3GHz, Dual-core Arm Cortex-R5F MPCore up to 533MHz
# of ADCs 4 2 8 2 6 8 2
14-bit RF-ADC w/DDC
Max Rate (GSPS) 2.95 5.9 2.95 5.9 5.9 2.95 5.9
# of DACs 4 8 6 8

Zynq™ UltraScale+™ RFSoCs

14-bit RF-DAC w/DUC
Max Rate (GSPS) 10.0(3) 10.0(3) 10.0(3) 10.0(3)
SD-FEC 0 0 0 0
Digital Front-End Hard IP (DFE IP) Channel Filter, DUC/DDC, Mixer, CFR, Complex Equalizer, PQ Resampler, DPD
Low PHY Hard IP FFT/iFFT, PRACH None FFT/iFFT, PRACH FFT/iFFT, PRACH
Number of DDCs per RF-ADC(1) 1 1 1 1
RF input Freq max. GHz 7.125
Decimation / Interpolation 1x, 2x, 3x, 4x, 5x, 6x, 8x, 10x, 12x, 16x, 20x, 24x, 40x
System Logic Cells (K) 393 328 489 489
Programmable Logic (PL)

CLB LUTs (K) 180 150 224 224

Max. Dist. RAM (Mb) 5.47 4.56 6.8 6.8
Total Block RAM (Mb) 17.6 15.8 22.8 22.8
UltraRAM (Mb) 36.6 22.5 45.0 45.0
DSP Slices 1,200 1,872 1,872 1,872
GTY Transceivers 4 8 8 8
PCIe® Gen3 x16/Gen4 x8 / CCIX(2) 0 0 0 0
150G Interlaken 0 0 0 0
100G Ethernet MAC/PCS w/RS-FEC 1 1 1 1
System Monitor 2 2 2 2
-1I, -1LI, -1I, -1LI, -1I, -1LI, -1I, -1LI,
Speed Grades
-2I, -2LI -2I, -2LI -2I, -2LI -2I, -2LI
PSIO, HDIO, HPIO PSIO, HDIO, HPIO PSIO, HDIO, HPIO PSIO, HDIO, HPIO
Package Footprint Package Dimensions GTR, GTY GTR, GTY GTR, GTY GTR, GTY
RF-ADC, RF-DAC RF-ADC, RF-DAC RF-ADC, RF-DAC RF-ADC, RF-DAC
214, 24, 130 214, 24, 130 214, 24, 130 214, 24, 130
E1156 35x35 4, 8 4, 8 4, 8 4, 8
6, 4 10, 8 6, 6 10, 8

Notes:
1. This value applies when all RF I/O of an RF-ADC tile are used.
2. Operates in compatibility mode for 16.0GT/s (Gen4) operation. See PG213.
3. 10GSPS RF-DAC operation is available in -2I speed grade.
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 Zynq® UltraScale+™ RFSoC Ordering Information

Device Name Device Attributes Footprint

XC ZU ## D R -1 F F V D #### E
Device Grade Zynq Value Processor Engine Type Speed Grade F: Flip-chip F: Lid V: RoHS 6/6 Package Package Temperature
Commercial UltraScale+ Index System R: RF Signal -1: Slowest w/ 1.0mm S: Lidless Stiffener Designator Pin Count Grade
Identifier -L1: Low Power Ball Pitch (E, I)
D: Quad APU; -2: Mid
Dual RPU -L2: Low Power

E = Extended (Tj = 0°C to +100°C)

I = Industrial (Tj = –40°C to +100°C)
Note: -L2E (Tj = 0°C to +110°C); -L2I (Tj = –40°C to +110°C)
Refer to DS889, Zynq UltraScale+ RFSoC Data Sheet: Overview for additional information

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 Disclaimer and Attribution
The information contained herein is for informational purposes only and is subject to change without notice. While every precaution has been taken in the
preparation of this document, it may contain technical inaccuracies, omissions and typographical errors, and AMD is under no obligation to update or otherwise
correct this information. Advanced Micro Devices, Inc. makes no representations or warranties with respect to the accuracy or completeness of the contents of this
document, and assumes no liability of any kind, including the implied warranties of noninfringement, merchantability or fitness for particular purposes, with respect
to the operation or use of AMD hardware, software or other products described herein. No license, including implied or arising by estoppel, to any intellectual
property rights is granted by this document. Terms and limitations applicable to the purchase or use of AMD’s products are as set forth in a signed agreement
between the parties or in AMD's Standard Terms and Conditions of Sale. GD-18

© Copyright 2023 Advanced Micro Devices, Inc. All rights reserved. Xilinx, the Xilinx logo, AMD, the AMD Arrow logo, Zynq, and other designated brands
included herein are trademarks of Advanced Micro Devices, Inc. Other product names used in this publication are for identification purposes only and may be
trademarks of their respective companies.

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