EE204

Logic Circuits
Combinational Circuits

Avni Morgül
Combinational Logic
INTRODUCTION
• Logic circuits for digital systems may be combinational or sequential.
• A combinational circuit consists of logic gates whose outputs at any
time are determined from only the present combination of inputs.
• Performs an operation that can be specified by a set of Boolean functions.
• Sequential circuits employ storage elements in addition to logic
gates.
• Their outputs are a function of the present inputs and the previous inputs
which are stored in the storage elements.
Combinational Logic
• Consists of an interconnection of logic gates.

n inputs Combinational m inputs

circuit

• For n input variables, there are 2n possible combinations.

• For each input combination, there is one possible value for each output variable.
• Thus, a combinational circuit can be specified with
• an n-input/m-output truth table
• or m Boolean functions, for m output variable.

• There are several combinational circuits that are used extensively in the design of digital
systems. These circuits are called standard components, such as adders, subtractors,
comparators, decoders, encoders, and multiplexers. These components are available in
integrated circuits as medium-scale integration (MSI) circuits.
ANALYSIS PROCEDURE
• Determination of the function of a given logic diagram. The analysis can be
performed manually by finding the Boolean functions by using truth table or by
using a computer simulation program.
• To obtain the output Boolean functions from a logic diagram:
1. Label all gate outputs that are a function of input variables with arbitrary
symbols with meaningful names. Determine the Boolean functions for each
gate output.
2. Label the gates that are a function of input variables and previously labeled
gates. Find the Boolean functions for these gates.
3. Repeat the process outlined in step 2 until the outputs of the circuit are
obtained.
4. By repeated substitution of previously defined functions, obtain the output
Boolean functions in terms of input variables.
Example
A T2
B
C F1
Step 1:
A T1
F2 = AB + AC + BC B
C T3
T1 = A + B + C F2

T2 = ABC A
B

A
F2
C

B
C
Obtaining the truth table directly from the logic diagram
• To obtain the truth table directly from the logic diagram without going
through the derivations of the Boolean functions, proceed as follows:
1. Determine the number of input variables in the circuit. For n inputs,
form the 2n possible input combinations and list the binary numbers
from 0 to (2n - 1) in a table.
2. Label the outputs of selected gates with arbitrary symbols.
3. Obtain the truth table for the outputs of those gates which are a
function of the input variables only.
4. Proceed to obtain the truth table for the outputs of those gates
which are a function of previously defined values until the columns
A T2
for all outputs are determined. B
C F1
A T1
AB AB B
C T3
C 00 01 11 10 C 00 01 11 10 F2

0 0 1 0 1 0 0 0 1 0 A
B
1 1 0 1 0 1 0 1 1 1 A
F2
C

𝐹1 = 𝐴ҧ 𝐵𝐶
ത F+ 𝐴𝐵ҧ 𝐶ҧ + 𝐴𝐵ത 𝐶ҧ + 𝐴𝐵𝐶
1 = ABC+ABC+ABC+ABC
𝐹F22 =
= AB+AC+BC
𝐴𝐵 + 𝐴𝐶 + 𝐵𝐶 B
C
DESIGN PROCEDURE
The design of combinational circuits means obtaining the logic diagram
of a logic function.
• The procedure involves the following steps:
1. From the specifications of the circuit, determine the required number of
inputs and outputs and assign a symbol to each.
2. Derive the truth table that defines the required relationship between inputs
and outputs.
3. Obtain the simplified Boolean functions for each output as a function of the
input variables.
4. Draw the logic diagram and verify the correctness of the design (manually or
by simulation).
Example: Code Conversion
Different codes are used by different digital systems.
A code conversion circuit may be required to be inserted
between the two systems.
The design procedure will be illustrated by an example that
converts binary coded decimal (BCD) to the excess-3
code (a self-complement code) for the decimal digits.

Each row is the

complement of
the reflected
code
Binary coded decimal (BCD) to the Excess-3
code Converter circuit

D z
D CD
ഥ
• 𝑧=𝐷 Common terms C y
• 𝑦 = 𝐶𝐷 + 𝐶ҧ 𝐷
ഥ C+D
C+D
ത + 𝐵𝐷
• 𝑥 = 𝐵𝐶 ത + 𝐵 𝐶ҧ 𝐷
ഥ = 𝐵ത 𝐶 + 𝐷 + 𝐵(𝐶 + 𝐷)
• 𝑤 = 𝐴 + 𝐵𝐶 + 𝐵𝐷 = 𝐴 + 𝐵(𝐶 + 𝐷) B
x

w
A
Adders Subtractors
• The most basic arithmetic operation is the addition of two binary digits.
• Addition consists of four possible elementary operations:
0+0= 0

ADDER
Number A Sum S=A+B
0+1= 1
1+0= 1 Number B Carry C
1 + 1 = 10
• The first three operations produce a sum of one digit, but when both bits are 1, the sum
consists of two digits.
• The higher significant bit of result is called a carry.
• A combinational circuit that performs the addition of two bits is called a half adder .
• The addition of three bits (two significant bits and a previous carry) is performed by a full
adder .
Half-Adder
• The input variables designate the augend and addend bits; the
output variables produce the sum (S) and carry (C). The C
output is 1 only when both inputs are 1.
• The simplified sum-of-products expressions are
Full-Adder
A full-adder is a combinational circuit that forms the arithmetic
sum of three bits. It consists of three inputs and two outputs.
The third input, z , represents the carry from the previous adder
block. So, full-adders can be cascaded!

Half Ader Half Ader

x x+y (x + y) + z
A S
B y
xy (x + y) z + xy
Cout
z
Cin
Full Ader
Adding multi-bit numbers
• To demonstrate with a specific example, consider the two binary
numbers A = 1011 and B = 0011. Their sum S = 1110 is formed
with the four-bit adder as follows:
Subscript ( i ) 3 2 1 0
S0 S1 S2 S3
Input carry 0 1 1 0 Ci
C1 C2 C3
Augend 1 0 1 1 Ai C0 FA FA FA FA Cout

Addend 0 0 1 1 Bi
A0 B0 A1 B1 A2 B2 A3 B3
Sum 1 1 1 0 Si
Output carry 0 0 1 1 Ci+1
Carry Propagation
• The addition of two binary numbers implies that all the bits of the augend,
addend and carry are available for computation at the same time. But, in any
combinational circuit, the signal must propagate through the Gates.
• The total propagation time is equal to the propagation delay of a typical gate
times the number of gate levels in the circuit. The longest propagation delay is
the time for the carry to propagate.
• For an n-bit adder, there are 2n gate levels for the carry to propagate from
input to output
Half Ader Half Ader
Pi (Pi + Ci)
Ai
Bi Si

Gi PiCi+Gi
Ci+1

Ci
 Lookahead Carry Generator
Half Ader Half Ader
Pi (Pi + Ci)
Ai
Bi Si

Gi PiCi+Gi
Ci+1

Ci (2-gate delay)

In the circuit of the full adder shown above we define two new binary variables
Look-ahead Carry Generator
Now lets re-write the Boolean functions for the carry outputs of each stage
Half Ader Half Ader
Pi (Pi + Ci)
Ai
Bi Si

Gi PiCi+Gi
Ci+1

Ci

A0 S0 S1 S2
A1 A2
B0 FA0 B1 FA1 B2
FA1 FA2
C0 = input carry C0 C1 C2 C3

C1 = G0 + P0C0 (6-gate delay)

C2 = G1 + P1C1 = G1 + P1(G0 + P0C0) = G1 + P1G0 + P1P0C0

C3 = G2 + P2C2 = G2 + P2G1 + P2P1G0 + P2P1P0C0
Lookahead Carry Generator

Half
Adder

Lookahead Carry Generator

4-Bit Full-adder
Binary subtractor
• The circuit for subtracting A-B consists of an adder with inverters placed
between each data input B.
• the circuit is an adder,
• the circuit becomes a subtractor.
• It is also possible to implement S0 S1 S2 S3
Overflow
subtraction by using 2’s C0 C1 C2 C3 C4
complement numbers. In that FA FA FA FA Cout

case addition and subtraction

may be implemented by an
adder circuit.
M A0 B0 A1 B1 A2 B2 A3 B3
BCD Adder
Since each input digit does not exceed 9, the
output sum cannot be greater than 9 + 9 + 1 = 19 C = K + Z8Z4 + Z8Z2
When C = 1, it is necessary to add 0110 to the binary
sum and provide an output carry for the next stage
 Magnitude Comparator
• The outcome of the comparison is specified by three binary variables
that indicate if A < B, A = B, or A > B.
• Two n-bit numbers has 2n entries.
• Consider two 4-bit numbers A=A3A2A1A0 and B=B3B2B1B0
• The equality of each pair of bits can be expressed logically with an
exclusive-NOR function as
xi=Ai Bi + A’i B’i for i = 0, 1, 2, 3
The resulting equations:
(A=B) = x3 x2 x1 x0
(A>B) = A3B’3 + x3 A2B’2 + x3 x2 A1B’1 + x3 x2 x1 A0B’0
(A<B) = A’3B3 + x3 A’2B2 + x3 x2 A1B’1 + x3 x2 x1 A0B’0
Magnitude Comparator Circuit

(A=B) = x3 x2 x1 x0
(A>B) = A3B’3 + x3 A2B’2 + x3 x2 A1B’1 + x3 x2 x1 A0B’0
(A<B) = A’3B3 + x3 A’2B2 + x3 x2 A1B’1 + x3 x2 x1 A0B’0
DECODER/ENCODER
3 to 8 Line Decoder Octal-to-Binary Encoder
𝐷0 = 𝑥ҧ 𝑦ത𝑧ҧ D0
z 𝐷1 = 𝑥ҧ 𝑦ത𝑧
D1
8 to 3
x
. y
ENCODER
. z
𝐷2 = 𝑥ҧ 𝑦𝑧ҧ .
D7
y
𝐷3 = 𝑥ҧ 𝑦𝑧

x 𝐷4 = 𝑥𝑦ത𝑧ҧ

𝐷5 = 𝑥𝑦ത𝑧
𝐷6 = 𝑥𝑦𝑧ҧ

𝐷7 = 𝑥𝑦𝑧
Priority Encoder
The priority encoder identifies a particular input
when several inputs are high (logic 1). Such as: D2 D1 D0 x y
D2 : Highest priority input. Encoded to xy = 01
D1 : Middle priority input. Encoded to xy = 10 0 0 0 0 0 inactive
D0 : Lowest priority input. Encoded to xy = 11 0 0 1 1 1 D0
Inactive state xy = 00
The xy outputs may be selected differently than this example.
0 1 0 1 0
D1
0 1 1 1 0
1 0 0 0 1
1 0 1 0 1
D2
1 1 0 0 1
D0 1 1 1 0 1
D0
D1 D1 y
x
D2 D2
Quiz
Design a 3-input priority encoder such that
• D2: The highest priority xy = 11
• D1: Middle priority xy = 01
• D0: The lowest priority xy = 10
• Inactive State xy = 00
Here D2, D1, D0 are the inputs and xy are the outputs of the encoder.
Lecture 5: MULTIPLEXERS (MUX)
A multiplexer is a combinational circuit that selects binary information from one
of many inputs. The selection of a particular input line is controlled by a set of
selection lines. There are 2n input lines and n selection lines.

00 I0
I0
I1 01 output
Y I1 4x1
I2
10 inputs Y
11 I2 MUX
I3 S1S0
I3

S1 S0
4x1 Multiplexer Circuit

Y = I0  S1 S0 = 00
Y = I1  S1 S0 = 01
Y = I2  S1 S0 = 10
Y = I3  S1 S0 = 11
 Boolean Function Implementation
by using a MUX
An n variable logic function may be implemented with a multiplexer that has
n selection inputs and 2n data inputs, one for each minterm.

But this is a waste of possible usage of the

inputs.
Implementation by using a MUX
It is possible to implement an n+1 variable function by using a multiplexer
with n selection inputs. One of the variables are connected to the inputs.
Example:
Implementation by using a MUX
There is an easier way to implement by using a simple table instead of truth table.
• Procedure: Example: F(A,B,C)=(1,4,5,6)
1. Draw a nx2 table I0 I1 I2 I3
2. Label the row C=0 and C=1 C=0 0 2 4 6
3. Labe the columns as Ii C=1 1 3 5 7
4. Labe the cells with the minterm numbers C 0 1 C’
5. Round the cells which are the minterms in the equation
6. Name each column with either 0 (if there is no round at this column) or 1 (if
both row are rounded), C (if the round is at C=1 row) or C’ (if the round is at
C=0 row)
7. Connect C or C’ to the related inputs, Ii , as shown in the previous figure.
I0=C, I1=0, I2=1, I3=C’
Implementation by using a MUX
More examples

I0 I1 I2 I3 I0 I1 I2 I3 I4 I5 I6 I7
C=0 0 2 4 6 D=0 0 2 4 6 8 10 12 14
C=1 1 3 5 7 D=1 1 3 5 7 9 11 13 15
D 0 1 D’ 0 0 D’ 1
F2
0 C 1 C’

F1
Implementation with Read-Only-Memory (ROM)
An n input decoder generates 2n minterms. Any of these minterms may be added by using
multy-input OR Gates to sum the minterms and generate any desired function. Any number
(m) of outputs may be obtained simultaneously.

ROM Size = 2n x m
Programmable Logic Array (PLA)
Field Programmable Gate Arrays (FPGA)
• A combinational circuit usually have Don’t Care conditions. These conditions become an
address input that will never ocur. So, it is a waste of available equipment if a ROM is
used when Don’t Care conditions are excessive.
• In that case it is more convenient to use another LSI (Large Scale Integrated circuit)
component called PLA.
• In PLA the decoder of ROM is replaced by a group of AND Gates. The logic function is
generated in SOP form.
• A PLA has n-inputs, m-outputs, k-product terms and m-sum terms.
m
nxk kxm
k-product links m-sum
terms terms m
(AND (OR m outputs
Gates) Gates) links
n-inputs nxk
links
Programming a PLA
• To program a PLA (or FPGA)
1.
The output functions and their complements are obtained using Karnaugh maps.
2.
All product terms and outputs are listed in a table
The minimum number of distinct product terms is found for output F and its invers F’
3.
4.
Necessary connections are done
AB AB
• Example: C 00 01 11 10
0 0 0 1 0
C 00 01 11 10
0 1 1 0 1
1 0 1 1 1 1 0 0 1 0

Product Inputs Outputs F1 = AB+AC+BC F2 = AC+BC+ABC

Max. # of AND gates: 4 Terms A B C F1 F2 AB AB
Max. # of of AND gate inputs: 3
BC 1 0 0 1 1 C 00 01 11 10 C 00 01 11 10
Max. # of OR gates: 2 AC 2 0 0 1 1 0 0 0 1 0 0 1 1 0 1
Max. # of OR gate inputs: 3 AB 3 0 0 1 1 0 1 1 1 1 0 0 1 0
ABC 4 1 1 1 1 F1 = AB+AC+BC F2 = AC+BC+ABC
True or Complement C T These two functions can be
realized by using only 4 terms
Implementation with the PLA
• Implementation of the given functions simultaneously by
using a PLA or FPGA which uses four 6-input (only 3 of the
inputs are used) AND gates and two 4-input OR Gates.
A BC
F1
B F1
AC
F2
C F2
AB
F1 = AB+AC+BC

ABC F2 = AC+BC+ABC
QUIZ
• Write the value of each input of the multiplexer (Ii), to implement
the following function:
F(ABC) = (1,4,5,6) =A’B’C+AB’C’+AB’C+ABC’

C I0
4x1
I1 MUX
Y F
I2
I3 S1 S0

A B