‫تجميعات االمتحان النهائية‬ ‫‪Khadijah‬‬

‫‪TM103 - Final‬‬ ‫‪Z‬‬

‫‪Raven‬‬
‫‪Abdullah‬‬
‫‪Yazeed‬‬

‫بسم هللا الرحمن الرحيم‬

‫‪TM103‬‬
‫حِلف الطالب العصاميين يقدم لكم النسخة الثانية من تجميعات االمتحانات النهائية محلول ًة بالكامل‪.‬‬
‫وتعقب وراجع النسخ‪ ،‬ومَن جمع الملفات على مر السنين‪.‬‬ ‫َّ‬ ‫الشكر ُمسدى لكل من صحَح‬
‫مقرر أولى وأكثر أهمية‪.‬‬ ‫نرجو أال تكون هذه التجميعات محل اعتمادكم في المذاكرة‪ ،‬فشرائح ال ُ‬
‫يغلب على النماذج تكرار األفكار األسئلة‪ ،‬لذا ننصح بالرجوع إليها واالهتمام بها‬

‫ف ي َر َٰى‪ ،‬ث َّم ي ۡجزَ َٰىه ٱ ۡل َجزَ آ َء ٱ ۡۡل َ ۡوفَ َٰى{‬ ‫س َع َٰى‪َ ،‬وأَ َّن َ‬
‫سعۡ يَهۥ َ‬
‫س ۡو َ‬ ‫س ِن ِإ ََّّل َما َ‬ ‫س ِل ۡ ِ‬
‫ۡلن َٰ َ‬ ‫} َوأَن لَّ ۡي َ‬

‫حرر في‪:‬‬
‫النسخة الثانية (‪)2‬‬ ‫‪16/2/1445 – 01/09/2023‬‬
‫الفصل الصيفي ‪Summer 22-23‬‬
PART 2 Q1 ANSWER:

PART 2 Q2 ANSWER:

a. Jump 6F0
b. Store 840

PART 2 Q3 ANSWER:

a. allow movement of data between a system and its external devices.

b.
− Data lines
− Control lines
− Address lines

PART 2 Q4 ANSWER:

SRAM: Static RAM

USB: Universal Serial Bus
ROM: Read Only Memory

PART 2 Q5 ANSWER:

a. SOP: x`y`z + x`yz + x`yz` + xyz + xyz`

b. Simplified F(x, y, z) = x`z + y

yz yz'
y'z’ y'z

x' 0 1 1 1

x 0 0 1 1
PART 3 Q1 ANSWER:

a.

(-72) = -(01001000) = (10110111) c1

(+48) = (00110000) c1

b.

1 1

10110111
00110000 +
------------------------
11100111

c. Since there is no carry out 1 from the eighth bits addition, the result is correct.

PART 3 Q2 ANSWER:

Value in AC Value in AC
Mode
after Load 500 after Subt 200
Immediate 500 300
Direct 300 200
Indirect 400 200
indexed 300 000

PART 3 Q3 ANSWER:

a. The org 300 directive sets the starting address of the program to 300 in memory. This means
that the first instruction of the program will be placed at memory location 300.

b. The “jump Else” instruction will be executed if the value of AC ≤ 0, in our case it will be
skipped since the value of AC = 2 due to the skipcond 800 (AC > 0 skips next instruction).

c. It will display 9

d. Value of 𝑥 = 6, because it’s unchanged by the program.

PART 3 Q4 ANSWER:

a. Size of main memory is 2(𝑡𝑎𝑔+𝑏𝑙𝑜𝑐𝑘+𝑤𝑜𝑟𝑑) = 𝟐𝟐𝟎

b. Number of blocks in cache memory is 2(𝑏𝑙𝑜𝑐𝑘𝑠) = 𝟐𝟏𝟎

c. Number of blocks in main memory is 2(𝑡𝑎𝑔+𝑏𝑙𝑜𝑐𝑘𝑠) = 𝟐𝟏𝟒

d.

− Word = 26 = 𝟔 𝐛𝐢𝐭𝐬
− Set = 210 / 23 = 𝟕 𝐛𝐢𝐭𝐬
− Tag = 20 − 6 − 7 = 𝟕 𝐛𝐢𝐭𝐬

7 7 6
tag set word
20 bits
‫الفصل الثاني ‪Spring 22-23‬‬
PART 2 Q1 ANSWER:

PART 2 Q2 ANSWER:

a) Jump 2A0
b) Clear

PART 2 Q3-A ANSWER:

Feedback in digital circuits occurs when an output is looped back to the input. sequential circuits
rely on feedback to remember a past state.

PART 2 Q3-B ANSWER:

− Sequential logic circuits must have a memory to remember values and store previous
inputs and outputs.
− Combinational circuits are memoryless; they don’t have the concept of storage.

PART 2 Q4 ANSWER:

IEEE: The Institute of Electrical and Electronic Engineers

EEPROM: electrically erasable PROM
USB: Universal Serial Bus

PART 2 Q5 ANSWER:

a) a’b’c’ + a’b’c + abc + abc’

b) F(a, b, c) = ab + a’c’ + bc’
PART 3 Q1 ANSWER:

a)

𝑥 𝑦 𝑧 𝑥` 𝑦` 𝑧` 𝑦` . 𝑧` 𝑥` + 𝑧` 𝑦. (𝑥` + 𝑧`) 𝑦` . 𝑧` + 𝑦(𝑥` + 𝑧`)

0 0 0 1 1 1 1 1 0 1

0 0 1 1 1 0 0 1 0 0

0 1 0 1 0 1 0 1 1 1

0 1 1 1 0 0 0 1 1 1

1 0 0 0 1 1 1 1 0 1

1 0 1 0 1 0 0 0 0 0

1 1 0 0 0 1 0 1 1 1

1 1 1 0 0 0 0 0 0 0

b)

Simplified F(x,y,z) = x’.y + z’

y`z` y`z yz yz`

x` 1 0 1 1

1 1
x 0 0

PART 3 Q2-A ANSWER:

(-68) = -(01000100) = 10111011c1 +1 = 10111100c2

(-64) = -(01000000) = 10111111c1 +1 = 11000000c2

PART 3 Q2-B ANSWER:

10111100
11000000
---------------
01111100 ⟶ - (10000011 + 1) = -132

01111100c2 = - (100001002) = -13210

PART 3 Q2-C ANSWER:

The carry-in and the carry-out are equal so it’s correct.

PART 3 Q3 ANSWER:

Value in AC Value in AC
Mode
after Add 400 after store 200
Immediate 1000 1000
Direct 900 900
Indirect 1200 1200
indexed 1000 1000

PART 3 Q4 ANSWER:

a) 227 bytes

b) 215 blocks

c) 227 / 26 = 221

d)

− Word: 26 = 6 bits

− Set: 215 / 24 = 11 bits

− Tag: 27 - 6 - 11 = 10 bits

10 11 6
tag set word
27 bits
‫الفصل األول ‪Fall 22-23‬‬
PART 2 Q1 ANSWER:

a) Load 4A0
b) Output

PART 2 Q2 ANSWER:

a) A Bus is a set of wires that simultaneously convey a single bit along each line (parallel
movement). It connects multiple subsystems within the system.

b)

− Data lines: are dedicated to moving data (the actual information that must be moved).

− Control lines: indicate which device has permission to use the bus and for what purpose
(reading or writing from memory or from an I/O device, …)

− Address lines: indicate the location (in memory, for example) that the data should be either
read from or written to.
PART 2 Q3 ANSWER:

SATA: serial advanced technology attachment

USB: Universal Serial Bus
EEPROM: electrically erasable PROM

PART 2 Q4 ANSWER:

a) x′y’z + xy’z + xyz + xyz’

b) f(x, y, z) = y’z + xy

PART 2 Q5 ANSWER:

PART 3 Q1-A ANSWER:

(-64) = -(01000000) = 10111111c1

(-68) = -(01000100) = 10111011c1

PART 3 Q1-B ANSWER:

10111111
10111011
------------------
01111010
+
1
------------------
01111011 ⟶ -(10000100) = -132

PART 3 Q1-C ANSWER:

It’s correct; the carry-in and the carry-out are equal.

PART 3 Q2 ANSWER:

a)

INPUT
STORE x
INPUT
STORE y
LOAD y
SUBT x
STORE z
JUMP End
LOAD x
End, OUTPUT
HALT

b) 3

PART 3 Q3 ANSWER:

Value in AC after Value in AC after

Mode
Add 400 Store 200
Immediate 1600 1600
Direct 1500 1500
Indirect 1800 1800
Indexed 1600 1600

PART 3 Q4 ANSWER:

a) 224 bytes
b) 212 blocks
c) 224 / 26 = 218

d)

− Word: 26 = 6 bits
− Set: 212 / 23 = 9 bits
− Tag: 24-9-6 = 9 bits

e)

9 9 6
tag Set word
24 bits
‫الفصل الصيفي ‪Summer 21-22‬‬
PART 2 Q1 ANSWER:

level 6: User
Level 5: High level Language
Level 4: Assembly Language
Level 3: System software
Level 2: Instruction Set Architecture (ISA), or Machine Level
Level 1: Control
Level 0: Digital Logic

PART 2 Q2 ANSWER:

Subt y:
MAR ⟵ y
MBR ⟵ M[MAR]
AC ⟵ AC - MBR

Load y:
MAR ⟵ y
MBR ⟵ M[MAR]
AC ⟵ MBR

PART 2 Q3 ANSWER:

JK flip-flop provides a stable state when both inputs are 1. Where the present output is the
complement of the past output instead of being undefined as in the SR flip-flop.

PART 2 Q4 ANSWER:

a) 1000 0100 0000 0000

b) 0110 0000 0000 0000

PART 2 Q5 ANSWER:
PART 3 Q1 ANSWER:

ORG 300
Input
Store x
Load x
Subt z
Store y
Load y

If, Skipcond 800

Jump Else
Output
Halt

Else, load x
Output
Halt

X, DEC 0
Y, DEC 0
Z, DEC 5

PART 3 Q2 ANSWER:

Value in AC after Value in AC after

Mode
Add 400 Load 200
immediate 800 200
Direct 700 400
Indirect 1000 300
indexed 800 300

PART 3 Q3 ANSWER:

a)

-46 = 10101110
-99 = 11100011

b)

10101110 (-46)
+ 11100011 (-99)
------------------
10010001 (-17) which is erroneous

c) The addition overflows, the last carry is discarded, the result is incorrect.
PART 3 Q4 ANSWER:

a) 26 * 220 / 25 = 221 blocks

b)

− Word: 32 = 25 ⟶ 5 bits
− Blocks: 16K = 24 * 210 ⟶ 14 bits
− Tag: 26 - (5+14) = 7 bits

7 14 5
Tag block word

26 bits

c)

− Word: 32 = 25 ⟶ 5 bits
− Set: 16K / 8 = 11 bits
− Tag: 26-5-11= 10 bits

10 11 5
Tag set word

26 bits
‫الفصل الثاني ‪Spring 21-22‬‬
PART 2 Q1 ANSWER:

J-K flip-flop modified the SR flip-flop to provide a stable state when both inputs are1, where the
present output is the complement (inverse) of the past output instead of being undefined as in
the SR flip-flop.

PART 2 Q2 ANSWER:

a) 111010.0012

b) 01001011.00102

PART 2 Q3 ANSWER:

a)

− It is much denser (can store many bits per chip),

− Uses less power,
− Less expensive,
− Generates less heat than SRAM.

b) SRAM is faster than DRAM.

PART 3 Q1 ANSWER:

a)

x y z 𝑥′ x’ . z y+z x'(y+z) x'.z+x’(y+z)

0 0 0 1 0 0 0 0
0 0 1 1 1 1 1 1
0 1 0 1 0 1 1 0
0 1 1 1 1 1 1 1
1 0 0 0 0 0 0 0
1 0 1 0 0 1 0 0
1 1 0 0 0 1 0 0
1 1 1 0 0 1 0 0
b)

SOP: x’y’z + x’yz

y'z’ y'z yz yz'

x' 0 1 1 0

x 0 0 0 0

Simplified F(x, y, z) = x’z

PART 3 Q2 ANSWER:

1- 16 bits / = 2 Bytes
2- 220 /24 = 216
3- Cache size = 32Kbit ⟶ 4KB

Number of blocks = 128

Size of a block = 4KB / 128 = 32 Bytes
Number of words in each cash = 32/2 = 16 words for each block.

4-
a-

9 7 4
Tag block word

20 bits

b-

11 5 4
Tag Set Word

20 bits
PART 3 Q3 ANSWER:

10A LOAD B
10B ADD B
10C SUBT C
10D SUBT C
10E ADD D
10F STORE A
110 HALT

111 A, DEC 3
112 B, DEC 6
113 C, DEC 5
114 D, DEC 7
‫الفصل األول ‪Fall 21-22‬‬
‫الفصل األول ‪Fall 20-21‬‬
 ‫‪400‬‬
‫‪200‬‬
‫‪800‬‬

‫‪300‬‬

‫‪100‬‬

‫‪400‬‬

‫‪200‬‬
‫‪300‬‬

‫تم إعادة كتابة األرقام لعدم وضوحها‬

PART 2 Q1 ANSWER:

Store X: stores the contents of AC into the memory location.

Halt: Terminates the program.

PART 2 Q2 ANSWER:

a. NAND & NOR

b.

PART 2 Q3 ANSWER:

a. 64 bits
b. 25 * 220 = 225

PART 2 Q4 ANSWER:

a. Skipcond 800
b. Add C40
c. Jump F6

PART 2 Q5 ANSWER:

a. (100011)2
b. (010001)2
c. (11010100)2

PART 3 Q1 ANSWER:

a. Signed magnitude: (10111010)2.

b. One's complement: (00111010)2 ⟶ (11000101) c1.
c. Two's complement: (11000101) c1 ⟶ (11000110) c2
PART 3 Q2 ANSWER:

Mode Value
Immediate 800
Direct 1300
Indirect 900
Indexed 600

PART 3 Q3 ANSWER:

a. (200)16
b. (1)10
c. Yes, because the condition of SKIPCOND is false.
d. (2)10

PART 3 Q4 ANSWER:

4 20 6 18
a. 2 * 2 / 2 = 2 blocks

b. Direct Mapped:

6
Word: 64 = 2 ⟶ 6 bits
3 10 13
Block: 2 * 2 = 2 ⟶ 13 bits
Tag: 24 - 6 - 13 = 5 bits

5 13 6
Tag block word

24 bits

c. Fully associative:
6
Word: 64 = 2 ⟶ 6 bits
Tag: 24 - 6 = 18 bits

18 6
Tag word

24 bits
PART 3 Q5 ANSWER:

a.

x y z 𝑦′ z’ y` + z` x(y` + z`) xyz xyz + x(y`+z`)

0 0 0 1 1 1 0 0 0
0 0 1 1 0 1 0 0 0
0 1 0 0 1 1 0 0 0
0 1 1 0 0 0 0 0 0
1 0 0 1 1 1 1 0 1
1 0 1 1 0 1 1 0 1
1 1 0 0 1 1 1 0 1
1 1 1 0 0 0 0 1 1

b. 𝑥𝑦′𝑧′ + 𝑥𝑦′𝑧 + 𝑥𝑦𝑧′ + 𝑥𝑦𝑧

c. Simplified F(x, y, z) = x

y'z’ y'z yz yz'

0
x' 0 0 0

x 1 1 0 1 1
‫الفصل األول ‪Fall 19-20‬‬
PART 2 Q1 ANSWER:

− Combinational circuits are memoryless; they do not have the concept of storage.
− Sequential logic circuits must have a memory to remember values and store previous inputs
and outputs.

PART 2 Q2 ANSWER:

Subt X:
MAR ⟵ X
MBR ⟵ M[MAR]
AC ⟵ AC - MBR

Load X:
MAR ⟵ X
MBR ⟵ M[MAR]
AC ⟵ MBR

PART 2 Q3 ANSWER:

a. Load B60
b. Halt
PART 2 Q4 ANSWER:

− A directive: is an instruction that is not supposed to be translated into machine code.

− Three directives: ORG, DEC, HEX

PART 2 Q5 ANSWER:

a. (01000101)2
b. (10101111)2

PART 3 Q1 ANSWER:

a. One's: (00101110)2 ⟶ -(46)10

b. Two's: 00101110 + 1 = (00101111)2 ⟶ -(47)10
c. Signed: -(1010001) = -(81)10

PART 3 Q2 ANSWER:

Mode Value
Immediate 600
Direct 300
Indirect 500
Indexed 800

PART 3 Q3 ANSWER:

a. 7 13 5
5 Tag Block Word
Word = 32 = 2 = 5 bits
3 10 13
Block = 8k = 2 * 2 = 2 = 13 bits 25 bits
Tag = 25 - 5 - 13 = 7 bits

20 5
b.
Tag Word
Word = 5 bits
Tag = 25 - 5 = 20 bits 25 bits

c.
Word = 5 bits 8 12 5
12 Tag Set Word
Set = 8K / 2 = 4K = 2 = 12 bits
Tag = 25 - 5 - 4 = 8 bits 25 bits
PART 3 Q4 ANSWER:

a.

𝑥 𝑦 𝑧 𝑥` 𝑦` 𝑧` 𝑥` . 𝑦` 𝑥 . 𝑦`. 𝑧` 𝑥` . 𝑦 𝑥` . 𝑦` + 𝑥𝑦`𝑧` + 𝑥`𝑦

0 0 0 1 1 1 1 0 0 1

0 0 1 1 1 0 1 0 0 1

0 1 0 1 0 1 0 0 1 1

0 1 1 1 0 0 0 0 1 1

1 0 0 0 1 1 0 1 0 1

1 0 1 0 1 0 0 0 0 0

1 1 0 0 0 1 0 0 0 0

1 1 1 0 0 0 0 0 0 0

b. Simplified F(x, y, z) = x' + y'z'

y'z’ y'z yz yz'

x' 1 1 0 1 1

x 1 0 0 0

PART 3 Q5 ANSWER:

20A LOAD D
20B ADD D
20C SUBT B
20D SUBT C
20E STORE A

20F A, DEC 2
210 B, DEC 0
211 C, DEC 3
212 D, DEC 4
Fall-Backup 19-20 ‫الفصل األول‬
PART 2 Q1 ANSWER:

a.
− No special tools are required for erasure.
− Erasure is performed by applying an electric field.

b.
− RAM is a read-write memory.
− RAM is volatile.

PART 2 Q2 ANSWER:

- (1.5)10 ⟶ (1.1)2 ⟶ 0.11 * 21

1 + 16 = 17

1 10001 11000000

PART 2 Q3 ANSWER:

Subt X:
MAR ⟵ X
MBR ⟵ M[MAR]
AC ⟵ AC - MBR

JumpI X:
MAR ⟵ X
MBR ⟵ M[MAR]
PC ⟵ MBR

PART 2 Q4 ANSWER: (Choose three)

− Binary, two's complement data representation.

− Stored program, fixed word length data and instructions.
− 4K x 16 word-addressable main memory.
− 16-bit instructions: 4 bits for the opcode, 12 bits for the address.
− A 16-bit arithmetic logic unit (ALU).
− Seven registers for control and data movement.
PART 2 Q5 ANSWER:

Characteristic table and the basic NOR-Gate representation:

PART 3 Q1 ANSWER:

a.

(-65)10 ⟶ (11000001)2
(-33)10 ⟶ (10100001)2

b.
1

1 | 1000001 +
1 | 0100001
-----------------
1 1100010 ⟶ (-98)10

PART 3 Q2 ANSWER:

5 20 6 19
a. 2 * 2 / 2 = 2 blocks

b. Direct Mapped Cache: 4 15 6

6 Tag Block Word
− Word: 64 = 2 = 6 bits
5 10 15
− Block: 32K = 2 * 2 = 2 = 15 bits 25 bits
− Tag: 25 - 15 - 6 = 4 bits

19 6
c. Fully associative: Tag word
6
− Word: 64 = 2 = 6 bits
− Tag: 25 - 6 = 19 bits 25 bits
PART 3 Q3 ANSWER:

Value in AC after Value in AC after

Mode
Add 300 Subt 100
Immediate 900 800
Direct 800 400

Indirect 1300 1200

Indexed 1300 1200

PART 3 Q4 ANSWER:

AC x y z Input Output

Initial Value 0 10 5 2 X X

Load x 10 10 5 2 X X

Store z 10 10 5 10 X X

Add y 15 10 5 10 X X

Output 15 10 5 10 X 15

Input 3 10 5 10 3 X
‫الفصل الصيفي ‪Summer 18-19‬‬
PART 2 Q1 ANSWER:

a.
− It's cheaper.
− It generates less heat.

b.

− EEPROM: Electrical Erasable Programmable Random-Access Memory

− IEEE: the Institution of Electrical and Electronic Engineer.

PART 2 Q2 ANSWER:

Because JK Flip-flops provide a stable state when both inputs are 1.

PART 2 Q3 ANSWER:

a. (146)8 = (001 100 110)2

b. (5BD)16 = (0101 1011 1101)2

PART 2 Q4 ANSWER:

Load X:
MAR ⟵ X
MBR ⟵ M[MAR]
AC ⟵ MBR

Add X:
MAR ⟵ X
MBR ⟵ M[MAR]
AC ⟵ AC + MBR
PART 2 Q5 ANSWER:

a. Jump 4C0
b. Input

PART 3 Q1 ANSWER:

a.

(10100111) = -(0100111) = -(39)10

(11100100) = -(1100100) = -(100)10

b.

1 1 1

1|0100111
1|1100100
----------------------
1 1 00 01011

c. There's an overflow.

PART 3 Q2 ANSWER:

Mode Value
Immediate 1000
Direct 1200
Indirect 1100
Indexed 1100

PART 3 Q3 ANSWER:

20
a. 64M / 64 = M = 2 blocks

b.
6
− Word: 64 = 2 = 6 bits 7 13 6
3 10 Tag Block Word
− Block: 8K = 2 * 2 = 13 bits
− Tag: 26 - 6 - 13 = 7 bits 26 bits
c.
6
− Word: 64 = 2 = 6 bits 10 10 6
10 Tag Set Word
− Set: 8K / 8 = K = 2 = 10 bits
− Tag: 26 - 6 - 10 = 10 bits 26 bits

PART 3 Q4 ANSWER:

a.

𝑥 𝑦 𝑧 𝑥` 𝑦` 𝑧` 𝑥` . 𝑦` 𝑦 + 𝑧` 𝑥` . ( 𝑦 + 𝑧`) 𝑥` . 𝑦` + 𝑥`(𝑦 + 𝑧`)

0 0 0 1 1 1 1 1 1 1
0 0 1 1 1 0 1 0 0 1
0 1 0 1 0 1 0 1 1 1
0 1 1 1 0 0 0 1 1 1
1 0 0 0 1 1 0 1 0 0
1 0 1 0 1 0 0 0 0 0
1 1 0 0 0 1 0 1 0 0
1 1 1 0 0 0 0 1 0 0

b. Simplified F(x, y, z) = x`

y'z’ y'z yz yz'

x' 1 1 0 1 1

x 0 0 0 0

PART 3 Q5 ANSWER:

a. (2110)16

b. Store Y

c. (110E)16

d. EndIf

e. ADD X
‫الفصل الثاني ‪Spring 18-19‬‬
PART 2 Q1 ANSWER:

a. A bus: is a group of wires that moves data and instructions to various places within a
computer.
b. Data lines, control lines, address lines.

PART 2 Q2 ANSWER:

− EEPROM: Electrical Erasable Programmable Random-Access Memory

− USB: Universal Serial Bus
− ALU: Arithmetic-Logic Unit

PART 2 Q3 ANSWER:

a) a′. b′. c′ + a′. b′. c + a. b. c + a. b. c′

b) F(a, b, c) = a. b + a′. c′ + b. c′

PART 2 Q4 ANSWER:

− AND, OR, NOT

− Truth Tables:

PART 2 Q5 ANSWER:

a. Jump 420
b. Output
PART 3 Q1 ANSWER:

a.
(-38) = -(00100110)2 ⟶ (11011001) c1
(-68) = -(01000100)2 ⟶ (10111011) c1
b.

1 1 1 1 1 1 1

11011001
10111011
---------------------
10010100
+
1
---------------------
(1 0 0 1 0 1 0 1) c1 = -(01101010)2 ⟶ -(106)10

c. It's correct; the carry-in and the carry-out are the same.

PART 3 Q2 ANSWER:

Value in AC after Value in AC after

Mode
Add 400 Store 200
Immediate 1000 1000
Direct 900 900

Indirect 1200 1200

Indexed 1000 1000

PART 3 Q3 ANSWER:

27
a. 2 bytes
15
b. 2 blocks
27 6 21
c. 2 / 2 = 2

d.
6 10 11 6
− Word = 2 = 6 bits
15 4 Tag Set Word
− Set = 2 / 2 = 11 bits
− Tag = 27 - 6 - 11 = 10 bits 27 bits
PART 3 Q4 ANSWER:

a.

𝑥 𝑦 𝑧 𝑥` 𝑦` 𝑧` 𝑦` . 𝑧` 𝑥` + 𝑧` 𝑦 . ( 𝑥` + 𝑧`) 𝑦` . 𝑧` + 𝑦(𝑥` + 𝑧`)

0 0 0 1 1 1 1 1 0 1
0 0 1 1 1 0 0 1 0 0
0 1 0 1 0 1 0 1 1 1
0 1 1 1 0 0 0 1 1 1
1 0 0 0 1 1 1 1 0 1
1 0 1 0 1 0 0 0 0 0
1 1 0 0 0 1 0 1 1 1
1 1 1 0 0 0 0 0 0 0

b. Simplified F(x, y, z) = x′. y + z′

y`z` y`z yz yz`

x` 1 0 1 1

1 1
x 0 0

PART 3 Q5 ANSWER:

a.

INPUT
STORE X
INPUT
STORE Y
JUMP End
LOAD X
End, OUTPUT
HALT

X, DEC 0
Y, DEC 0

b. 6
‫الفصل األول ‪Fall 18-19‬‬
PART 2 Q1 ANSWER:

− (0.25)10 ⟶ (0.01)2
-1
− normalizing: 0.1 * 2
− bias of 16: -1 + 16 = 15
− Answer:
0 01111 10000000

PART 2 Q2 ANSWER:

a.
− It is programmable and reprogrammable.
− Erasing requires a special tool that emits ultraviolet light.

b.
− It's cheaper.
− It uses less power.

PART 2 Q3 ANSWER:

Subt X:
MAR ⟵ X
MBR ⟵ M[MAR]
AC ⟵ AC - MBR

Output:
OutREG ⟵ AC

PART 2 Q4 ANSWER:

a. Store B20
b. Jump C40

PART 2 Q5 ANSWER:

Characteristic table and the basic NOR-Gate representation:

PART 3 Q1 ANSWER:

a.

(65)10 ⟶ (01000001)2
(97)10 ⟶ (01100001)2

b.

1 1

0 | 1000001 +
0 | 1100001
--------------------
0 1100010 ⟶ (98)10

which is erroneous.

c. It's incorrect; the addition overflows.

The correct result is (162)10

PART 3 Q2 ANSWER:

20
a. 32M / 32 = M = 2 blocks

b. Direct mapping:

5
− Word: 32 = 2 = 5 bits 5 15 5
15 Tag Block Word
− Block: 32K = 2 = 15 bits
− Tag: 25 - 5 - 15 = 5 bits 25 bits

c. Fully-Associative:
20 5
5 Tag word
− Word: 32 = 2 = 5 bits
− Tag: 25 - 5 = 20 bits 25 bits
PART 3 Q3 ANSWER:

Value in AC after Value in AC after

Mode
Load 300 Subt 100
Immediate 300 200

Direct 600 400

Indirect 400 000

Indexed 100 -500

PART 3 Q4 ANSWER:

a. (2110)16

b. Skipcond 800

c. (9108)16

d. Halt

e. Z
‫الفصل الثاني ‪Spring 17-18‬‬
PART 2 Q1 ANSWER:

a. Feedback in digital circuits occurs when an output is looped back to the input.
Combinational circuits rely on feedback to remember a past state.

b. Because it's stable for all inputs.

PART 2 Q2 ANSWER:

a. NAND, NOR

b.
− Complex integrated circuits are often much easier to build using the same building block.
− Universal gates are cheaper to build than other gates.

c.

PART 2 Q3 ANSWER:

Subt X:
MAR ⟵ X
MBR ⟵ M[MAR]
AC ⟵ AC - MBR

Jump X:
PC ⟵ X

PART 2 Q4 ANSWER:

a. Store B60
b. Jump 040
PART 2 Q5 ANSWER:

Characteristic table and the basic NOR-Gate representation:

PART 2 Q6 ANSWER:

a. (67)10 ⟶ (01000011)2
b. (171)10 ⟶ (10101011)2

PART 3 Q1 ANSWER:

a.
(-108)10 ⟶ -(01101100)2 ⟶ (10010011)c1 ⟶ (10010100)c2
(-18)10 ⟶ -(00010010)2 ⟶ (11101101)c1 ⟶ (11101110)c2

b. After complementing the negative operands, we perform regular addition, then we discard
the carry-out if it happens at the last bit.

c.

1 11111

10010100 +
11101110
-----------------
10000010 ⟶ -(01111101) + 1 = -(01111110)2 = (-126)10
PART 3 Q2 ANSWER:

Mode Value
Immediate 900
Direct 600
Indirect 800
Indexed 1100

PART 3 Q3 ANSWER:

a.

𝑥 𝑦 𝑧 𝑥` 𝑦` 𝑧` 𝑥` . 𝑦` 𝑥 . 𝑦`. 𝑧` 𝑥` . 𝑦 𝑥` . 𝑦` + 𝑥𝑦`𝑧` + 𝑥`𝑦

0 0 0 1 1 1 1 0 0 1
0 0 1 1 1 0 1 0 0 1
0 1 0 1 0 1 0 0 1 1
0 1 1 1 0 0 0 0 1 1
1 0 0 0 1 1 0 1 0 1
1 0 1 0 1 0 0 0 0 0
1 1 0 0 0 1 0 0 0 0
1 1 1 0 0 0 0 0 0 0

b. Simplified F(x, y, z) = x′ + y′z′

y'z’ y'z yz yz'

x' 1 1 0 1 1

x 1 0 0 0
PART 3 Q4 ANSWER:

10A LOAD B
10B ADD B
10C SUBT D
10D ADD C
10E STORE B

10F B, DEC 3
110 C, DEC 9
111 D, DEC 4
112 E, DEC 2

PART 3 Q5 ANSWER:

a. Direct mapping:

− Word: 64 = 26 = 6 bits
− Block: 4K = 22 * 210 = 12 bits
− Tag: 25 - 6 - 12 = 7 bits

7 12 6
Tag block word

25 bits

b. Fully Associative mapping:

− Word: 64 = 26 = 6 bits
− Tag: 25 - 6 = 19 bits

19 6
Tag word

25 bits

c. 8-way set Associative mapping:

− Word: 64 = 26 = 6 bits
− Set: 4K / 8 = 29 = 9 bits
− Tag: 25 - 6 - 9 = 10 bits

10 9 6
Tag Set Word

25 bits
‫الفصل األول ‪Fall 17-18‬‬
PART 2 Q1 ANSWER:

a. They hold data that can be readily accessed by the CPU.

b. General purpose, special purpose

c. If the number of inputs is (2𝑛 ), then (n) selectors are needed.

PART 2 Q2 ANSWER:

− Combinational circuits are memoryless; they do not have the concept of storage.
− Sequential logic circuits must have a memory to remember values and store previous inputs
and outputs.
PART 2 Q3 ANSWER:

Store X:
MAR ⟵ X
MBR ⟵ AC
M[MAR] ⟵ MBR

Add X:
MAR ⟵ X
MBR ⟵ M[MAR]
AC ⟵ AC + MBR

PART 2 Q4 ANSWER:

a. Add 710
b. Jump 200

PART 2 Q5 ANSWER:

PART 2 Q6 ANSWER:

a. (57)10 ⟶ (00111001)2
b. (175)10 ⟶ (10101111)2

PART 3 Q1 ANSWER:

a. - (00101111)2 ⟶ (-47)10
b. - (00110000)2 ⟶ (-48)10
c. - (1010000)2 ⟶ (-80)10
PART 3 Q2 ANSWER:

Mode Value
Immediate 200
Direct 700
Indirect 400
Indexed 200

PART 3 Q3 ANSWER:

11A LOAD C
11B SUBT D
11C ADD E
11D ADD E
11E STORE B

11F B, DEC 0
120 C, DEC 6
121 D, DEC 4
122 E, DEC 2

PART 3 Q4 ANSWER:

a.

𝑥 𝑦 𝑧 𝑥` 𝑦` 𝑧` 𝑥`. 𝑦`. 𝑧` 𝑥 . 𝑦`. 𝑧` 𝑥` . 𝑦`. 𝑧 𝑥 . 𝑦`. 𝑧 𝑥`. 𝑦`. 𝑧` + 𝑥. 𝑦`. 𝑧` + 𝑥`. 𝑦`. 𝑧 + 𝑥. 𝑦`. 𝑧

0 0 0 1 1 1 1 0 0 0 1
0 0 1 1 1 0 0 0 1 0 1
0 1 0 1 0 1 0 0 0 0 0
0 1 1 1 0 0 0 0 0 0 0
1 0 0 0 1 1 0 1 0 0 1
1 0 1 0 1 0 0 0 0 1 1
1 1 0 0 0 1 0 0 0 0 0
1 1 1 0 0 0 0 0 0 0 0

b. Simplified F(x, y, z) = y′

y'z’ y'z yz yz'

x' 1 1 0 0
1
x 1 0 0
Scan or Click me.