Table of contents

• Basic knowledge
o CP and FT
o What test engineers need to consider
o What is DFT?
• Fault Model
o Fault class hierarchy
• DFT Methods
o Ad-hoc
o Scan:
o Logical BIST
o Boundary Scan
• DFT-Scan
o D algorithm
o Scannable Equivalent Filp-Flop
• ATPG
• MBIST
o Memory type
o Memory Defects
o MBIST algorithm
o The basic architecture of MBIST
 BASIC KNOWLEDGE
1. CP and FT

• CP is the abbreviation of (Chip Probe), which refers to the fact that when
the chip is in the wafer (wafer) stage, the performance and function of the
chip are tested through probes stuck on the chip pins. Sometimes this
process is also called WS (Wafer Sort)
• FT is the abbreviation of Final Test, which refers to the final testing of the
chip after the packaging is completed. Only chips that pass the test will
be shipped, and the detailed testing is carried out.

Under what circumstances is CP required?

• Because the packaging itself may affect the yield and characteristics of
the chip, all measurable test items of the chip must be tested in the FT
stage. The CP stage is optional.
• Since the test accuracy in the CP stage is often not accurate enough, the
test judgment criteria can be appropriately relaxed and only preliminary
screening is done. Fine and rigorous testing can be placed in the FT stage.
• If the packaging cost is not large and the chip itself has a relatively high
yield, you can consider not doing CP testing, or only doing sampling
testing and supervising the process during the CP stage.
• When a new product is introduced into mass production, the
development and core introduction of the FT test program should be
completed first. In the early stage of product mass production, FT is far
more important than CP. After the product gradually goes into volume,
CP can be formulated and developed based on the actual situation of FT
test.
2. What test engineers need to consider?

• Reduce testing costs:

• Starting from test planning, consider chip performance requirements,
ATE, Load Board, etc., and reduce costs by reducing chain length, testing
logic instance number.
• ATPG efficiency.
• Choose appropriate test vectors.

3. What is DFT?

DFT = Design-for-Testability

• extra pin.
• Will insert testing logic.
DFT cost:

• Area cost.
• Affect performance.
• ATPG tool cost and pattern debug cost.
• ATE testing cost.

How to reduce DFT cost:

• Reasonable test plan, such as reducing chain length, memory

concurrent testing.
• Reduce the number of patterns.
• Increase test frequency.
 FAULT MODEL
physical fault:

• IO leakage or short
• net open
• material pollution

Logic fault:

• signal hard fault

• delay fault
• static current fault

Fault model is to build a bridge between physical fault and logical fault, or it is
a logical model that reflects the impact of physical fault.
For example, the following SA fault (static fault):

Pin A may be physically short-circuited to ground, so it is equivalent to setting

it to a static 0 when modeling.
Transition fault mainly examines speed and timing

STR: slow to rise

STF: slow to fall
Path delay fault: It is also reflected in speed and timing. It examines whether
the delay on the entire path has timed out, usually the critical path.

IDDQ: Test the total current of the CMOS circuit in static state.

• In the static state, CMOS only has leakage current or diode reverse
current.
• Any open circuit or short circuit will cause the total current to be different
from the normal, resulting in IDDQ variation

Fault class hierarchy

• DT-Detected
• PT - Possibly detected
• UD - Undetectable
• AU - ATPG untestable
• ND - Not detected
 DFT METHODS
Ad-hoc (function point testing)
Structured (structured testing):

• Scan
• Built-in self-test (BIST)
• Memory
• Logic
• Boundary scan

Ad-hoc

Add testable logic where designers care:

• Add controllable nodes and observation nodes.

• Break down large circuits into small test blocks.

For example, add a scan point in front of the ROM below to see whether the
data entering the ROM is incorrect.
.
shortcoming:

Scan:
Replace the DFF with a DFF with scan mode and string them together to form a
scan chain.
Logical BIST
BIST = Build in self-test

Put the work of ATE (automatic test machine) (Test data generation, test
response evaluation) on the chip.

In addition, the internal data of the system can be protected. Because there is
no external control and observation, the information of internal nodes cannot
be obtained.

shortcoming:

• Expensive
• Lower fault coverage, higher test time
• Debugging is difficult, I only know that something is wrong, but I don’t
know where it is.
Commonly used in chips that do not require many pins (relatively few pins) and
have security issues, such as bus card chips.
Boundary Scan
Test multi-chip interconnects. Test board-level manufacturing process errors,
including using wrong components, wrong pin short circuits, open circuits, etc.

• It has an independent subsystem (independent clock).

• Only 5 pins are needed: TDI, TDO, TMS, TCK, TRST (can be omitted) (JTAG)
• The interconnection of multiple chips can be tested by connecting the
TDO and TDI of multiple chips in series.
Basic JTAG:

For example, through TAP mode selection, the authentication of the device is
detected to verify whether it is the correct chip.
 DFT-SCAN
D algorithm:

• Select a specific fault point (guess where there is a fault).

• Enter the driving value to ensure that the theoretical value generated
when the value reaches the fault point is opposite to the fault.
• Propagate the fault value to the nearest output point
• Record test graphics and report faults.

Example: The output of the U1 unit below is suspected to have a static fault
(short circuit to ground).
 • First, give 0 to the input of U1. If there is no problem with U1, the output
should be 1 (green, indicating no fault), otherwise, output 0 (red,
indicating static 0 fault)
• The inputs of other pins need to be coordinated so that the final output
pin can reflect the value of U1. In this way, the fault of U1 is moved to the
output pin. By judging the output value, you can determine whether there
is a problem with U1.

For this example, there are the following concepts:

1. Input Stimulus: test stimulus, here refers to 1000
2. Expected response: expected response, here refers to the output value
when there is no fault, which is 1
3. Test Vector: Test vector, that is, the above two combined together 10001
4. Test pattern: Test pattern, one or more test vector sequences
constructed to detect a target fault.

In fact, we don't know whether there is a problem with U1. Even if the final
output reports a fault, we cannot be sure whether U1 is wrong. Therefore, when
doing it, it will be iterated multiple times, and the range of fault points will be
gradually reduced according to different test incentives until the fault point is
found.
Advantages and disadvantages of D-algorithm:

advantage:

• Deterministic: determined, done step by step

• Exhaustive: Exhaustive, until the test is completed or there is an
undetectable fault
shortcoming:

• Only one fault can be tested at a time

• Make decisions at every step

For some hard-to-detect faults, multiple iterations of testing may be required.

Note: Some fault points cannot be detected, such as redundant logic.
practice:

Scannable Equivalent Filp-Flop

The above method is to test combinational logic, but to test sequential logic,
you need to replace the DFF:
All replaced DFFs are then strung together to form a chain.

Purpose: To facilitate filling test stimuli into any DFF.

method:

• SE selects the SI terminal and moves the test stimulus to the register
through the SI terminal through scan shift.
• SE selects the D terminal and lets the register capture data
• SE selects the SI terminal, continues shifting, and outputs the result of
the point to be measured to the output pin.
• Continue Capture...

Example:

To test the fault of the marked point, a test stimulus of 1000 is needed. First,
the data is entered into the corresponding register through the SI terminal,
and then the fault result is captured, and then the shift is continued. After a
few cycles, all DFF's capture value is exported from PO, and the fault result
can be determined.
 ATPG
Automatic test pattern generation. Chip testing requires patterns, and
manually designing patterns is very time-consuming.

Main Tools: Tetramax , Tessent, Encouter Test.

ATPG flow:

• Read design
• Build design
• DRC
• Prepare for ATPG
• Run ATPG
• Save patterns and faults

Memory is handed over to BIST during testing. It is a black box, but the
observability near the Memory block is very low. How to solve it?

• Add bypass logic, (mem input to output plus DFF).

• Use TetraMax Model (model memory).
 MBIST
Why do MBIST?

• Memory accounts for an increasing proportion of current chips. (80%-

90% Today)
• mem is very sensitive to process fluctuations
• Currently, many embedded mems have built-in redundancy
(redundancy logic), which can replace some failed mem areas, and the
failed areas require BIST to detect
Memory type

• SRAM
• DRAM
• CAM
• ROM
• FLASH

MBIST generally only targets SRAM, DRAM, and ROM

Memory Defects

• Address decoding logic

• Read and write control logic
• memory cell

Similarly, memory faults also include stuck-at fault (clamped at a fixed level)
and transition fault. In addition, mem also has Coupling Fault
Coupling Fault:

• Inversion Coupling Faults (CFin)

A jump on one cell causes another cell to jump in the opposite direction.

• Idempotent Coupling Faults

Like the above, it just causes another cell to jump to a fixed value.

• Bridge Coupling Faults (BF)

There is a bridge between internal cells. The effect is that the two cells appear
to be OR or AND.

• Neighborhood Pattern Sensitive faults

MBIST algorithm

• Address Decoder Algorithm

• March Algorithm
• Checkerboard Algorithm
The basic architecture of MBIST