Physics Practiacl 6th Sem
Physics Practiacl 6th Sem
Aim: - To Verify truth tables of AND, OR, NOT, NOR, NAND, XOR, XNOR gates.
Apparatus Required: -
1.All the basic gates mention in the fig
2.IC Trainer Kit
Procedure: -
Kit.
Disconnect output from the LEDs and note down the corresponding
A O/P
0 1
1 0
2-Input AND Gate 7408LS
A B O/P
0 0 0
0 1 0
1 0 0
1 1 1
A B O/P
0 0 0
0 1 1
1 0 1
1 1 1
A B O/P
0 0 1
0 1 1
1 0 1
1 1 0
2-Input NOR Gate 7402LS
A B O/P
0 0 1
0 1 0
1 0 0
1 1 0
A B O/P
0 0 0
0 1 1
1 0 1
1 1 0
0 1 0
1 0 0
1 1 1
Conclusion:-
Truth table of logic gates are verified.
Aim: - Implementation of various gates by using universal properties of NAND & NOR gates
and
Verify truth table.
APPARATUS REQUIRED
THEORY:
NAND OR NOR gates are sufficient for the realization of any logic expression. because of
this reason, NAND and NOR gates are known as UNIVERSAL gates.
PROCEDURE:
A B AB
0 0 0
0 1 0
1 0 0
1 1 1
A B A+B
0 0 0
0 1 1
1 0 1
1 1 1
A B
0 0 1
0 1 0
1 0 0
1 1 0
A B A⊕B
0 0 0
0 1 1
1 0 1
1 1 0
A B AʘB
0 0 1
0 1 0
1 0 0
1 1 1
2.For NOR gate as universal gate
PROCEDURE:
A Ā
0 1
1 0
A B A+B
0 0 0
0 1 1
1 0 1
1 1 1
A B AB
0 0 0
0 1 0
1 0 0
1 1 1
A B AB
0 0 1
0 1 1
1 0 1
1 1 0
A B A⊕B
0 0 0
0 1 1
1 0 1
1 1 0
A B AʘB
0 0 1
0 1 0
1 0 0
1 1 1
Conclusion:-
We have constructed and verified truth table of all gates using universal gates NAND and NOR gate.
Aim: - Implementation of half adder and Full adder using logic gates.
APPARATUS REQUIRED
THEORY:
Half-Adder: A combinational logic circuit that performs the addition of two data bits, A and B, is
called a half-adder. Addition will result in two output bits; one of which is the sum bit, S, and the
other is the carry bit, C. The Boolean functions describing the half-adder are:
S =A ⊕ B C=AB
Full-Adder: The half-adder does not take the carry bit from its previous stage into account. This
carry bit from its previous stage is called carry-in bit. A combinational logic circuit that adds two
data bits, A and B, and a carry-in bit, Cin, is called a full-adder. The Boolean functions describing
the full-adder are:
S = (x ⊕ y) ⊕ Cin C = xy + Cin (x ⊕ y)
0 0
0 1
1 0
1 1
Cin
Half adder and full adder are constructed and their truth tables are verified.
Aim: - Implementation of half subtractor and Full subtractor using logic gates.
APPARATUS REQUIRED
THEORY:
Half Subtractor: Subtracting a single-bit binary value B from another A (i.e. A -B) produces a
difference bit D and a borrow out bit B-out. This operation is called half subtraction and the circuit
to realize it is called a half subtractor. The Boolean functions describing the halfSubtractor are:
D =A ⊕ B Br = Α̅ B
Full Subtractor: Subtracting two single-bit binary values, B, Cin from a single-bit value A produces a
difference bit D and a borrow out Br bit. This is called full subtraction. The Boolean functions
describing the full-subtracter are:
Half subtractor and full subtractor are constructed and their truth tables are verified.