CIE 2 MSD Scheme & Solutions

27th May 2024

1. Determine the best way of generating the bias voltage VB in the circuit of Fig. 1. Also demonstrate
that one threshold voltage is wasted in the voltage headroom at the output. 05

VDD
VOUT
IREF IOUT
VB M3
X Y
M1 M2

Fig. 1: Question 1

Solution:
Figure 1 shows the basic idea of a cascode current mirror. If the voltages at nodes X and Y are made
same by choosing an appropriate bias voltage VB , then the currents IREF and IOUT are well-matched even
in the presence of channel length modulation. Assume that all transistors are identical and that all are
biased in saturation. Recall that for a transistor to be in saturation, VGS ≥ VT +VDS,sat and VDS ≥ VDS,sat .
We want: VY = VX = VT +VDS,sat
Then, VB = VY +VGS3
∴ VB = 2VT + 2VDS,sat
VDD

IREF VOUT

IOUT
P
M0 M3
X Y
M1 M2

Figure 1: Cascode Current Mirror

Observe that a voltage of VT + VDS,sat is set-up across the drain-source terminals of transistor M1 in
Figure 1. By the same logic, the voltage VB can be derived by stacking another diode-connected transistor
on top of M1 , as shown in Figure 1. The lengths of transistors M0 and M3 must be kept same for good
current matching between them. (4)

1
 ..............................................................................................
The output swing for the cascode current mirror is given by:
Vout,min = VY +VDS3,sat = VT + 2VDS,sat
It is to be noted that if the output voltage goes below the value calculated, then the transistors will no
longer be in saturation; in which case the output current will not track the reference current. For a
stacking of two transistors, 2VDS,sat should be enough for maintaining them in saturation, but here an
additional threshold voltage is needed for the same. (1)

2. Demonstrate, with the help of a neat circuit diagram, the need for two-stage operational amplifiers
in achieving high gain and high output swing. 05
Solution:
One-stage opamps allow the small-signal current produced by the input pair to flow directly through
the output impedance. The gain of these topologies is therefore limited to the product of the input pair
transconductance and the output impedance. Cascoding in such circuits increases the gain while limiting
the output swings.
In some applications, the gain and/or the output swings provided by cascode op amps are not adequate.
In such cases, “two-stage” op amps are employed, with the first stage providing a high gain and the
second, large swings (Figure 2). In contrast to cascode op amps, a two-stage configuration isolates the
gain and swing requirements. Each stage in Figure 2 can incorporate different topologies, but the second
stage is typically configured as a simple common-source stage so as to allow maximum output swings.

(4)
Figure 2: Cascode op amps with single-ended output
..............................................................................................
Figure 3 shows an example, where the first and second stages exhibit gains equal to gm1,2 (ro1,2 ||ro3,4 )
and gm5,6 (ro5,6 ||ro7,8 ) respectively. The overall gain is therefore comparable with that of a cascode op
amp, but the swing at Vout1 and Vout2 is equal is to VDD −|VOD5,6 |−VOD7,8 . The first stage can incorporate
cascode devices to obtain higher gain. (1)

Figure 3: Simple implementation of a two-stage op amp

2
 VDD

M3 M4
vout

M1 M2
vin

IBIAS

Fig. 2: Question 3

3. For the circuit of Fig. 2, given IBIAS = 100 µA and all transistors have W /L = 100/2, VT = 0.7 V
and λ = 0.08 V−1 . Find the differential gain if µnCox = 100 µA/V2 . 05
Solution:
The differential gain is given by: Ad = gm1,2 (ro2 || ro4 ). (2)
..............................................................................................
Since IBIAS = 100 µA, a current of 50 µA flows in each branch.
r r
W 100
gm1,2 = 2µnCox ID1,2 = 2 × 100µ × × 50µ = 0.707 mS
L 2
1 1
ro2 = ro4 = = = 250 kΩ
λ ID 0.08 × 50µ
250 kΩ
∴ Ad = gm1,2 (ro2 || ro4 ) = 0.707 mS × = 88.375 or 38.93 dB (3)
2

4. Analyze the large signal behavior of an OTA using 5 transistor realization. 05

Solution:
VDD

M3 M4
F vout

vin1 M1 M2 vin2
P

VB M5

(2)
Figure 4: 5 transistor OTA Figure 5: Large Signal Input-Output Characteristic
..............................................................................................
In Figure 4, when Vin1 is much more negative than Vin2 , M1 is OFF and so are M3 and M4 . Since no
current can flow from VDD , both M2 and M5 operate in deep triode region, carrying zero current. Hence,
Vout = 0.
As Vin1 approaches Vin2 , M1 turns ON, drawing part of ID5 through M3 and thereby turning ON M4 also.
The output voltage then depends on the difference between ID4 and ID2 . When Vin1 and Vin2 are nearly
equal, both M2 and M4 are in saturation, providing high gain.

3
 As Vin1 becomes more positive than Vin2 , ID1 increases leading to an increase in |ID3 | and |ID4 | but ID2
decreases; eventually driving M4 into the triode region. If Vin1 −Vin2 is sufficiently large, M2 turns OFF
and M4 operates in deep triode region with zero current. Hence, Vout = VDD . These are demonstrated in
Figure 5. (3)

5. Analyze the circuit of Fig. 3, assuming the Op-Amp is a single pole voltage amplifier. If Vin is a
small step, calculate the time required for the output voltage to reach within 5% of its final value.
Determine the minimum unity-gain bandwidth of the Op-Amp if (1 + R1 /R2 ) ≈ 5 and the 5%-
settling time is to be less than 5 ns. 10

Fig. 3: Question 5

Solution:
Since  
R2
Vin −Vout A(s) = Vout ,
R1 + R2
we have
Vout A(s)
(s) =
Vin 1 + R1R+R
2
2
A(s)
For a one-pole system, A(s) is given by
A0
A(s) =
1 + s/ω0
where ω0 is the 3-dB bandwidth, A0 is the DC gain and A0 ω0 is the unity-gain bandwidth or the gain-
bandwidth product. Thus
  
Vout A0 R2 A0 A0
(s) = 1+ · = R
Vin 1 + s/ω0 R1 + R2 1 + s/ω0 2
1 + R1 +R 2
A0 + ωs0
( )  
A0  s 
= 1 +
1 + R1R+R
 
1 + R1R+R
2
2
A0  2
A0 ω0 
2

Comparing the above two equations, we find that the closed-loop amplifier is also a one-pole system
with a time constant (reciprocal of pole frequency) equal to
   
1 R1 + R2 1 R1 1
τ=  ≈ = 1+
1 + R2 A ω R2 A0 ω0 R2 A0 ω0
R1 +R2 0 0

The output step response for Vin = au(t) can be expressed as

  
R1 −t
Vout (t) ≈ a 1 + 1 − exp u(t)
R2 τ
with the final value VF ≈ a(1 + R1 /R2 ). (5)

4
 For 5% settling, Vout = 0.95VF and hence
−t5%
1 − exp = 0.95 yielding t5% = τ ln(20) ≈ 3τ (2)
τ
For a 5% settling of 5 ns, τ ≈ 5/3 = 1.667 ns and
 
R1 1 5
A0 ω0 = 1 + = = 3 Grad/s (477.5 MHz) (3)
R2 τ 1.667 × 10−9

6. Design a fully differential telescopic Op-Amp with the following specifications: VDD = 3 V, differen-
tial output swing = 3 V, power dissipation = 9 mW, voltage gain = 1200. Assume µnCox = 60 µA/V2 ,
µ pCox = 30 µA/V2 , λn = 0.1 V−1 , λ p = 0.2 V−1 (for an effective channel length of 0.5 µm), γ = 0
and threshold voltages VT n = |VT p | = 0.6 V. 10
Solution:

Figure 6: Telescopic Cascode Op Amp Topology

(2)
..............................................................................................
Figure 6 shows the op amp topology along with two current mirrors defining the drain currents of M7 -
M9 . The design of the telescopic cascode is generally done in the following steps.
Step 1: Determine the DC bias currents based on the power budget:
9 mW power budget from 3 V supply allows a total DC bias current of 3 mA. We may allocate 2.7 mA
to M9 and the remaining 300 µA to Mb1 and Mb2 . Thus, each cascode branch of the op amp carries a
current of 1.35 mA. (1)
..............................................................................................
Step 2: Consider the required output voltage swings:
Each of nodes X and Y must be able to swing by 1.5 V without driving M3 -M6 into the triode region.
With a 3 V supply, therefore, the total voltage available for M9 and each cascode branch is 1.5 V, i.e.,
|VOD7 | + |VOD5 | +VOD3 +VOD1 +VOD9 = 1.5 V
Since M9 carries the largest current, we choose VOD9 ≈ 0.5 V, leaving 1 V for the four transistors in the
cascode. Moreover, since M5 -M8 suffer from low mobility, we allocate an overdrive of 300 mV to each,
obtaining 400 mV for VOD1 +VOD3 . As an initial guess, VOD1 = VOD3 = 200 mV. (1)
..............................................................................................
Step 3: Determine the aspect ratios of transistors using the known bias current and overdrive voltage of
each transistor from the relation ID = (1/2)µCox (W /L)(VGS −VT H )2 (where VOD = VGS −VT H ):

5
Since overdrive voltages and bias currents for transistors M1 -M4 are 200 mV and 1.35 mA respectively,
we have
2ID 2 × 1.35 mA
(W /L)1−4 = = = 1125
µnCox (VOD ) 2
60 µA/V2 × (200 mV)2
Similarly for M5 -M8 , the overdrive voltages and bias currents are 300 mV and 1.35 mA respectively.
Therefore
2ID 2 × 1.35 mA
(W /L)5−8 = = = 1000
µ pCox (VOD )2 30 µA/V2 × (300 mV)2
For M9 , overdrive voltage is 500 mV and bias current is 2.7 mA. Hence
2ID 2 × 2.7 mA
(W /L)9 = = = 360 (3)
µnCox (VOD )2 60 µA/V2 × (500 mV)2
..............................................................................................
Step 4: Calculate the small-signal voltage gain p of the design thus obtained using
Av ≈ gm1 [(gm3 ro3 ro1 ) || (gm5 ro5 ro7 )], gm = 2µCox (W /L)ID and ro = 1/(λ ID ):
p 1
gm,1−4 = 2 × 60µ × 1125 × 1.35m = 13.5 mS; ro,1−4 = = 7.41 kΩ
0.1 × 1.35m
p 1
gm,5−8 = 2 × 30µ × 1000 × 1.35m = 9 mS; ro,5−8 = = 3.70 kΩ
0.2 × 1.35m
∴ Av ≈ 13.5m [741.26 kΩ || 123.21 kΩ] = 13.5m × 105.65 kΩ = 1426.3
Since this meets the target gain, the design is complete. (3)