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Clock Domain Crossing

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Ahmed Elgmmal
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35 views

Clock Domain Crossing

Uploaded by

Ahmed Elgmmal
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PDF, TXT or read online on Scribd
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Clock domain crossing

CDC
-clk1 and clk2 are asynchronous to
each other. When data generated
by a clock is captured by another
clock which is asynchronous to the
clock which generated the data, it is
called Clock Domain Crossing.
-NOTE: If 2 domains from same source (PLL) this is not considered CDC,
case being considered CDC when from 2different domain source.
-2 different domain is between edges unpredicted phase.

Metastability:
 The worst problems due to CDC, the output of a flip-flop can oscillate
between the logic high and logic low states instead of settling to a stable
logic level.
 Metastability can occur when a signal changes close to the edge of a
clock signal, it is considered it change in close to setup time or close to
hold time for this we try avoid violations in setup and hold time .
 In a metastable state, the output of the flip-flop is unpredictable and
can oscillate between the high and low logic levels. The duration of
metastability is unpredictable and can vary from a few nanoseconds to
an indefinite period, depending on various factors such as the signal
timing, noise, and the characteristics of the flip-flop.
As shown in the figure:
1. A, E: is met setup and hold, so settle
after hold.
2. B, D: is violated in setup and hold
respectively for this take
unpredictable time after hold to
settle. -------------------------------------------------------------------------------
Problems Due to Metastability:
 Dissipated Short circuit power between supply and
ground, CMOS transistors is somewhere mid-way
between 0 and 1.

 Propagate different values at the same


time, Assume F1 capture data from
asynchronous flipflop
- C1 =4ns
- C2=7ns
- Tclk=10ns
- Tcq|f1=4ns
F2 no violation and data settle before capture new edge.
F3 will violation in setup and data notable early and will capture
different data.
--------------------------------------------------------------------------------------
Avoid metastability:
-Multi-Flop Synchronizations this Technique used with single bit
(Enable signal /Mux selected /Ready-Ack handshaking)
-F1: Destination flop.
-F2: Synchronizing flop.
F1’s output could go metastable, F2’s
output will settle.
--------------------------------------------------------------------------------------------------
MTBF (Mean time between failures):
-If need more stable(less failures), need more MTBF.
-if need more MTBF, need more flops.
-if need more flops, need more cycles (increase latency).
- increasing in latency, increase MTBF, decrease Failure (more stable)

Data Incoherence:
Bus Synchronization: Bus means a set of signals like.
(Vectored data lines, address lines)
Note: if we need transfer data bus between 2 different domains it will
result garbage data because
- Difference in routing delays for different bits.
- Different bits are being captured by different flops, and, each flop might behave in its
own manner>> (metastability).

Different ways to solve this bus synchronization:


1. Grey encoding: depend on it change only single bit
it will synchronize single bit each cycle.

2. Enable signal:

3. Handshake
How to avoid data loss?
FIFO:
The generation of the Empty signal is
without any delay. However, due to the
delay on the write pointer side, the FIFO
might take an extra cycle to deassert the
Empty signal. So, effectively, the assertion
of full and Empty happens without any
delay. But, the deassertion might involve an extra cycle. This means, there
might be an additional wasted cycle; however, this additional wasted cycle
is worth it – to prevent any failure.
-Cases for calculated depth of FIFO:
Assume:
FA: Launch Flip Flop. FB: Capture Flip Flop.
1. Case 1: FA > FB (with no idle cycle)
2. Case 2: FA > FB (with idle cycle)
3. Case 3: FA < FB (with no idle cycle)
4. Case 4: FA < FB (with idle cycle)
5. Case 5: FA=FB (With no idle case)
6. Case 5: FA=FB (With idle case)
For solution:
1- Time for writing one data = 1/Freq * no.of idle cycles
2- Time for Reading one data = 1/Freq * no.of idle cycles
3- Time for writing length burst = time of write one data * length_burst (TWLB)
4- Time for reading length burst = time of read one data * length_burst (TRLB)
5- Depth of fifo = difference (TWLB-TRLB) / Time for Reading one data

NOTE: Idle cycle for transmit packet of data should wait n.of cycles (idle
cycles).
CDC Question
1. Define Setup & Hold Time?
2. What happens when we violate setup and hold time?
3. What’s CDC?
4. If we have the same clock that feeds two flops, can we have clock
domain crossing?
5. How do we solve the CDC problem?
6. What’s the main problem of a synchronizer when clk1 is faster
than clk2?
7. What are the methods we use if we want to transfer a bus from
domain to another domain?
8. . If we have 3 bits data that needs to be Clock domain crossed, and
apart from the three mentioned solution, suggest a solution to
transfer the bit
9. Why do we use gray encoding in CDC instead of binary encoding?
10. Draw the block diagram of the FIFO and explain how it
works
11. What’s is full condition for the FIFO? Write it and state the
clock of every variable in the equation?
12. What’s the case when we need to use a FIFO?
13. What’s the case when we should use a FIFO instead of gray
encoding?
14. If we don’t want to use handshaking, FIFO or gray encoding
what method should we do?

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