Synthesis Interview Questions

What is Synthesis?

What is a Moore machine? How is it different from a Mealy machine?

Assume that variable a is integer and b is natural. When are the following statements valid?

What modeling technique will decompose designs hierarchically?

Do variables need time queues?

Does simulation time advance during delta cycles?

Is it true that synthesis transformations take less time at the top abstraction levels?

Is it true that synthesis transformations give refined results at the top abstraction levels?

What will a well formed case statement synthesize to?

What will happen to a design that is synthesized without any constraints?

Explain what role the Synopsys DesignWare libraries fulfill in the synthesis process.

What is the difference between a high level synthesis tool (as represented by Synopsys behavioral
Compiler) versus a logic synthesis tool (as represented by Synopsys Design Compiler)?

Explain what it meant for Synopsys DesignWare component to be ‘inferred’ by a synthesis tool?

What are different power reduction techniques?

How do you perform Synthesis activities in Multi vt libraries?

What are the advantages of clock gating?

One circuit will be given to you, where one of the inputs X have a high toggling rate in the circuit. What
steps you take to reduce the power in that given circuit?

You will be told to realize a Boolean equation. The next question is how efficient usage of power is
achieved in that crcuit?

Some circuit will be given to you and will be instructed to set certain timing exceptions commands on
that particular path.
What is the difference in PT timing analysis during post and pre layout designs?

What you mean by FSM States?

Draw the timing waveforms for the circuit given?

What is Setup time and hold time effects on the circuit behavior while providing different situations?

What is the difference of constraints file in Pre layout and post layout?

What is SPEF? Have you used it? How you can use it?

What difference you found (or can find) in the netlist and your timing behavior, while performing timing
analysis in pre layout and post layout?

What is clock uncertainty, clock skew and clock jitter?

What is the reason for skew and jitter?

What is clock tree synthesis?

What are the timing related commands with respect to clock?

In front end, you set ideal network conditions on certain pins/clocks etc. Why? In Back end how is it
taken care?

Which library you have used?

What difference you (can) find in TSMC and IBM libraries?

Draw the LSSD cell structure in TSMC and IBM libraries?

Every tool has some drawbacks? What drawbacks you find in Prime time?

What are the difference you find when you switch from 130nm to 90nm?

Explain the basic ASIC design flow? Where your work starts from? What is your role?

What is 90nm technology means?

What are the issues you faced in your designs?

Perform the setup and hold check for the given circuit.

Why setup and hold required for a flop?

You had any timing buffer between synthesis and P&R? How much should be the margin?
What are the inputs for synthesis and timing analysis from RTL and P&R team? Whether any inputs for
changing the scripts?

How will you fix the setup and hold violation?

What are the constraints you used for the synthesis? Who decides the constraints?

What is uncertainty?

What is false path and multi cycle path? Give examples? For given example for false path what you will
do for timing analysis?

What strategies used for the power optimization for your recent project?

Why max and min capacitance required?

You have two different frequency for launch (say 75Mhz) and capture (say 100Mhz).

What will happen to data? Write the waveform? If hold problem what you will do?

What is Metastability? How to overcome metastability? If metastable condition exists which frequency
you will use as clock- faster or slower? Why?

Have you used formality? For a given block what checks it will do? How it verifies inside the block?

If you changed the port names during the synthesis how will you inform Formality?

Why you use power compiler? What is clock gating? What are advantage and disadvantages of clock
gating? Write the clock gating circuit? Explain.

How will you control the clock gating inference for block of register? Write the command for the same?

Write the total power equation? What is leakage power? Write equation for it.

For clock gated flop and non clock gated flop outputs connected to a AND gate what problem can you
expect? How to avoid the problem?

Write the sequence detector state which detects 10? How will optimize? write the verilog code for the
same?

What is jitter? Why it will come? How to consider? What is the command for that?

What is clock latency? How to specify? What is the command for that?

What is dynamic timing analysis? What is the difference with static timing analysis? Which is accurate?
Why it is accurate?

Give any example for Dynamic timing analysis? Do you know anything about GCL simulation?
What is free running clock?

What type of operating condition you consider for post layout timing analysis?

What is one-hot encoding technique? What are advantages? What are types of encoding?

Which scripting language you know?

How will you analysis the timing of different modes in design? How many modes you had in your design?
What are the clock frequencies?

What your script contains?

Write the digital circuit for below condition: "when ever data changes from one to zero or zero to one
the circuit should generate a pulse of one clock period length"?

Have come across any design with latches? What is the problem in timing analysis if you have latch in
your design?

Have you come across any multiple clock design? What are the issues in multiple clock designs?

What you mean by synthesis strategies

To better understand the process of RTL synthesis, let’s take a closer look at its key steps:

RTL Design: The initial step involves creating the RTL description of the digital circuit, specifying its
behavior and functionality.

Design Constraints: Parameters such as clock frequency, power consumption, and area constraints are
defined at this stage.

Logic Synthesis: The RTL code is transformed into a circuit netlist, consisting of gates and flip-flops, by
mapping the RTL operations onto the library cells.

Technology Mapping: The circuit netlist is further optimized by mapping the gates to specific cells
available in the technology library.

Timing Optimization: Timing constraints are considered, and the netlist is modified to meet the desired
timing requirements.

Power Optimization: Techniques such as clock gating, power gating, and voltage scaling are applied to
reduce power consumption.

Physical Design: The final optimized netlist is subjected to physical design steps, including placement and
routing, to create a layout that can be fabricated