Digital System Design and

Digital Systems Laboratory 3†

ELEE09035
SCQF Level: 9
SCQF Credits: 20

Digital System Design 3†: ELEE09024, 10 Credits

Digital Systems Laboratory 3: ELEE09018, 10 Credits

Course Organiser†: Dr Alister Hamilton

[email protected]
Course Overview
— Introduction and review of fundamentals
— Equivalent states and reduction of state tables
— Introduction to Verilog HDL
— Hardware Description Languages (HDLs)
— Behavioural, structural and data flow models
— Synthesis
— Programmable Logic Devices (PLDs)
— Simple, Complex PLDs, FPGAs, Programmable SoCs
— Design examples
— Data path and controller model

2
Course Overview (continued)
— Addition
— Carry look-ahead adders, parallel prefix adder
— Multiplication
— Add and shift multiplier, array multiplier
— State Machine Charts and Microprogramming
— Floating point arithmetic
— Multiplication, addition, division
— Design of RISC Microprocessors
— Verification of Digital Systems
— Functional verification
— Timing verification

3
Reference Text Books
1. C. H. Roth Jr. and L. K. John, “Digital Systems Design Using
VHDL“, 3rd (international) edition, Cengage Learning, 2016, ISBN-
13: 978-1-305-63892-1
2. P. J. Ashenden, “Digital Design: An Embedded Systems Approach
Using Verilog”, Morgan Kaufmann (Elsevier, 2008) ISBN 978-0-
12-369527-7
3. P. Minns and I. Elliott, “FSM based Digital Design using Verilog
HDL”, Wiley, 2008

Although this course is based upon [1], the HDL of choice is Verilog
rather than VHDL. Lecture material on Verilog is derived from [3].
Reference [2] was recommended for 2nd year digital courses and
remains a good general reference for 3rd year.

Course lecture notes under went a major revision for the 2018/19
academic year.
Assessment

Section A Section B Total

(20 marks) (15 marks) Questions
Digital System Design 3 1 2 out of 2 3

Assessment: 100% examination

The number of questions in section B was reduced from 3 to 2 in

academic year 2020/21. There is now no choice of questions to
answer in this section.

Digital Systems Laboratory 3 is assessed separately

Introduction: Review of Logic
Design Fundamentals
— These introductory lecture slides contain
revision material you should be familiar with.
— State minimisation using the implication chart
is introduced as a new concept.
— In teaching digital system design we develop
techniques for small problems designed by
hand to illustrate concepts.
— The practical design of digital systems is highly
automated with the use of computer systems
and complex algorithms.

6
Learning Objectives
— Combinational Logic
— Boolean Algebra and Algebraic Simplification
— Karnaugh Maps
— Designing with NAND and NOR Gates
— Hazards in Combinational Circuits
— Flip-Flops and Latches
— Mealy Sequential Circuit Design
— Design of a Moore Sequential Circuit
— Equivalent States and Reduction of State Tables
— Sequential Circuit Timing
— Tristate Logic and Busses

1-7
Combination Logic: Basic Gates
— AND Gate: C = A AND B = A ▪ B = AB

— OR Gate: C = A OR B = A + B

— NOT Gate or Inverter: C = NOT A = A’

1-8
Combination Logic: Basic Gates
(cont’d)
— XOR Gate: C = A XOR B = AB’ + A’B = A B

1-9
Combination Logic: Canonical
Forms
— Generally not the simplest form (can be
minimised)
— Derive directly from a Boolean function’s truth
table
— Two canonical forms:
— Sum of Products (minterm)
— Product of Sums (maxterm)

1-10
Combination Logic: Canonical
Forms (cont’d)
X Y Cin Cout Sum
— Sum of Products (minterm)
0 0 0 0 0
— Example:
0 0 1 0 1
Cout = X’YCin + XY’Cin + XYC’in + XYCin
0 1 0 0 1
0 1 1 1 0
1 0 0 0 1
1 0 1 1 0
— Minterm expansions can be 1 1 0 1 0
written in m-notation or decimal 1 1 1 1 1
notation:
— Sum = m1 + m2 + m4 + m7 = ∑m(1,2,4,7)
— Cout = m3 + m5 + m6 + m7 = ∑m(3,5,6,7)

1-11
Combination Logic: Canonical
Forms (cont’d)
— Product of Sums (maxterm)
— Example:
— Cout = (X + Y + Cin)(X + Y + C’in)(X + Y’ + Cin)(X’ + Y + Cin)

X Y Cin Cout Sum

— Maxterm expansion in decimal 0 0 0 0 0
notation: 0 0 1 0 1
— Cout = M0 ▪ M1 ▪ M2 ▪ M4 = ∏ 𝑀(0,1,2,4) 0 1 0 0 1
0 1 1 1 0
1 0 0 0 1
1 0 1 1 0
1 1 0 1 0
1 1 1 1 1
1-12
Boolean Algebra and Algebraic
Simplification
— DeMorgan’s Law:
— Complement all the terms in the expression:
— Replace each variable by its complement.
— Switch 1 with 0 and 0 with 1.
— Change all ANDs to ORs and all ORs to ANDs.
— Add parentheses to ensure proper order of
operations.
— If AND is performed before OR in F, then
parentheses may be required to ensure that OR is
performed before AND in F’.

1-13
Boolean Algebra and Algebraic
Simplification (cont’d)
— Operations with 0 and 1:
— X + 0 = X X•1=X
— X + 1 = 1 X•0=0

— Idempotent laws
— X+X=X X•X=X
— Involution law:
— (X')' = X

— Laws of complementarity:
— X + X' = 1 X • X' = 0

1-14
Boolean Algebra and Algebraic
Simplification (cont’d)
— Commutative laws:
— X + Y = Y + X XY = YX

— Associative laws:
— (X + Y) + Z = X + (Y + Z) = X + Y + Z
— (XY)Z = X(YZ) = XYZ

— Distributive laws:
— X(Y + Z) = XY + XZ
— X + YZ = (X + Y)(X + Z)

1-15
Boolean Algebra and Algebraic
Simplification (cont’d)
— Simplification theorems:
— XY + XY' = X (X + Y) (X + Y') = X
— X + XY = X X(X + Y) = X
— (X + Y')Y = XY XY' + Y = X + Y

— DeMorgan’s laws:
— (X + Y + Z + … )' = X'Y'Z'… (XYZ …)' = X' + Y' + Z' + …
— [f(X1, X2, … XN, 0, 1, +, •)]' = f(X1', X2', … XN', 1, 0, •, +)

1-16
Boolean Algebra and Algebraic
Simplification (cont’d)
— Duality:
— (X + Y + Z + …)D = XYZ … (XYZ…)D = X + Y + Z + …
— [f(X1, X2, … XN, 0, 1, +, •)]D = f(X1, X2, … XN, 1, 0, •, +)

— Theorem for multiplying out and factoring:

— (X + Y)(X' + Z) = XZ + X'Y
— XY + X'Z = (X + Z) (X' + Y)

— Consensus theorem:
— XY + YZ + X'Z = XY + X'Z
— (X + Y)(Y + Z)(X' + Z) = (X + Y)(X' + Z)

1-17
Boolean Algebra and Algebraic
Simplification (cont’d)
— Four ways of simplifying a logic expression
are:
— Combining terms: use theorem XY + XY’ = X to combine two
terms.
— Eliminating terms: use theorem X + XY = X to eliminate
redundant terms. Then try to apply consensus theorem
(XY + X’Z + YZ = XY +X’Z).
— Eliminating literals: use theorem X + X’Y = X + Y to eliminate
redundant literals. Simple factoring might be required prior to
using the theorem.
— Adding redundant terms: can be introduced in several ways
such as adding XX’, multiplying by (X + X’), and so on.

1-18
Karnaugh Maps
— K-maps provide a convenient way to simplify
logic functions of three to five variables.
— 4 variable K-maps:

1-19
Karnaugh Maps (cont’d)
— Procedure to obtain a minimum sum of
products from a Karnaugh map:
— 1. Choose a minterm (a 1) that has not yet been covered.
— 2. Find all 1’s and X’s adjacent to that minterm.
— 3. If a single term covers the minterm and all the adjacent 1’s
and X’s, then that term is an essential prime implicant, so
select that term.
— 4. Repeat steps 1, 2, and 3 until all essential prime implicants
have been chosen.
— 5. Find a minimum set of prime implicants that cover the
remaining 1’s on the map.

1-20
Designing with NAND and NOR
Gates
— To design a circuit of NOR gates:
— Get a product-of-sums representation of the function.
— Find a circuit of OR and AND gates that has an AND gate at the
output.
— If an AND gate output doesn’t drive an AND gate input and an
OR Gate output doesn’t connect to an OR gate input,
conversion is done by replacing all gates with NOR gates and
complementing inputs if needed.
— Conversion to a circuit of NAND gates is
similar except:
— The starting point is a sum-of-products.
— The output gate of the AND-OR circuit should be an OR gate.

1-21
Hazards in Combinational Circuits
— Transients occur when different paths from
input to output have different propagation
delays:
— Static 1-hazard: in response to an input change and for some
combination of propagation delays, a circuit output may
momentarily go to 0 when it should remain a constant 1.
— Static 0-hazard: if the output may momentarily go to 1 when it
should remain a 0.
— Dynamic hazard: when the output is supposed to change from
0 to 1 (or 1 to 0), the output may change three or more times.

1-22
Hazards in Combinational Circuits
(cont’d)
— To design a circuit that is free of static and
dynamic hazards, use this procedure:
— Find a sum-of-products expression (Ft) for the
output in which every pair of adjacent 1’s is
covered by a 1-term.
— If a different form of circuit is desired,
manipulate Ft to the desired form by using
simple factoring, DeMorgan’s laws, and so on.
Treat each xi and x’i as independent variables to
prevent introduction of hazards.

1-23
Latches
— Some types of latches include:
— S-R latch, Transparent D Latch.
Transparent D Latch:

1-24
Latches (continued)

— S-R latch: S R Q Q+ Comment

0 0 0 0 No change
0 0 1 1 No change
S
Q’ 0 1 0 0 Reset
0 1 1 0 Reset
1 0 0 1 Set
1 0 1 1 Set
Q
R 1 1 0 - Not allowed
1 1 1 - Not allowed

1-25
Flip-Flops
— Sequential circuits commonly use flip-flops as
storage devices. Some types include:
— Delay (D) flip-flops, J-K flip-flops, Toggle (T)
flip-flops
Clocked D Flip-Flop:

1-26
Flip-Flops (continued)
— JK flip-flop
J K Q Q+ Comment
0 0 0 0 Hold
Q’ Q
0 0 1 1 Hold
0 1 0 0 Reset
FF 0 1 1 0 Reset
1 0 0 1 Set
1 0 1 1 Set
1 1 0 1 Toggle
K CK J
1 1 1 0 Toggle

Since there is a ‘bubble’ at the clock input, all changes occur following
the falling edge of the clock input.
Flip-Flops (continued)
— T flip-flop
Q’ Q
T Q Q+ Comment
0 0 0 Hold
FF 0 1 1 Hold
1 0 1 Toggle
1 1 0 Toggle
CLK T

A JK flip flop is converted into a T flip flop by connecting J and K

together and to T.
Mealy Sequential Circuit Design
— Two types of sequential circuits:
— Moore: the outputs depend only on the present state.
— Mealy: the outputs depend on both the present state and the
present inputs.
— Consists of a combinational circuit, which generates the outputs and the
next state, and a state register, which holds the present state. The state
register is usually comprised of D flip-flops.

1-29
Mealy Sequential Circuit Design
(cont’d)
— Steps required to design a sequential circuit:
— 1. Determine the required relationship between the input
and output sequences. Find a state graph and state table.
— 2. Reduce the table to a minimum number of states.
— 3. If the reduced table has m states (2n -1 < m £ 2n ), n flip-flops
are needed. Use either the encoded state assignment
technique or the one-hot assignment technique.
— 4. Form the transition table.
— 5. Plot next-state maps and input maps for each flip-flop
and derive the flip-flop input equations. Derive the output
functions.
— 6. Realize the flip-flop input equations and the output
equations using the available logic gates.
— 7. Check your design.

1-30
Moore Sequential Circuit Design
— Outputs depend only on the present state.
— Easier to design and debug than Mealy
machines, but often contain more states than
equivalent Mealy machines.
— No outputs occur during the transition.
— Cannot respond to an input until the active
edge of the clock occurs; this is in contrast to
a Mealy circuit.

1-31
Equivalent States and Reduction of
State Tables
— This concept is important for design and
testing as it helps to reduce the hardware
consumed by circuits.
— Two states in a sequential circuit are said to
be equivalent if we cannot tell them apart by
observing input and output sequences.
— To determine equivalence, use the state
equivalent theorem: if and only if for
every single input X, the outputs are the same
and the next states are equivalent.

1-32
 Reduction of State Tables

• Elimination of redundant states using row

matching.
• Elimination of redundant states using an
implication table.
Why?
• More states mean more flip-flops.
• This means chip/device area occupied is
larger, hence higher cost.
 A Sequence Detector Example
A sequential network has one input X and one
output Z. The network examines groups of four
consecutive inputs and produces an output Z=1
during the last bit of the input sequence 0101 or
1001. The network resets after every four inputs.
Find the Mealy state diagram for this network.

Reminder
• If the output of a sequential network is dependent on the
current state and the current inputs, then the network is
often referred to as a Mealy machine.
• Moore and Mealy machines have slightly different State
Diagrams.
• In a Mealy machine, the outputs are shown on the arrows,
whereas in a Moore machine they are shown on the nodes.
First attempt at a
state table
• A sequential network
has one input X and
one output Z.
• The network
examines groups of
four consecutive
inputs and produces
an output Z=1 during
the last bit of the
input sequence 0101
or 1001.
• The network resets
after every four
inputs.
 Elimination of Redundant States
using row matching
•If two states in a state table have the same next
state and the same outputs for all input
combinations, then these states are equivalent.
•In the table for the sequence detector shown, this
applies to states H and I, so we write H≡I and
remove row I from the state table.
•Similarly, K, M, N and P are also equivalent to H,
and can be removed from the state table
(H≡K≡M≡N≡P).
•Also J≡L, so we remove row L from the state
table.
•All references to removed states must also be
replaced by their equivalents.
Second attempt at a reduced state table
• Removing states I, K, L, M, N, and P from the state table and
replacing states I, K, M, N, P with H and L with J yields:-

• However, this table is

not yet minimal.
• From the table, D≡G
and E≡F.
 Third attempt at a reduced state table
• Removing states F and G from the state table and
replacing them with E and D yields:-

• This is the smallest state table we can achieve using row

matching.
• This enables us to draw a smaller state diagram (reducing the
number of states from 15 to 7 in this example).
 Mealy machine - State diagram

• Note that the outputs cannot be shown on the state nodes. Outputs must be
shown on the arrows. Note also the clear labelling of the arrows using the key.
Equivalent States and Reduction of
State Tables (cont’d)
— Summary of the implication table method of
determining state equivalence:
— 1. Construct a chart that contains a square for each pair of states.
— 2. Compare each pair of rows in the state table. If the outputs
associated with states i and j are different, place an X in square
i–j. If the outputs are the same, place the implied pairs in square
i–j. If the outputs and next states are the same place a check (√)
in square i–j.
— 3. Go through the table square by square. If square i–j contains
the implied pair m–n, and square m–n contains an X, then i º j,
and an X should be placed in square i–j.
— 4. If any X’s were added in step 3, repeat step 3 until no more X’s
are added.
— 5. For each square i–j that does not contain an X, i º j.

1-40
 Implication Table

• To find all states which

are equivalent we use
an implication table.

• We illustrate this
technique using an
artificial example:-
• To draw an implication table, we draw a triangular
diagram with all the states at the bottom except
the last and all the states except the first one up
the side, i.e.:-
• First we eliminate all the combinations which cannot
be equivalent because their outputs are different,
illustrated by a cross.
• Next, we write into each square the equivalences
required to make each combination equivalent, e.g. for
states b and d to be equivalent, a≡f and e≡h.
• Self equivalences can be ignored, e.g. when testing
combination a and d, the condition a≡d can be ignored.
• For states b and g, h≡h is always true and can also be
ignored as a condition.
• Go through each square, crossing out each square which cannot
be true because of a cross in another square.
• For example, b cannot be equivalent to d because a is not
equivalent to f.
• Repeat this until no further states are eliminated.
• After first pass:-
 After second pass:-

A third pass does not eliminate any more states. The

boxes which are not crossed out are therefore
equivalent. Thus in this case cºe and aºd.
Thus we end up with the following reduced state table
(reducing the number of states from 8 to 6) :-
Sequential Circuit Timing
— The correct functioning of sequential circuits
involves several timing issues:
— Propagation Delay or Clock-to-Q delay: small
amount of time that elapses from the time the
clock changes to the time the Q output
changes.
— Setup Time (tsu): the amount of time the D
input is stable before the active edge of the
clock.
— Hold time (th): the amount of time the D input
is stable after the active edge of the clock.

1-48
Tristate Logic and Busses
— Tristate buffers: gates with a high impedance
state (hi-Z) in addition to high and low logic
states. The high impedance state is equivalent
to an open circuit.
— Use tristate buffers when connecting multiple
gate outputs to the same wire or channel.
— Can be used to aid in data transfers between
registers.
— Tristate buffers are either inverting or non-
inverting.

1-49
Tristate Logic and Busses
(cont’d)
— 4 kinds of tristate buffers:

1-50
Summary
— This lecture serves as a review of important
logic design topics such as:
— Combinational logic
— Sequential logic
— Synchronous design
— State reduction
— Sequential circuit timing
— Tri-state outputs

1-51