8088/8086 Hardware

• 40 pins
• 8-bit bi-directional data bus, requiring two
read/write cycles to transmit 16-bit data.
• 20-bit output address bus
• Other pins are for control and status
signals, and communication with
peripherals
• Two operation modes: minimum mode &
maximum mode
• Pins 24 through 31 and pin 34 perform
different functions in minimum mode and
maximum mode

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Lecture on 5 October 2005
Vcc, GND, CLK

Vcc and GND (input) provide the power supply.

Vcc = 5 volts and GND = 0

CLK (input) receives the clock signal, which

provides a reference for synchronization.

0
33% duty cycle

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Address/data pins
AD0 – AD7 (bi-directional) transmit part of
the address (the lowest 8 bit) or 8-bit data.

A8 – A19 (output) transmit part of the address.

A16/S3 – A19/S6 (output) carry the most

significant 4 bits of the address or 4 status bits.

When representing status, S3 and S4 indicate

the segment register being used. S6 always
remains logic 0 and S5 indicates the I flag.

S4 S3
0 0 Extra segment
0 1 Stack segment
1 0 Code or no segment
1 1 Data segment

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Tri-state pin
Signal on a tri-state pin may be in
one of the three states:
1) low (0);
2) high (1);
3) open (high impedance) High Low High High impedance Low High

The “high-impedance” state is equivalent to disconnecting the pin from both the
high and low voltage sources.

If a pin is in the high-impedance state, it will not affect the system bus to which it
is connected. Thus the bus can transmit other signals without being affected.

In 8088, all address pins, data pins, and some of the control pins are tri-state.

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Minimum mode control signals
INTA (tri-state): interrupt acknowledge.

ALE (output):address latch enable, indicating that

the address is available on the bus.

DEN (tri-state): data bus enable, indicating that the

processor is ready to send or receive data.

DT/R (tri-state): data transmit/receive, indicating

whether the processor is sending or receiving data.

IO/M (tri-state): accessing memory or I/O ?

WR (tri-state): is the CPU outputting data ?

HLDA (output):hold acknowledge

HOLD (input): hold request from external circuitry

SS0 (tri-state) is used DT/R with IO/M and to decode

data transfer operations.

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Maximum mode control signals

LOCK (output): lock peripherals off the system

RQ/GT1, RQ/GT0 (bi-directional): request/grant for the
direct memory access (DMA) operation.

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8088 pins summary

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Latch for address lines
Remember that address pins are output !

A latch is like a “buffer” or “bridge” between the

CPU address pins and the system address bus. 8088

The “bridge” allows one-way traffic, which is

controlled by a latch enable signal.

ALE pin from 8088 is used as the latch enable. A8

A9

1) When the latch enable is low, the input pins A15

are set at high-impedance state (don’t care)
2) When the enable line becomes high, the
output is made equal to the input
3) If the enable line goes back low again, the
output retains its current value.

OE (output enable) may be used to provide control on the time instant when
the output become effective.
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Transceiver for data lines
Data transfer is bi-directional between the CPU
and the system bus.

The 8286 transceiver is used with 8088/8086

microprocessor. It contains 16 tri-state pins:
A0 – A7 and B0 – B7.

The OE (output enable) pin gives permission to

the data flow. The T (transmit) pin selects the
direction of data transmission (from A to B or
from B to A).

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De-multiplexing address and data

Problem: the data bus shares part of

the address bus.

De-multiplexing is to separate and

distinguish between address and data.

ALE controls the 74LS373 transparent

latches to perform de-multiplexing.

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Clock generator: 8284A

The 8284A generates the clock pulses from

the oscillator.

It also synchronizes the READY signal and

generates the RESET signal.

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Bus timing
Bus timing concerns the instant and duration that address, data and control
signals appear on the system bus.

Simplified timing diagram

Write Read

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Bus cycles
The 8088 completes a read/write operation in one bus cycle.

Each bus cycle has 4 clock cycles:

T1: Valid address ready on the address bus;

Control signals ALE, DT/R and IO/M are sent out.
T2: Control signals RD and WR are issued;
DEN is set to turn on the data bus;
In write cycle, the data appear on the data bus for external access.
T3: In write operation, this period provides more time for memory access.
In read operation, the microprocessor starts to read the data bus.
T4: In read operation, the microprocessor finishes data reading;
All bus signals are deactivated in preparation for the next cycle.

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Wait state and READY signal
Wait states are needed when accessing slow memory.

The READY signal is used to control whether a wait state should be inserted.
It is sampled at the end of T2. If a logic 0 is detected, indicating “not ready”, T3
will be delayed by inserting an additional cycle Tw.

To insert a wait state, To continue T3 in after the

READY must be low current Tw, READY must go
before this point back high early than this point

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Detailed read timing
TCLAV: clock-to-address valid
measures how soon the address is
made available after T1 starts.

The memory chip has to put data

on the data bus well in advance to
the end of T3.

TDVCL, data valid-to-clock,

specifies how early valid data
should be available.

Thus, the time allowed for the

memory IC to complete data
retrieval is
3T – TCLAV – TDVCL

The read operation would fail if the

memory IC is slower than this.

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I/O interface
I/O interface: data transfer between peripheral devices and microprocessor.
Components of an I/O interface may include:
- data buffer
- low-level communication (hand-shaking) protocol
- conversion of data format (e.g. parallel-serial)
- error detection
- addressing modes

CPU side Peripheral side

Data bus Data buffer (registers) Output ports

Address bus Status registers Input ports

Control bus I/O protocol unit Protocol lines

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8088 I/O interface

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Parallel and serial data transfer
Parallel transfer
– whole byte of data transferred simultaneously using separate data lines
– a dedicated ground line required for each data line to reduce noise
– lower voltage for transmission
– example: printer ports

Serial transfer
– a single line used: transfer one data bit after another
– higher voltage can be used
– good for slower data transfer or over long distance, e.g. mouse, modem
– RS232: the most popular standard

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8255 programmable peripheral interface (PPI)
Intel 8255 is the most commonly used general-purpose parallel I/O interface.

It is a programmable device that follows the control commands of the CPU. The
control command is sent from the CPU to the PPI via the “OUT” instruction.

A0 A1 A0-A7

0 0 A0H

0 1 A1H

1 0 A2H

control port 1 1 A3H

When the control port is selected, 8255 will

receive an 8-bit “control word” via D0 – D7.
This is the way that the 8255 is programmed.

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8255 modes of operation
Mode 0: basic I/O (no handshaking)
Ports A and B: 8-bit unidirectional ports
Port C: 2 × 4-bit unidirectional ports

Mode 1: strobed I/O

Ports A and B: 8-bit unidirectional
Port C: handshaking port. Data are latched for both directions with the strobe
signal carried by one of the port C pins

Mode 2: strobed bi-directional I/O

Port A: 8-bit bi-directional
Port B: 8-bit unidirectional
Port C: handshaking port

Mode of operation is selected by loading a control word into the command

register inside the 8255.

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8255 control word
Each control command is 8-bit. Bits 2, 5 and 6 are for mode selection while bits 0,
1, 3 and 4 are to select I/O directions. Bit 7 must be 1 to enable the control.

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Programming 8255: examples
If the control word equals to 80H, i.e. 1000 0000 in binary, the PPI will operate
in mode 0. All ports are output.

The control word is loaded using the instruction OUT. Similarly, data transfer
to/from the data ports is carried out with instructions OUT and IN.

If the control port has address A3H,

MOV AL,99H
OUT 0A3H,AL
will program the PPI in mode 0, with port A and C as input, port B as output.

Suppose that port A is wired to an 8-line DIP switch and port B is wired to a set
of 8 LEDs. Think about what the following codes will do:

GETSW: IN AL,0A0H
OUT 0A1H,AL
JMP GETSW

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8255 handshaking communication
Handshaking signals are required, for example, in printers, to detect the paper-
out status and whether the printer is ready to accept new data.

8255 mode 0 doesn’t have handshaking. The timing of data’s presence must be
well controlled.

Handshaking for input ports:

STB: strobe to indicate that input data is valid,

asserted by the peripheral to indicate that it has
sent the data.

IBF: input buffer full, asserted by the PPI to

indicate that it has got the data.

INTR: interrupt request from the PPI to tell the

CPU that it has data to be read.

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8255 handshaking communication (continued)
Handshaking for output ports:

OBF: output buffer full, indicating that 8255 has

data to send out

ACK: acknowledge by the peripheral, indicating

that it has received the output data

For bi-directional ports (mode 2), all

of the five handshaking signals are
required.

Meanwhile, port B can be used

either as in mode 0 (basic I/O, no
handshaking) or in mode 1 (strobed
I/O with handshaking).
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8255 application: A/D conversion

The PPI operates in mode 0 (no handshaking):

Port A: input port receiving the results of A/D.
Port C: output port conveying control signals between CPU and
ADC0804 (PC0 – PC3 as input and PC4 – PC7 as output).

To start a conversion, WR must be pulled low.

During the conversion, INT will be kept high and this causes
the 8255 to await for the completion of conversion. Once
the CPU detects that INT becomes low, it will start read
operation by activating RD.
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8255 application: A/D conversion (continued)

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