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DLD Lab 7

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33 views

DLD Lab 7

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arabyeol7
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© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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Department of Electrical Engineering

Faculty Member:Sir Habeel Dated: March 19, 2024

Semester:2nd Section: E

Group No.:
EE-241: Digital Logic Design
Lab 07: Design a display system of a rolling dice

PLO4/CLO4 PLO4/ PLO5/ PLO8/ PLO9/CLO7


CLO4 CLO5 CLO6

Name Reg. No Viva / Lab Analysis Modern Ethics Individual Total


Performanc of data in Tool and and Team marks
e Lab Usage Safety Work Obtaine
Report d

5 Marks 5 Marks 5 Marks 5 Marks 5 Marks 25


Marks

Rimsha Nosheen 471832

Mehreen 462557

Ans-Ur-Rehman 473914

Farhan Naveed 466629


Lab7: Design a system that display from 1 to 6. It displays the result on a
dice. The dice has seven lights

This Lab Activity has been designed to practice the use of basic gates for designing a
system
 Simplification of Combinational Circuits
 Design and Implementation of a design a system to display dice values.
 Values-Segment Decoder for Selected Digit Display
 There are related questions at the end of this activity. Give complete answers.
Use diagrams if needed for clarity.

PreLab Task (5 marks – Individual and team work)


Design a system that display from 1 to 6 (ONLY)i.e. it shows no output in case of illegal
input like 0 and 7. It displays the result on a dice. The dice has seven LEDs a,b,c,d,e,f,g,
placed in H shape pattern as shown on the diagram below

a d e
b f
c g

A 1 for each segment ( a, b, c, d, e, f, g) indicates that it is lit (on); and a 0 that it is off. The
arrangement is the six numbers on a dice are shown below; where the darken circles
depicts LED is ON. (Make sure to switch off all the lights in Don’t care case)

7 bit output

3 bit Input 2
1 3 4 5 6

 Design a driver that produces the seven LED (a, b, c, d, e, f, g) to drive the display.
1. Complete the following table. (Make sure to switch off all the lights in Don’t
care case) (First 3 inputs are filled for guidance)

Inputs (Binary) Outputs(7 LEDs on Dice Display)

Minterm # A B C a b c d e f g

0 0 0 0 0 0 0 0 0 0 0

1 0 0 1 0 0 0 1 0 0 0

2 0 1 0 1 0 0 0 0 0 1

3 0 1 1 1 0 0 1 0 0 1

4 1 0 0 1 0 1 0 1 0 1

5 1 0 1 1 0 1 1 1 0 1

6 1 1 0 1 1 1 0 1 1 1

7 1 1 1 0 0 0 0 0 0 0

 Write minimum possible functions to realize outputs (Either using k-mapping/ or


minimization of Boolean function) (Make sure to switch off all the lights in Don’t
care case). Show and get verified the minimized Boolean Function expressions to
Lab Engineer before implementation.
Hint: You will get 7 output expressions. Output expression for ‘a’ and ‘g’ will be
same. Output expression for ‘b’, and ’f’ will be same. Output expression for ‘c’ , and ‘e’
will be same.

a=(A^B)|(B&(~C));
b=(A&B&(~C));
c=A&((~C)|(~B));
d=C&((~A)|(~B));
e=A&((~C)|(~B));
f=(A&B&(~C));
g=(A^B)|(B&(~C));

 Draw the complete logic circuit diagram of the system from simplified equations.
Proteus Simulation:

1.A=0,B=0,C=0

2.A=1,B=0,C=0
3.A=1,B=1,C=0

4.A=1,B=1,C=1
Lab Task 1 (5 marks – Analysis of Lab report)
 Implement the designed logic circuit on hardware. Utilize your creativity to make
the Dice display model

Inputs (Binary) Hardware Outputs (7 LEDs on Dice Display)

Minterm # A B C a b c d e f g

0 0 0 0 0 0 0 0 0 0 0

1 0 0 1 0 0 0 1 0 0 0

2 0 1 0 1 0 0 0 0 0 1

3 0 1 1 1 0 0 1 0 0 1

4 1 0 0 1 0 1 0 1 0 1

5 1 0 1 1 0 1 1 1 0 1

6 1 1 0 1 1 1 0 1 1 1

7 1 1 1 0 0 0 0 0 0 0
Hardware:

Lab Task 2 (5 marks – Modern tool usage)


 Write Verilog code to realize the design using dataflow model. Design also test bench to
check the valid outputs. Include all the timing diagram snap shots and Verilog code in
the report.

Model sim Simulation:


Code:

module dice(a,b,c,d,e,f,g,A,B,C);

input A,B,C;

output a,b,c,d,e,f,g;

assign a=(A^B)|(B&(~C));

assign b=(A&B&(~C));

assign c=A&((~C)|(~B));

assign d=C&((~A)|(~B));

assign e=A&((~C)|(~B));

assign f=(A&B&(~C));

assign g=(A^B)|(B&(~C));

endmodule

module testdice;

reg A,B,C;

wire a,b,c,d,e,f,g;

dice d1(a,b,c,d,e,f,g,A,B,C);

initial

begin

#100A=1'b0;B=1'b0;C=1'b0;

#100A=1'b0;B=1'b0;C=1'b1;

#100A=1'b0;B=1'b1;C=1'b0;

#100A=1'b0;B=1'b1;C=1'b1;

#100A=1'b1;B=1'b0;C=1'b0;

#100A=1'b1;B=1'b0;C=1'b1;

#100A=1'b1;B=1'b1;C=1'b0;
#100A=1'b1;B=1'b1;C=1'b1;

end

endmodule

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