Unit – 4

Microprogrammed Control Organization

Presented by Purvi Vaghela

• Control Memory
• Address sequencing
• Micro program example
• Design of Control Unit

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 Control Memory
• The function of the control unit in a digital computer is to initiate sequences of
micro operations.
• The control unit initiates a series of sequential steps of micro operations.
• The control variables at any given time can be represented by a string of 1's
and 0's called a control word.
• As such, control words can be programmed to perform various operations on
the components of the system.
• A control unit whose binary control variables are stored in memory is called
micro programmed control unit.
• A memory that is a part of control unit is called a control memory.

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 Address sequencing
• Control memory address register specifies the address of the microinstruction, and
the control data register holds the microinstruction read from memory.
• The microinstruction contains a control word that specifies one or more micro
operations for the data processor.
• The next address generator is sometimes called a micro program sequencer, as it
determines the address sequence that is read from control memory.
• The control data register holds the present microinstruction while the next address is
computed and read from memory. The data register is sometimes called a pipeline
register.
• It allows the execution of the micro operations specified by the control word
simultaneously with the generation of the next microinstruction.

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5 Unit - 4 2024
 Micro program example

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 Micro-instruction code format (20 bits).
The micro operations are subdivided into three fields of three bits each.
The three bits in each field are encoded to specify seven distinct micro
operations.
The CD (condition) field consists of two bits which are encoded to
specify four status bit conditions.
The BR (branch) field consists of two bits. It is used, in conjunction with
the address field AD.

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 The fields specify the following information:
1. The label field may be empty or it may specify a symbolic address. A
label is terminated with a colon (:).
2. The microoperations field consists of one, two, or three symbols,
separated by commas, . There may be no more than one symbol from
each F field. The NOP symbol is used when the microinstruction has no
micro operations. This will be translated by the assembler to nine zeros.
3. The CD field has one of the letters U, I, S, or Z.
4. The BR field contains one of the four symbols defined in previous
Table.
5. The AD field specifies a value for the address field of the
microinstruction in one of three possible ways:
a. With a symbolic address, which must also appear as a label
b. With the symbol NEXT to designate the next address in sequence
c. When the BR field contains a RET or MAP symbol, the AD field is left
empty and is converted to seven zeros by the assembler.

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 Design of Control Unit

• The bits of the microinstruction are usually divided into fields, with
each field defining a distinct, separate function.
• The various fields encountered in instruction formats provide control
bits to initiate microoperations in the system, special bits to specify
the way that the next address is to be evaluated, and an address
field for branching.
• The number of control bits that initiate microoperations can be
reduced by grouping mutually exclusive variables into fields and
encoding the k bits in each field to provide 2^k micro operations.

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10 Unit – 4 2024
 Above Figure shows the three decoders and some of the connections that must be
made from their outputs.
Each of the three fields of the microinstruction presently available in the output of
control memory are decoded with a 3 × 8 decoder to provide eight outputs.
Each of these outputs must be connected to the proper circuit to initiate the
corresponding microoperation.
For example, when F1 = 101 (binary 5), the next clock pulse transition transfers the
content of DR(0-10) to AR (symbolized by DRTAR in Table 7-1).
Similarly, when F1 = 110 (binary 6) there is a transfer from PC to AR (symbolized by
PCTAR).
As shown in Figure, outputs 5 and 6 of decoder F1 are connected to the load input of
AR so that when either one of these outputs is active, information from the multiplexers
is transferred to AR.
The multiplexers select the information from DR when output 5 is active and from PC
when output 5 is inactive.
The transfer into AR occurs with a clock pulse transition only when output 5 or output 6
of the decoder are active.
The other outputs of the decoders that initiate transfers between registers must be
connected in a similar fashion.

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