Exercise 7.

(a) State diagram and transition table:

0,0 0,0

0,1

1,0
00 00

1,1 1,1

0,1 1,0 1,0 0,1

1,1 1,1

1,0
00 00
0,1

0,0 0,0

I1 I0 C1 C0 C1+ C0+
0 0 0 0 0 0
0 1 0 1
1 0 1 0
1 1 1 1
0 1 0 0 0 1
0 1 1 0
1 0 1 1
1 1 0 0
1 0 0 0 1 1
0 1 0 0
1 0 0 1
1 1 1 0
1 1 0 0 1 0
0 1 1 1
1 0 0 0
1 1 0 1
(b) Circuit schematic:

C1 = I1C1’C0’ + I0C1’C0 + I0’C1C0 + I1’C1C0’

C0 = I1I0’C0’ + I1’I0C0’ + I1I0C0 + I1’I0’C0

I1
C1
C0

I0
C1
C0
C1
D Q
I0
C1
C0 Clk

I1
C1
C0
C0 D Q

Clk
I1
I1
C0

I1
I0
C0

I1
I0
C0

I1
I0
C0
(c) NAND/NOR/XOR implementation:

C1 = [(I0 xor C1) + (I1 xor C1)]C0’

C0 = (I1 xor I0) xor C0

I0
C1

C1
I1 D Q

C1
C0 Clk

I1
I0 C0
C0 D Q

Clk
Exercise 7.2
We begin designing the three bit counter by first drawing the state transition graph, then
the state transition table. Since state 101 is not part of the sequence, we need to make
sure that it has a transition out to a state that is part of the sequence.

State diagram:

000 010

001 111

011 100

110

101

State transition table:

C B A C+ B+ A+
0 0 0 0 1 0
0 0 1 0 0 0
0 1 0 1 1 1
0 1 1 0 0 1
1 0 0 1 1 0
1 0 1 1 1 0
1 1 0 0 1 1
1 1 1 1 0 0
Exercise 7.3

(a) 3-bit counter:

D C B A D+ C+ B+ A+
0 0 0 0 0 0 0 1
0 0 0 1 0 0 1 0
0 0 1 0 0 0 1 1
0 0 1 1 0 1 0 0
0 1 0 0 0 1 0 1
0 1 0 1 0 1 1 0
0 1 1 0 0 1 1 1
0 1 1 1 1 0 0 0
1 0 0 0 1 0 0 1
1 0 0 1 0 0 0 0

State transition table

0000 0001 0010 0011 0100

1001 1000 0111 0110 0101

State diagram
(b) Circuit schematic:

D
A
D
C D Q

B
Clk
A

C
B

C
C
A D Q

C Clk
B
A

B
A
B
D D Q

B
Clk
A

A A
D Q

Clk

(c) Expressions for a self-starting counter:

D+ = DA’ + DCB’ + DC’B + D’CBA

C+ = CB’ + CA’ + C’BA

B+ = BA’ D’B’A + CB’A

A+ = A’
Exercise 7.4

(a) Gray-code counter:

D C B A D+ C+ B+ A+
0 0 0 0 0 0 0 1
0 0 0 1 0 0 1 1
0 0 1 0 0 1 1 0
0 0 1 1 0 0 1 0
0 1 0 0 1 1 0 0
0 1 0 1 0 1 0 0
0 1 1 0 0 1 1 1
0 1 1 1 0 1 0 1
1 0 0 0 0 0 0 0
1 0 0 1 1 0 0 0
1 0 1 0 1 0 1 1
1 0 1 1 1 0 0 1
1 1 0 0 1 1 0 1
1 1 0 1 1 1 1 1
1 1 1 0 1 0 1 0
1 1 1 1 1 1 1 0

State-transition table

0000 0001 0011 0010

0100 0101 0111 0110

1100 1101 1111 1110

1000 1001 1011 1010

State Diagram
(b) Circuit Schematic:

D B
A A

D
D
D C B
B D Q D Q
A
C Clk Clk
D
B
C
A
A

C
C
A
B

C
C D
B D Q
A
D Q
D Clk D
B Clk
A
C
B

(c) We don’t need to worry about the self-starting because every possible state is part of
the sequence that the Gray-code counter goes through. So no matter what state the
counter starts out in, it will always count correctly.
Exercise 7.5
4-bit Johnson Counter:

D C B A D+ C+ B+ A+
0 0 0 0 1 0 0 0
0 0 0 1 0 0 0 0
0 0 1 0 - - - -
0 0 1 1 0 0 0 1
0 1 0 0 - - - -
0 1 0 1 - - - -
0 1 1 0 - - - -
0 1 1 1 0 0 1 1
1 0 0 0 1 1 0 0
1 0 0 1 - - - -
1 0 1 0 - - - -
1 0 1 1 - - - -
1 1 0 0 1 1 1 0
1 1 0 1 - - - -
1 1 1 0 1 1 1 1
1 1 1 1 0 1 1 1
State Transition Table

0000 1000 1100 1110

0001 0011 0111 1111

State Diagram

If we assume that the states that are not part of the sequence will never be entered, we can
use the outputs for those states as don’t-cares, which will make our implementation less
complex. The following are the next-state expressions:

D+ = CA’ + BA’

C+ = DB’A’ + DCB

B+ = CB + CA’

A+ = D’B + CB
Exercise 7.6
The solution for Exercise 7.5 is self-starting. All of the states eventually lead into the
counting sequence. The following state diagram illustrates the transitions from each of
the 16 possible states:

0100

0010 1001 1010

1101 0000 1000 1100 1110

0101 0001 0011 0111 1111

1011 0110

State diagram for the 4-bit Johnson counter

Exercise 7.7
An asynchronous load or reset signal may be acceptable when we need to immediately
change the contents of a register without waiting for an extra clock cycle. This could be
important in communication between two FSMs or counters. Of course, we would have
to make sure that asynchronous behaviors in two communicating FSMs were not
inadvertently connected to create an asynchronous feedback cycle (that is, a loop not
interrupted by waiting for a clock signal).
Exercise 7.8
The Load signal on the counter-chip tells the counter to load the value that is on the
parallel load inputs. We can see from the timing diagram that when the counter reaches
11112, the compliment of the RCO signal causes Load to be driven low and the counter
circles back to the value at the parallel load inputs. If we take the RCO compliment and
AND it with an active-low reset signal, we will be able to force the counter to start
counting in its first valid state whenever the reset is driven low. Since we are using an
AND gate with the reset and RCO signals, the functionality of the counter will be exactly
the same but we will be able to start out in the first valid count sequence whenever we
wish. One assumption that we must make about the reset signal is that it is asserted for at
least one clock cycle. If it doesn’t, the counter may behave unpredictably.
Exercise 7.9
To build a BCD counter out of a 163 counter component, we need to have the counter roll
back to zero when 10012 is reached. We can accomplish this by checking the value of the
parallel outputs and when it reaches 10012, drive the CLR input low, which will cause the
next output to be zero. The following circuit diagram illustrates this:
U1
Vcc
P
RCO
T
Clk
Clk
Gnd
D DQ
Gnd
C CQ
Gnd
B BQ
Gnd
A AQ
Vcc
LOAD

CLR

c163

1-Digit BCD Counter

We can add another bit by using two 1-digit BCD counters. The second counter will be
for the most significant bit. This counter should only be incremented every time the least
significant counter rolls over. We can achieve this functionality by using the same signal
that we use to roll over the low order counter as a clock signal for the high order counter.
We have to invert the output of it so that when the low order counter rolls over, the signal
will go high for one clock cycle causing the high order counter to increment itself. This
can be generalized to an n-digit BCD counter by using n BCD counters and using the
CLR output from the n-1 counter as the n counter Clk. The following circuit schematic
illustrates this with a 2-digit BCD counter:

Vcc Vcc
P P
RCO RCO
T T
Clk
Clk Clk
Gnd Gnd
D DQ D DQ
Gnd Gnd
C CQ C CQ
Gnd Gnd
B BQ B BQ
Gnd Gnd
A AQ A AQ
Vcc Vcc
LOAD LOAD

CLR CLR

c163 c163

Low order BCD counter High order BCD counter

Exercise 7.10
So, essentially what we have is two cutoff/offset counters that are set to roll over at their
corresponding correct values. When they roll over, they load the starting value from the
parallel inputs and continue counting. C5-C0 are the bit values for the 6-bit output. The
reset is also tied to the load, which will cause the counters to reset to their start value.
The following circuit schematic illustrates a 6-bit BCD counter:

Vcc
P
RCO
T

Clk
Gnd
D DQ
Gnd
C CQ
Gnd C5
B BQ
Gnd C4
A AQ

reset LOAD

CLR

c163

Vcc
P
RCO
T
Clk
Clk
Gnd C2
D DQ
Gnd C3
C CQ
Vcc C1
B BQ
Gnd C0
A AQ

reset LOAD

CLR

c163
Exercise 7.11

(a) Circuit schematic for the 4-bit serial adder:

A3 A2 A1 A0

Reset
R S R S R S R S
‘0’ A
D Q D Q D Q D Q

CLK B3 B2 B1 B0

Reset
R S R S R S R S
‘0’ B
D Q D Q D Q D Q

CLK

Reset
‘0’ 1
C 0 CI
CO C
A A
S
B B D Q D Q D Q D Q

CLK

S3 S2 S1 S0

(b) The only control signal in this implementation is Reset. When the Reset signal is
asserted, each bit of the two operands is loaded into the registers in parallel. When
the reset signal goes low, each value is shifted to the right on every clock cycle. The
Reset signal also acts as the control for a 2:1 multiplexor, which loads the first carry-
in with a zero. The carry-out feeds back into the carry-in, which causes it to be used
for the subsequent add. After the entire 4-bit value has been shifted through the
adder, the result can be accessed on the output of each sum register.
Exercise 7.12

(a) The way to guarantee that the clock signal only goes high for one clock cycle is to
only assert it when the input signal is changing from low to high. We can do this by
using a 2-bit shift register and checking the value of each bit. When the second one is
low and the first one is high, we assert the output signal.

button
D Q D Q

Clk

pulse

(b) The simplest way to implement this design is to use a register which loads a one into
it when it is reset. The button signal is used as the reset for this register. The clock
input to this register is tied to the output signals from the 163 counter in a manner that
will cause the clock to cycle once on the 13th cycle and load a zero.

button
Vcc
P
RCO
T RST
Gnd pulse_13
Clk D Q
Clk Vcc
Gnd CE
D DQ
Gnd
C CQ
Gnd
B BQ
Gnd
A AQ

LOAD

CLR

c163
(c) A system that will provide a single clock step can be implemented with an extension
of the design in part a. The portion of the design from part a guarantees that the
output will be exactly one clock cycle. ANDing this output with the clock signal will
cause it to cycle from low to high and back down to low again.

button
D Q D Q

Clk

pulse
Clk
Exercise 7.13
The first piece that we need to design is the next state logic. 4:1 multiplexors work well
to implement this functionality. We will use load and count as the control signals for
these multiplexors. When load is zero, we are either counting or not counting. In the
case that we are not counting, the multiplexor just needs to feed back the current value
that the flip-flop has in it. If we are counting, the multiplexor for the B flip-flop is simply
the sum of the A and B flip-flops, which can be implemented with an 2-input XOR. The
mutliplexor for the A flip-flop is just the current output inverted when we are counting.
If the load signal is high, the input to both multiplexors is simply their respective load
values. To achieve the clear functionality, we tie the CLR signal to the reset input of the
flip-flops and tie the CE input to the flip-flops to Gnd. This will reset both of the flip-
flops to zero when the CLR signal is asserted and it will have precedence over both the
count and the load signals. Lastly, the RCO signal is just the outputs of the A and B flip-
flops ANDed together. The resulting circuit schematic looks as follows:

Mux1 Clr
B
B i0

i1 RST
A B
LB D Q
i2 Gnd
LB s1 s0 CE
i3

Clk B
Load Count RCO
A

Mux2 Clr
A
i0
A RST
i1 A
LA D Q
i2 Gnd
LA s1 s0 CE
i3

Clk
Load Count

2-bit up-counter
Exercise 7.14
The biggest problem associated with using both positive and negative edge-triggered flip-
flops is that they latch their inputs at different times and the output for each one is not
valid at the same time as the output of the other one. This can cause serious problems if
the combinational logic which computes the next state of one flip-flop relies on the
output of the other flip-flop. For example, if we have flip-flop A and B, each of which is
triggered on different clock edges, the combinational logic of A may be half way done
computing the next state for A and the output of B changes. This would cause
unpredictable behavior in the combinational logic for A.
Exercise 7.15
Using both flip-flops clocked on both clock edges changes timing constraints
dramatically. Since we are assuming we are not keeping negative and positive edge-
triggered flip-flops segregated, instead of having the single constraint:

Tperiod > Tpd + Tcomb + Tsu

We will now have two constraints, one for each of the two parts of the clock cycle, one
for when the clock is high and one for when the clock is low:

Thigh > Tpd + Tcomb-high + Tsu

Tlow > Tpd + Tcomb-low + Tsu

Therefore, the constraints are much tighter as Thigh and Tlow add up to Tperiod. If the
clock’s duty-cycle is 50%, then things can be made to be pretty similar to a single clock-
edge system if the combinational logic delays can be evenly split between the two parts.
If the clock duty-cycle is 90%, then one constraint will be very tight (10% of the clock
period) while the other will be almost a full period (90% to be exact).
There is rarely an advantage to clocking a single system with both clock edges as it
makes it more difficult for the designer to decide where to place combinational logic.
Exercise 7.16
Since we already have an odd parity checker, designing an even parity checker is trivial.
An even parity checker is just the inverse of an odd one. So we can simply add an
inverter to the output of the odd parity checker. The resulting circuit schematic looks as
follows:

reset

RST
out
in D Q
Gnd
CE

Clk

Even parity checker

Exercise 7.17

(a) It is possible to designe a state diagram with a small number of states to implement
this 9th bit parity checker system. The system doesn’t need to track all possible
combinations of 9 bits. If it did, the system would have 29th or 512 states. In reality,
the state diagram only needs to have 9 states. The first 8 states would count how
many bits the input has seen and update the parity checker for each one. The last
state would compare the current parity checker value with the 9th bit and assert OK or
ERROR.

(b) The way that this design works is when the system is reset, the counter clears its
contents out to be zero. Each clock cycle the counter counts up one and the parity
checker reads in a new value. When the counter reaches 9, the clock inputs to the
counter and flip-flop are disabled, the current value in the flip-flop is XORed with the
9th bit of the input and inverted. If this value is a one, it means that the parity bit and
9th input bit are the same and the output is asserted.

reset

RST
in D Q
Gnd in
CE

out

Clk

Vcc
P
RCO
T

Clk Clk
Gnd
D DQ
Gnd
C CQ
Gnd
B BQ
Gnd
A AQ

LOAD
reset
CLR

c163
9-bit serial parity checker
Exercise 7.18
Let L be the number of flip-flops, J be the number of inputs, and K be the number of
outputs.

(a) The maximum number of states is: 2L = 8

The minimum number of states is: 2L = 8

(b) The maximum number of transitions starting in a particular state is: 2J = 4

The minimum number of transitions starting in a particular state is: 2J = 4

(c) The maximum number of transitions that can end in a particular state is: 2J * 2L = 32

The minimum number of transitions that can end in a particular state is: 0

(d) The maximum number of binary patters that can be displayed on the outputs is:

Min(2K, 2J * 2L) = 32

The maximum number of binary patters that can be displayed on the outputs is:

1
Exercise 7.19
Let L be the number of flip-flops, J be the number of inputs, and K be the number of
outputs.

(a) The maximum number of states is: 2L = 32

The minimum number of states is: 2L = 32

(b) The maximum number of transitions starting in a particular state is: 2J = 8

The minimum number of transitions starting in a particular state is: 2J = 8

(c) The maximum number of transitions that can end in a particular state is: 2J * 2L = 256

The minimum number of transitions that can end in a particular state is: 0

(d) The maximum number of binary patters that can be displayed on the outputs is:

Min(2K, 2L) = 32

The maximum number of binary patters that can be displayed on the outputs is:

1
Exercise 7.20
The counter circuit in this exercise has 2 flip-flops, which tells us that the state diagram
will have four states. We will assume that we don’t care what the transitions are if the
input C is 0. This leaves us with a total of eight entries in our truth table that we care
about. To figure out these values we will trace through the circuit. Once we have the
next state values, we can draw our state diagram.

D C S1 S0 S1+ S0+
0 0 0 0 - -
0 1 - -
1 0 - -
1 1 - -
0 1 0 0 0 1
0 1 1 0
1 0 1 1
1 1 0 0
1 0 0 0 - -
0 1 - -
1 0 - -
1 1 - -
1 1 0 0 1 1
0 1 0 0
1 0 0 1
1 1 1 0
Truth table
As we can see from this truth table the forward sequence of the counter is: 00, 01, 10, 11,
and the reverse sequence is: 00, 10, 01, 11. The transitions are labeled DC, where D is
the count direction input and C is the count input. The state diagram for this design looks
as follows:

00, 10

reset
S0
0 [00] 01

11 00, 10
1
S1 S3
[01] [11]
00, 10 11 11

0 01
S2
[10]

00, 10
Exercise 7.21
A dime and a nickel are asynchronously inserted into the vending machine. At the first
rising edge of the clock, Q1 latches a 1. At the second rising edge of the clock, Q0 latches
a 1 from the nickel. One gate delay later the Moore machine’s Open is asserted. The
asynchronous Mealy machine’s Open is asserted one gate delay after the nickel is
inserted. The synchronous Mealy machine’s Open is asserted when the Open register
latches a 1. We can see that the synchronous Mealy machine is the only implementation
that exhibits the behavior we are looking for. The timing diagram looks as follows:

Clk

Q1

Q0

Moore

A. Mealy

S. Mealy
Exercise 7.22
The state machine needs to be designed so that we must see at least 2 zeros in a row and 2
ones in a row before the output is asserted. So the output is 0 in all states except the final
state, S8. The state diagram looks as follows:

reset
S0
0 1

S1 S2
1
0
0 1
S4 S5

0 1 0
S3 0
1
S7
0
S6
1
0
1

0,1 S8
reset = 0
Exercise 7.23
This design can be implemented with 8 states because the system only needs to keep
track of the last 3 input bits. The transitions are labeled X/Z1Z2, where X is the current
input and Z1 and Z2 are the current outputs. State S7 is the trap state that the system goes
into if it sees the sequence 011. The resulting state diagram looks as follows:

reset
0/00 S0
0/00 1/00

S1 S2

1/10 0/0 0/00

0/00 S5
S3
0/00

1/01 1/10
S4
1/01 1/10

S7 1/01 S6

0/01
Exercise 7.24
Since this system only needs to remember 2 bits of the input sequence, the state diagram
only needs four states. The input is shown next to each transition and the output is shown
in brackets within each state. The resulting state diagram looks as follows:

11, 00

reset
S0
01, 10 [0]
11
00, 10
S1 00 S3
[0] [1]
00, 10
01, 10

11 01
S2
[1]

11, 01
Exercise 7.25

(a) This system can be implemented with four states. Essentially, all it does is count how
many ones have been received. State S1 is the only state which has the output
asserted. The transitions are labeled X/Z, where X is the input and Z is the output.
The resulting state diagram looks as follows:

reset
S0
0/1 1/0
(Mod 1)
0/0
1/0
S1 S3

0/1
(Mod 2)
1/1 1/0
S2

0/0

(b) This system is similar to the system in part a except that it needs to keep track of
whether or not the number of zeros received is even. This basically doubles the
number of states plus it needs an extra state for the start state giving a total of nine.
The transitions are labeled X/Z, where X is the input and Z is the output. The
resulting state diagram looks as follows:
reset
0/1
0/0
S1 S2 S0
0/0

1/0 1/0 1/0

1/0
0/0
0/0
S3 S4 S3 1/0
0/0

1/0 1/0
1/0

0/0
0/0
S5 S6 S3
0/0

1/1
Exercise 7.26

(a) The Mealy machine for this system has four states for each of the combination of the
previous input and the current input plus one for the start state. The transistions are
labeled X1X2/Z1Z2, where X1 and X2 are the inputs and Z1 and Z2 the outputs. The
resulting state diagram looks as follows:

reset
Start
00/00 01/00

01/10
S0 00/01 S1

00/00 01/00
00/01 01/01
00/01 10/10 10/10 01/11

10/10 11/10
S2 11/01 S3

10/01

10/00 11/00
(b) Since the outputs of a Moore machine only depend on the current state, the Moore-
implementation of this system is much more complicated. In order to simplify the
diagram the transition arrows have been left out. Assume a transition arrow from
each of the states to each state S1 through S10 (this corresponds to 90 transitions,
hence, the reason they were omitted). Each tier of the state diagram represents the
previous value seen. The state diagram looks as follows:

Reset
Start

Prev. Input: Equal Greater Than Less Than

S1 S2
00 [0,0] [1,0]

S3 S4 S5
01 [0,0] [1,0] [0,1]

S6 S7 S8
10 [0,0] [1,0] [0,1]

S9 S10
11 [0,0] [0,1]
Exercise 7.27
States q0, q2, and q4 represent an even number of 0’s, with states q0, q1, and q2
representing an even number of zeros. The output would be one in states q1 and q3. The
state diagram looks as follows:

reset

1 0

q2 q0 q3

1 1 0 0 1 1

q4 q1 q5

0 1
Exercise 7.28
There are six different states that the lights can be in. The following chart illustrates one
complete cycle of the traffic lights:

East Red Red Green Yellow Red Red Red

West Red Red Green Yellow Red Red Red
South Green Yellow Red Red Red Red Green
North Green Yellow Red Red G Arrow Y Arrow Green
45 15 45 15 20 10

45 60 105 120 140 150

The input signals to this system include:
Timer 45 done, Timer 15 done, Timer 20 done, Timer 10 done, and Reset
The output signals include:
East Red, East Yellow, East Green, West Red, West Yellow, West Green,
South Red, South Yellow, South Green, North Red, North Yellow, North Green,
N Arrow Yellow, N Arrow Green,
Load 45 Timer, Load 15 Timer, Load 20 Timer, Load 10 Timer

E,W – R E,W – G E,W – R

N,S – G N,S – R N,S – R
NArrow - G

Timer Timer 45 Timer 20

45 Done? Done?
Load Load
Timer Timer
Load Load Load
Timer Timer Timer

E,W – R E,W – Y E,W – R

N,S – Y N,S – R N,S – R
NArrow - Y

Timer Timer 15 Timer 10

15 Done? Done?

Load
Timer

Traffic Controller State diagram

Exercise 7.29
The inputs for the washing machine design are as follows:

Coin = C, Timer = T, Double Wash = D, Lid Open = L

The state diagram looks as follows:

L
C Spin
Soak Off
Hold
L’
T

L
Wash1 Spin

T*D’
T T

Rinse1 Rinse2
T*D T
Wash2
Exercise 7.30
The candy vending machine has a total of 6 states. F is the only state in which the output
is enabled. The states are as follows:

A = Reset, B = 5 cents, C = 10 cents, D = 15 cents, E = 20 cents, F = 25 cents or more

The inputs are as follows:

X1 = 5 cents, X2 = 10 cents, X3 = 25 cents, X4 = reset

The state diagram is as follows:

X2

X4 X1 X1
A B C

X1 X3
X2 X2, X3

X1 X1, X3
D E F
[1]
X1, X2,
X2, X3 X3

X3
Exercise 7.31
The newspaper vending machine has a state that represents how much money has been
deposited so far. Each state has three output transitions, which correspond to a nickel,
dime and quarter being deposited. The transitions are labeled X/Z, where X represents
the input and Z represents the output. If there is no input on a transition it is labeled X,
similarly, if there is no output signals asserted it is labeled Z. The only state that a
newspaper is released in is state q50. If the user deposits more than 50 cents, the system
jumps to a ref state where the money deposited is refunded. The resulting state diagram
is as follows:

D/Z D/Z

reset N/Z q5 N/Z q10 N/Z q15

Q/Z D/Z D/Z

Q/Z Q/Z

D/Z N/Z
D/Z

N/Z N/Z N/Z

q35 q30 q25 q20

D/Z D/Z Q/Z

Q/Z
N/Z Q/Z Q/Z

X/unlatch,REL
q40 N/Z q45 N/Z q50
back to reset

Q/Z
D,Q/Z
ref
X/REF
back to reset D/Z