Captura de Pantalla 2023-12-02 A La(s) 18.10.01
Captura de Pantalla 2023-12-02 A La(s) 18.10.01
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CONTENTS
1. SPECIFICATIONS 3
2. FRONT PANEL FACILITIES ... 5
3. CONNECTION DIAGRAM I
4. BLOCK DIAGRAM 11
5. LEVEL DIAGRAM 13
6. CIRCUIT DESCRIPTIONS
6.1 FM Tuner Section 14
6.2 AM Tuner Section 14
6.3 CD-4 Demodulator Section 16
6.4 SO Full Logic/RM Decoder Section 20
6.5 Control Amplifier 23
6.6 Power Amplifier Section 24
6.7 Protection Circuit 24
7. DISASSEMBLY
7.1 Wooden Gabinet 26
7.2 Bottom Plate . 26
7.3 Front Panel . 27
8. ADJUSTMENTS
8.1 AM Section 28
8.2 FM Section 29
9.3
C FM MPX Section 30
8.4 Power Amplifier Section 31
NOTE:
THE MODEL QX-949A COMES IN TWO VERSIONS DISTINGUISHED AS FOLLOWS:
Round label on
rear panel Voltage Type
110V, ]-20V,130V,220V,
F and 240V (switchable) General export model
@l
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J
Loosen screw to open cover Pull out connector Rotate connector 180" and re-insert it
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5. LEVEL DIAGRAM
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6. CIRCUIT DESCRIPTIONS
6.1 FM TUNER SECTION a DC voltage is produced. By setting the FM
Front End Muting switch to ON, pin 12 is connected to pin
This consists of. a 4-gang variable capacitor tuning 5, and the analog switch in HA1137 is operated
circuit, dual-gate MOS FET RF amplifier and ON-OFF to perform muting.
mixer, and local oscillator with buffer. By employ-
ing a glounded gate-Z of the dual-gate MOS FpT, Multiplex Decoder
the circuit becomes equivalent to a cascade ampli- Demodulation is performed by switching detection
fier, providing large gain with stable operation in with the circuit contained in the IC (HA1156),
the RF amplifier. depicted in Fig. 3. A phase locked loop (PLL)
In the mixer stage, the signal is applied from the produces a 38kHz square wave synchronized to
local oscillator to gate-2. This method allows input the pilot signal. The two gates are alternately
power from the local oscillator to be minimized switched ON-OFF by this signal to derive the L
and features low mutual interference. A variation and R channels from the composite signal. By
of a Clapp circuit forms the local oscillator and by detecting the pilot signal level, the switching signal
inserting a buffer amplifier between it and the from PLL to demodulator is operated ON-OFF.
mixer, the oscillator load is reduced and waveform The STEREO indicator lights at the same time.
distortion suppressed. The oscillation frequency
drawing effect is also eliminated, to provide 6.2 AM TUNER SECTION
extremely stable operation even with strong inputs.
This consists of a 3-gang variable capacitor tuning
lF Amplifier and Detector circuit, a dual element ceramic filter and an IC
These are composed of three dual-element ceramic (HA1138). The IC (Fig. 4) contains an RF stage
filters and two integrated circuits. The first stage and two IF amplifier stages.
IC (HA1201") incorporates a current limiter, while
the second stage IC (HA1137) is shown in Fig. 2.
When pin 12 of HA1137 is at more than xTOkHz
detuning and with an extremely low input level,
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lC: HA1156
lC: HA1138
Fis.4
15
6.3 CD-4 DEMODULATOR SECTION signals, as the difference signal is demodulated
from a frequency modulated 30kHz carrier (sub
Fig. 5 illustrates the composition of this section. signal), and the sum signal varies according to the
cartridge output level (though indirectly related),
Sum Signal System level matching becomes necessaq/.
IC HA1452 is an orthodox 2-channel equalizer In other than the CD-4 mode, a fixed resistor
amplifier. In CD-4 operation, a variable resistor is replaces of the variable resistor to provide a fixed
inserted in the NFB circuit to provide separation gain (35.6d8 at lkHz) equalizer amplifier. The
control by varying the main signal (sum signal) inclusion of a balanced power supply with this
gain. Although the final objective of the CD-4 circuit maintains input and output point potentials
demodulator is to matrix the sum and difference at 0V, preventing click noises when switches are
operated. The 100kS2 impedance of this circuit is
nN452-% r. P. t. changed to 50kA by inserting two 100k0 resistors
in parallel during other than CD-4 operation.
HAI 335
Hl Aoc,'p r i [)e.emnhasis
Separati on
llr-r I f-{-l
control
A. 11. R. S.
Fig. 5
DISC SURFACE
LEFT CHANNEL R]GHT CHANNEL
STYLUS
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20kHz 20kHz
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The equalizer amplifier output goes through a low
pass filter (LPF) to remove the sub signal (30kHz
FM signal). This LPF is an active filter whose
frequency response is shown in Fig. 7.
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Fig.8
-30
I *FM Demodulator
-{0 The block diagram of the PLL FM demodulator
circuit is depicted in Fig. 9. This circuit consists
5I I 0k 30t 50k I 00r
of a voltage control oscillator (VCO), phase com-
Frequency (llz)
Fig.7 parator (PC), DC amplifier (A) and low pass filter
(LPF), with a type of NFB loop following the
Difference Signal System input signal. The VCO oscillates at a controlled
The sub signal is taken from the equalizer amplifier frequency according to the LPF output voltage.
NFB circuit. As it does not pass through the RIAA A voltage proportional to the phase difference
playback standard equalizer, it possesses a flat between the input signal and VCO oscillation out-
frequency response. After passing through a high put is generated in the PC. By using this voltage
pass filter (fc = 27kHz, L?dBloct.), the sub signal to control the VCO oscillation, the oscillation
enters IC HA1335. becomes locked to the input signal phase.
This IC contains a phase locked loop (PLL) FM If the input signal is frequency modulated, the
demodulator circuit, an automatic gain control control signal obtained from the LPF becomes the
(AGC) circuit to stabilize the PLL input signal, FM demodulated output. With an excessively
a muting circuit to cut the demodulated output large frequency deviation of the input signal, which
in the absence of an input signal, and a demodu- the PLL circuit cannot follow, the lock becomes
Iated signal amplifier. In addition to the IC, a disengaged. The frequency range in which locking
de-emphasis circuit, automatic capture range con- can be performed is termed the lock range.
trol (ACC) circuit, LPF, HPF, indicator lamp drive, Locking also becomes impossible when the VCO
and other circuits are used to demodulate the dif- free running frequency (oscillating frequency with-
ference signal from the sub signal. out an input signal) and input signal frequency are
excessively separated. The frequency range in
*AGC Amplifier
which locking can be performed is termed the
Fig. 8 shows the AGC amplifier principle. In this capture range. The locking and capture ranges are
circuit, e1 is the input signal voltage, e2 the output determined by the PLL loop gain and LPF con-
signal voltage, Vr the reference voltage, and Vb stant.
the control voltage.
If Vb is much greater than Vr, 13 becomes approx-
imately equal to I, and e2 o. 0. Conversely, if Vb
is much less than Vr, 13 becomes approximately
equal to I, and e, reaches a maximum (determined
by the murimum gain of the AGC amplifier). The
amplifier gain can therefore be controlled by Vb
in this manner, Vb being obtained from a synchro-
nous detector.
17
6.4 SO FULL LOGIC/RM DECODER SECTION If the sound source is CF (center front) or CB
(center back), front to rear separation cannot be
SQ System obtained since LF', RF', LB' and RB' all become
The Matrix four channel system utilizes 2-channel the same volume. The logic circuit is provided for
media (tape, records, broadcasts, etc.) to transmit improve this effect.
4 or more channel signals. Four channel playback With CF crosstalk to LB and RB is at out of and
systems employ matrixing 4-2-4 (n-2-$ to convert since with CB crosstalk to LF and RF is also at
2-channel into 4-channel. The main systems cur- out of, only these anti-phase components are
rently available for this purpose are RM (Regular cancelled. This is termed front-back logic. The
Matrix) and SQ (Stereo Quad). objective of full logic is to deal not only with CF
With the RM system, if the only sound source is and CB sound sources, but also with various other
LF (left front), - 3dB crosstalk occurs in the RF directions.
(right front) and LB (left back). In the SQ system Front-back logic performs CF and CB detection,
however, - 3dB occurs in LB and RB (right back). while wave matching logic performs LF, RF-, LB
RM and SQ are therefore not compatible. and RB detection. The combined detector signal
Fig. 13 shows the basic SQ decoder construction passes through a time constant circuit and is
and signal vectors. LT and RT are combined in LB applied to the gain control circuit, where gain is
and RB, while LF' and RF' are taken directly controlled in order to adequately reduce the cross-
from LT and RT. LB' and RB' are obtained from talk level.
LT and RT by phase shifting and blending. But
LB' and RB' contain respective LF, RF other than
necessary components. Left and right separation
remains good since LF' does not combine with
RF, and RF' does not combine with LF.
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Time constant circuit
F is. 15
Operating Description For rear control, wave matching logic produces a
The input signal (LT & RT) enters the Se basic negative voltage with respect to afront single signal
decoder (M51651P), where 4-channel signals LF, (LF or RF) and a positive voltage with respect to
RF, LB and RB are obtained by the Se decode a rear single signal (LB or RB). Front control is
matrix, then these signals enter the gain control, also performed by producing the reverse polarity
back blend and logic cirbuits. The front-back logic of these voltages.
produces a positive voltage with a CF sound The rear control voltage passes through the time
source, and a negative one with a CB source. This constant circuit and is applied to the gates of
voltage passes through the time constant circuit MOS FETs for LB and RB gain control. The front
and is applied to the gates of the MOS FETs for control voltage passes through the time constant
LF and RF gain control. circuit and is applied to the gates of the junction
As these FETs are P channel enhancement types, FET for back blend and the MOS FETs for LF
their equivalent internal resistance decreases only and LB gain control. As the junction FET is an N
when a negative voltage is applied. Front (LF & channel depletion type, LB and RB are normally
RF) output signal levels are attenuated with a CB blended, but the device becomes open when a
sound source. negative voltage is applied.
The detector outputs of the full logic IC (CX-049)
with respect to sound source are as shown in the
following table.
LF RF LB RB CF CB Gain control*
FIB F 0 0 0 0 + LF, RF
logic
B 0 0 0 0 + IF iF
CAUTI ON
The gain control lC (CX-718D) is an MOS (metal oxide semiconductor) type and subject to
dielectric breakdown from static electricity. Note the following precaution when handling.
*Do not remove the aluminum
cap from the tC until it has been instalted in teh circuit. First
solder the lc to the circuit board, then remove the aluminum cap.
?2
BX.949A
6.5 CONTROL AMPLIFIER CIRCUIT
The control amplifier circuit of the QX-949A is
the NFB type, using a FET (fietd effect transistor)
in the first stage.
The FET amplifier being a controlable voltage
type, which holds"the input impedance constant,
even if the level of the NFB changes, and has
additional advantage as a coupled circuit, as the
input impedance can be raised
Low Frequency Control
Fis. 16
The low frequency control circuit is shown in
Fig. 16, and the equivalent circuit, when boosting
low frequency, is shown in Fig. 17.
As the parallel impedance of VR1 and C29, in
Fig. 17, is high at low frequency, the volume of
the NFB decreases and the gain in the low
frequency range increases.
The equivalent circuit, when cutting out low
frequencies, is shown in Fig. 18. In this case, the
input signal is applied to Q9, through the parallel Fig. 17
impedance of VR1 and C33, which is high in the
low frequency range and suppresses the lower
frequency signals.
F is. 19
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Fig. 20 Fig.21
23
6.6 POWER AMPLIFIER SECTION Relay Driving Circuit
This unit possesses four power amplifiers. The Q7 - Q9, in Fig. 22, comprise the relay driving
circuitry employs a balanced power supply and circuit.
consists of direct-coupled Darlington connection In the normal condition reverse bias is applied to
pure complementary OCL amplifiers. By applying the base of Q7, and Q7 is in a cutout condition.
1007o DC NFB from the output stage center point When one of the above mentioned detection
to the first stage differential amplifier, circuit DC circuits goes on, current flows through R28, the
gain becomes 0dB. Since the center point potential base potential falls and Q7 is turned on. Con-
is determined by the first stage base potenfial, sequently Q8 comes on and Q9 goes off. When
temperature compensating and fine adjustment Q9 goes off, the current of the relay circuit is
circuits are included in the first stage base bias cut, to release the switch of the output circuit.
circuit to maintain the center point potential at 0V. When the power switch is turned oo, a delay
operation occurs in this circuit. R33, R34 and
2-channel Power Boosting Circuit C7, in the base circuit of Q9, are the time con-
The power supply can be boosted when using this stant elements which determine the delay time.
unit as a Z-channel stereo amplifier (using only When the power switch is switched on, C7 charges
ch1 and ch3, and with the MODE switch set to to a potential of +30 volts through R33 and R34,
zCH). Power transistors of channels 1 and 3 are and Q9 is kept in the OFF condition during this
of higher rating than those of channels 2 and 4. time. When the power source is switched off the
Their supply voltage can be raised during 2-channel muting operation of Q8 prevents shock noise.
operation to provide increased power to each chan- In the normal condition, the potentials of +30
nel. volts and - 5.1 volts are applied to Q8 through
Power boosting is available by turning over the R31 and R32. The resultant potential at the base
rear panel plug. This raises the power transformer of Q8 is -1 volt in the cutout condition. When the
secondary winding taps and opens CHz and CH4 power supply is turned off, the potential of - 5.1
power amplifier output circuits. volts disappears immediately, due to the small
For safety reasons, a microswitch in the power time constant of the power circuit. Thus a positive
transformer primary side cuts off the power supply base potential remains, switching Q8 on, which in
when the selector plug cover is opened. turn switches off Q9 and hence the relay.
6"7 PROTECTION CIRCUIT
This protection circuit functions to protect the
speakers from damage due to short-circuit of the
load, etc., and performs a muting operation to cut
Relay driving circuit
noise and distortion which occur when switching
the power on and off.
The circuit is shown in Fig. 22, and consists of a
bridge type over-current and overload detector, a
differential amplifier DC voltage detector, and a
power switch on/off detector section.
---- r--r-iivl
L ----
---- --l
DC voltage
detection circuit
Fig.22
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Over-current and Overload Detection
The equivalent circuit of this detector section is
shown in Fig. 23, andFig. 24 shows the equivalent
circuit at the time of a positive half cycle. When
this equivalent circuit is overloaded, the balance of
the bridge, formed by REI-, R1, Rg and RL, is
disturbed, and a potential is produced between b
and a in such a direction that Q1 is turned on. Relay driving circuit
Fis.25
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Fis.26
7. DISASSEMBLY
7.1 WOODEN CABINET
Unscrew the two screws holding each side, then
lift the back of the wooden cabinet upward.
a"'.rr--//12.j1
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-,.
26
GIX-g4gA
7.3 FRONT PANEL
Pull off knobs. For TUNING knob, loosen the
setscrews with a hexagonal wrench before remov-
ing it. Unscrew the two screws in the upper edge
of the front panel, and the three nuts from the
shafts. Then pull the panel gently forward.
N \
27
8.3 FM MPX SECTION 3. Connect the oscilloscope horizontal inputs to
1. Set FM signal generator at external modulation. MPX sG's PILor our terminals and vertical
Connect to unit's FM antenna terminals via inputs to No. 18 terminal of tuner assembly.
300-ohm balanced dummy antenna. Set FM SG 4. Tune unit and FM SG to g8MHz.
output to 60d8. 5. Produce a Lissajous pattern on oscilloscope and
2. Adjust MPX signal generator to obtain main adjust VRl to make the pattern still.
signal modulation of lkHz, 67.5kHz frequency 6. Then set signal generator for modulation of L
deviation. Connect to FM SG's external modu- (later R) and pilot. Adjust vR2 to obtain
lator terminals. muimum channel separation.
Tuner assembly
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8.4 POWER AMPLIFIER SECTION amplifier has been come into operation, a defect
1. Do not connect load to speaker terminals" in the output transistors can be suspected.
VOLUME Control set at minimum. Check the output stage.
2. Set power boosting switch to 4CH position. 6. After approx. 10- 20 minutes of warming-up
Then energize unit. time, adjust VRB so that the voltage across
3. For first approximately six seconds, the relay terminals 1 and 2 of the power amplifier
remains open, keeping the unit muted. assembly becomes 20mV.
Confirm that all voltages are as indicated in the 7. In the same w&y, adjust VR4 to obtain 20mV
circuit diagram on page 98. voltage readings across the terminals 25 and 26.
4.lt voltages are greatly different from rated 8. Next, connect voltmeter between terminal 5 and
values, shut off power immediately. Check ground. Adjust VRl to obtain 0V reading.
suspicious areas, especially power supply unit. 9. In the same w&V, adjust VR2 to obtain zero
readings between terminal 23 and ground.
5. If the relay opens immediately after the power
'(+)
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9. DIAL CORD STRINGING
1. Turn the tuning capacitor so that its plates protrude as much as possible.
2. Tie one end of the string to the spring on the Tuning drum (attached to the
tuning capacitor).
3. Lead the string around pulleys A, B, C, D and E, then wind it 3 turns around
the tuning shaft.
4. Lead the string around pulleys F and G, then wind it 2 turns around the Tuning
drum.
5. Now tie the other end of the string to the spring on the Tuning drum. Turn
the tuning shaft and check for proper function. Then trim the ends of the
string.
6. Turn the tuning shaft until the plates of the variable are all the way in. Move
the pointer to the left-end starting point on the dial and fasten it to the string
in that position.
Dial pointer
Tuning shaft
32
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57
HA1452(EO AMP tC)
sl (FUNCT|ON)
515 415 315 215 ',t 15
I 4
10 3
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11 2
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Bottom plate s id
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Rear view
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HA1 137
HA1 136 HA1 156
HA 1 336 HA 1452 3SK45
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'Index
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Index Index
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A-J^E
2SA725 2S8507
2SA7 26 2SC461 2SD31 3
2SA72OA 25A679 258527
2SC869 2SC7 17 25D525 2SA733 2S8530 258528
25 C1312 2SC 1344 2SA763P 2SC 1 079 25D357
2SC945 25D370 25D358
ffi3 ryE
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c
B
2SC1318A /ffO\',-C
I ll z-'\
tli +B
2SC 1 682 2SC 1451 2SC 1384
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13.3 HEADPHONE JACK ASSEMBLY (RWX.Os4)
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150 150 < 150
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RESISTORS OTH E RS
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4CH
0.ol o-{ F--+
0.01
ss
2CH
4CH
Power transformer (V LT)
Power transformer (R ED)
Power transformer (V LT)
Power transformer (R ED)
Power ampl if ier assembly-No. 24
Power amplifier assembly-No. 1 4
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CAPACITORS
Symbol Description Part No. Symbol Description Part No.
c1 Electrolytic O.22 10V CSSA R22M 1O R36 Carbon film 2.2k RD%PM 222J
c2 Electrolytic O.22 10V CSSA R22M 1O R37 Carbon {ilm 15k RD%PM 153J
c3 Electrolytic O.22 10V CSSA R22M 1O R38 Carbon film 47k RD%PM 413J
c4 Electrolytic O.22 10V CSSA R22M 1O
c5 Electrolytic 4-1O 6V cEA 471P 6
SEMICONDUCTORS
c6 Electrolytic 47O 6V cEA 471P 6
c7 Electrolytic 22O Symbol Description Part No,
10V cEA 221P 10
c8 Electrolytic 4.7 25V CEA 4R7P 25 o1 Transistor 2SC869-C, B or D
(2SC1515K)
RESISTORS a2 Transi stor 2SC869-C, B or D
(2SC1515K)
Symbol Description Part No.
o3 T ra nsistor 2SC869-C, B or D
R1 Carbon film 3.3k RD%PM 332J (2SC1515K)
R2 Carbon film 3.3k RD%PM 332J
R3 Carbon film 3.3k RD%PM 332J o4 T ra nsistor 2SC869-C, B or D
R4 Carbon film 3.3k RD74PM 332J (2SC1515K)
R5 Carbon film 3.3k RD!/4PM 332J o5 Transisto r 2SC945-R or O
o6 Transistor 2SC945-R or O
R6 Carbon f ilm 3.3k RD74PM 332J a] Tra nsistor 2SA733-R or Q
R7 Carbon film 3.3k RDz.PM 332J
R8 Carbon film 3.3k RD%PM 332J o8 Transistor 2SC945-R or Q
R9 Carbon f ilm 15k RD74PM 153J o9 Tra nsistor 2SC1384-0 or R
R10 Carbon f ilm 15k RDY4PM 153J
D1 Diode 152472
R11 Carbon film 15k RD%PM 153J D2 Diode 152472
R12 Carbon f ilm 15k RD%PM 153J D3 Diode 152472
R13 Carbon f ilm 15k RD74PM 153J D4 Diode 152472
R14 Carbon f ilm 15k RD]/.PM 153J D5 Diode 152472
R15 Carbon f ilm 15k RD7.PM 153J
D6 Diode 152472
R16 Carbon film 15k RD%PM 153J
D7 Diode 152472
R17 Carbon film 47k RD%PM 473J D8 Diode 152472
R18 Carbon film 47k RD%PM 473J D9 Diode 152472
R19 Carbon film 47k RD%PM D10 Diode 152473
473J
R20 Carbon film 4-1k RD74PM 473J
D11 Diode 152473
R21 Carbon f ilm 1.5k RD%PM 152J
D12 Diode 152473
R22 Carbon f ilm 1.5k RD%PM 152J
R23 Carbon film 82 RD%PM B2OJ
R24 Carbon film 82 RD%PM 82OJ
R25 Carbon film 5.6k RD74PM 562J
a5
2
13.8 CONTROL AMPLTFTER ASSEMBLY (AWG-023)
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Parts List of Power Supply Circuit A Assembly (RWR-O80)
v CAPACITORS ..Enr
SEMICONDUCTORS
Symbol Description Part No. Symbol Description Part No.
c1 Ceramic 0.01 150V ACG-004 o1 Transistor 2SD525-O or R
c2 Ceramic 0.01 150V ACG-004 02 Transistor 2SC1318A-O or R
c3 Ceramic 0.01 150V ACG-004 o3 Transistor 2SC945-R or O
c4 Ceramic 0.01 150V ACG-004 04 Transistor 2SD313-E or D
c5 Electrolytic 470 16V cEA 471P 16 o5 Transistor 2SB507P-E or D
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Parts List of Switch Circuit Assembly (AWS-048)
CAPACITORS SEMICONDUCTORS
Symbol Description Part No. Symbol Description Part No.
c1 "
Ceramic 1O0p 50V CKDSL 101K 50 D1 Diode srBol-ol
c2 Ceramic 100p 50V CKDSL 101K 50 D2 Diode srBol -o1
c3 Ceramic l OOp sOV CKDSL 101K 50 D3 Diode srBol -o1
c4 Ceramic lOOp 5OV CKDSL 101 K 50 D4 Diode srBol -01
C5 Mylar O.O33 sOV coMA 333K 50 D5 Diode srBol -o1
R11 Metal oxide 150 2W RS2P 151K Push switch (SPEAKERSI ASG-046
R12 Metal ox ide 150 2W RS2P 151K
R13 Metal oxide 75 1W RSlP 75OK
R14 Metal ox ide 75 lW RSlP 75OK
R15 Metal oxide 75 1W RSlP 75OK
97
2 3
13.11 POWER AMpLtFtER ASSEMBLY (AWH-027)
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PIOI\EEFI ELECTFIONIC COFIPOFIATICIN
4-'1 , Megutro 1-Chome, Meguno-ku, Tokyo '1 53, Japan