Power-Aware Testing and Test Strategies for Low Power

Devices
Patrick Girard, Nicola Nicolici, Xiaoqing Wen

To cite this version:

Patrick Girard, Nicola Nicolici, Xiaoqing Wen. Power-Aware Testing and Test Strategies for Low
Power Devices. ATS: Asian Test Symposium, Nov 2012, Niigata, Japan. Springer, 2012, 978-1-4419-
0928-2. �lirmm-00820737�

HAL Id: lirmm-00820737

https://hal-lirmm.ccsd.cnrs.fr/lirmm-00820737
Submitted on 6 May 2013

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 !"#$%&'%$( )**+,-,.$/,0,1

Power-Aware Testing and Test Strategies

for Low Power Devices

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McMaster University
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Kyushu Institute of Technology
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1

Power-Aware Testing and Test

Strategies for Low Power Devices

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Springer web site:

http://www.springer.com/engineering/circuits+%26+systems/book/978-
1-4419-0927-5
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Final Test Final Test
Whole population
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Burn-In (4-24 hrs)

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ANALYSIS

Test on Stress

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Sample population ATE (up to 2000 hrs)

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Reliability measurements

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Inputs Outputs
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CLK
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J&"6(*6 J&"6(2G#
ScanENA

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C(P(C(P 4 4 4 4 C(C(C(C 4 4 4 4

P(((((((((((4(((((((((4(((((((((((4 P(((((((((((P((((((((((P(((((((((((P
C(((((((((((P((((((((((4((((((((((4 C(((((((((((P((((((((((P(((((((((((P
P(((((((((((C((((((((((P(((((((((((4 C(((((((((((C((((((((((P(((((((((((P
C(((((((((((P((((((((((C(((((((((((P C(((((((((((C((((((((((C(((((((((((P
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\ 1.35 millions of flip-flops, all are scannable !!
8

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Switching (dynamic) Power

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\ !-i. g--F :(a13j

Leakage (static) Power

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Much higher than during functional operations

!-.(h(!"&'"7=(h(1//0%67
Excessive
determine Test Power
During
)G"$; Structural
K/G6; Testing

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Much higher than during functional operations

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,J*1(>"$%#ZS=#%&@(W%#Z(J&"6E(PX(7"#=?E(ACC'T%#?(J+,X(

Toggle activity under functional mode : 15%-20%

Toggle activity under test mode : 35%-40%

>(!$=?=6#=;(TY(a$==?&"0=(e(*U1(FCCN(@
Power under test mode up to 3.8X power during functional mode

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Main reasons for excessive test power

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1/SD$=??%/6("6;(&/SD"&#%/6(G?=;(V/$(#=?#(;"#"(I/0GS=($=;G&#%/6

For conventional (non low-power) designs, dynamic power

is the main responsible for excessive test power !!

Leakage power is a real issue during IDDQ test (reduced sensitivity) and
during burn-in test (can result in thermal runaway condition and yield loss)

12

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Conventional (slow-speed) scan testing

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At-speed scan testing with a LOC/LOS scheme

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Ç 6/(I"0G=(Z"?(#/(T=(&"D#G$=;h?#/$=;
Ç one peak is not relevant

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Ç S/$=(#Z"6(/6=(D="'(› $=0"#=?(#/(high average power
Ç problems may occur

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Ç 0/7%&(I"0G=?(Z"I=(#/(T=(&"D#G$=;h?#/$=;
Ç one peak is highly relevant

18

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Elevated Average Power

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>=:7:(Z/#(?D/#@ -%=0=&#$%&(K$="';/W6 V$/S(VG6&#%/6"0(S/;=

Chip Damage Reduced Reliability Yield Loss

19

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Elevated Average Power

>#=SD=$"#G$=(%6&$="?=E(=]&=??%I=(Z="#(;%??%D"#%/6@

3/W(,00/W"T0=(!"$"00=0%?S +=;G&=;(U=?#(a$=5G=6&Y
>8"V=$(U=?#%67(d(!"&'"7=(U=?#%67@ >8"V=$(U=?#%67(d(!"&'"7=(U=?#%67@

Low Test Throughput

>0/67=$(#=?#(#%S=@

20

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Elevated Peak Power

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Manufacturing Yield Loss

>2I=$Oj%00@

As huge designs can be manufactured today, most power-related

test issues (during scan) are due to excessive peak power
21

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g;;Oc
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(courtesy: O. Sentieys, IRISA, France) 22

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(courtesy: A. Domic, Synopsys, USA) 23

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24

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activate all modules activate only one module

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(courtesy: K. Hatayama, STARC, Japan) 25

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Straightforward Solutions

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̇ )$%;(J%f%67(V/$(#=?#(DG$D/?=(#//(=]D=6?%I=(^^

Costly or longer test time

26

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Main classes of dedicated solutions

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Objective

Make test power dissipation comparable to functional power

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27

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Main classes of dedicated solutions

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-=?%76(V/$(U=?#(!/W=$(+=;G&#%/6(((
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JY?#=SO3=I=0(!/W=$O,W"$=(U=?#(J&Z=;G0%67

28

14
 @)514)5'6/0'-#/4,##'6&/A'&'6,#%)&/
The Role of Test Data in Test Flow
Test
Tester

Test
Patterns

LSI Chip
Probe Card
Fabrication Prober
Design Data
Socket Board
Handler

Expected Comparison Actual

Responses Responses
GO NG
Data
Passing Chips Falling Chips
JZ%D -%?&"$;

29

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Target of Scan Test Pattern Generation

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PI PO
U=?# 1/ST%6"#%/6"0 U=?#
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PPO +=?D/6?=
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1cU

Scan-Out

J&"6
!!*OJ#%SG0G? aa? !!2O+=?D/6?=

Scan Chain

Scan-In

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>W%#Z/G# #Z= V"G0#@ 1cU &$="#= ;%VV=$=6# $=?D/6?=? /6 "# 0="?# /6= /G#DG# >!2 h !!2@:
30

15
 @)514)5'6/0'-#/4,##'6&/A'&'6,#%)&/
Automatic Test Pattern Generation (ATPG)
CUT
X
U=?#(1GT=
1"$=(K%# 1 a"G0# >0/7%&(I"0G=(V%]=;("#(C@
X
0
1
1
-/6o#(1"$=(K%#
X #/(T$%67(-(#/("6(/G#DG#
4OK%#
X

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V/$ %6DG# T%#? %6 /$;=$ #/ ;=#=&# " V"G0# %6 #Z= 7%I=6 1cU:
\ ./# "00 %6DG# T%#? 6==; #/ T= "??%76=; W%#Z 0/7%& I"0G=? %6 /$;=$ #/ ;=#=&# " V"G0#:
\ UZ= %SS=;%"#= $=?G0# /V ,U!) %? " #=?# &GT=E WZ%&Z &/6#"%6? T/#Z ?D=&%V%=; T%#?
>&"$= T%#?@ "6; G6?D=&%V%=; T%#? >;/6o# &"$= T%#? /$ 4OT%#?@:
31

@)514)5'6/0'-#/4,##'6&/A'&'6,#%)&/
X-Bits in Test Cubes
>K0/&'(%6("6(*6;G?#$Y(1Z%DL(BC6SO!$/&=??(h(P:Fg(h(RCjO)"#=(h(F:R`(g--(*+O-$/D(,00/W"6&=@
100
90
X-bits Ratio (%)

80
70
60
50
40
30
20
0 50 100 150 200 250 300 Vec.

\ , 0"$7= D=$&=6#"7= /V %6DG# T%#? %6 " #=?# &GT= "$= ;/6o# &"$= T%#? >4OT%#?@:
\ .==; 4OV%00%67 >i.e., assigning logic values to X-bits@ #/ &$="#= " &/SD0=#= #=?# D"##=$6:
32

16
@)514)5'6/0'-#/4,##'6&/A'&'6,#%)&/
Conventional X-Filling Technique: Random-Fill

\ 1/6I=6#%/6"00YE 4OT%#? %6 " #=?# &GT= "$= V%00=; W%#Z $"6;/S 0/7%& I"0G=?:
\ ,;I"6#"7=? › Small test pattern count due to “fortuitous detection”
\ -%?";I"6#"7= › High test (shift and LTC) power
33

@)514)5'6/0'-#/4,##'6&/A'&'6,#%)&/
Various Low-Power X-Filling Techniques

Low-Shift-Power X-Filling X
JZ%V#O*6(!/W=$(+=;G&#%/6 JZ%V#O2G#(!/W=$(+=;G&#%/6 U/#"0(JZ%V#(!/W=$(+=;G&#%/6
0-fill
1-fill output-justification-based X-
MTR-fill

X
MT-fill filling
adjacent fill / repeat fill
Low-LTC-Power X-Filling
aaO2$%=6#=; ./;=O2$%=6#=; 1$%#%&"0O,$="O2$%=6#=;
PMF-fill
LCP-fill PWT-fill CCT-fill
preferred fill state-sensitive X-filling CAT-fill

X
JP-fill
CTX-fill
Low-Shift-and-LTC-Power X-Filling
impact-oriented X-filling hybrid X-filling bounded adjacent fill
Low-Power X-Filling for Compressed Scan Testing
0-fill PHS-fill CJP-fill

(source: X. Wen and S. Wang, Low-Power Test Generation, Chapter 3 in Power-Aware Testing and
Test Strategies for Low Power Devices, edited by P. Girard, N. Nicolici & X. Wen, Springer, 2009) 34

17
@)514)5'6/0'-#/4,##'6&/A'&'6,#%)&/
Example 1: Low-Shift-Power X-filling

\ GoalL U/ "??%76 D$/D=$ 0/7%& I"0G=?

#/ ;/6o# &"$= T%#? >4OT%#?@ %6 " #=?#
&GT= ?/ "? #/ $=;G&= #$"6?%#%/6? %6
?&"6 &Z"%6? >"6; #ZG? "0?/ %6 #Z=
&/ST%6"#%/6"0 0/7%&@:
\ !/DG0"$ #=&Z6%5G=? %6&0G;= 0-fillE
1-fillE MT-fillE "6; adjacent-fill:
\ X/?#0Y ?Z%V#O%6 D/W=$ %? $=;G&=;:
2&&"?%/6"00YE ?Z%V#O/G# D/W=$ "6;
3U1 D/W=$ "$= "0?/ $=;G&=;E
=?D=&%"00Y TY 0-fill:
\ +=D/$#=; TY U* "# *U1 FCCA:
\ ./ "$=" /I=$Z="; TG# S"Y
%6&$="?= #=?# D"##=$6 &/G6#:

35

@)514)5'6/0'-#/4,##'6&/A'&'6,#%)&/
Example 1 (cont’d): Low-Shift-Power X-filling

J&"6O2G#L(P(0 4(4(1 4(C(4(4(C(LJ&"6O*6

COa%00 a%00("00(XO?#$%67?(W%#Z(C:
POa%00 a%00("00(XO?#$%67?(W%#Z(P:
XUOa%00 *V(#Z=(?D=&%V%=;(T%#?(/6(T/#Z(?%;=?(/V("6(X-?#$%67(Z"I=(#Z=(?"S=(
0/7%&(I"0G=E(#Z=(X-?#$%67(%?(V%00=;(W%#Z(#Z"#(0/7%&(I"0G=<(/#Z=$W%?=E(
#Z=(X-?#$%67(%?(V%00=;(W%#Z("6("$T%#$"$Y(0/7%&(I"0G=:
,;p"&=6#Oa%00 a%00("6(XO?#$%67(W%#Z(#Z=(?D=&%V%=;OT%#(/6(#Z=(?Z%V#O/G#(?%;=:

COa%00 ,;p"&=6#Oa%00
POa%00 XUOa%00

P(C(0 0 P 0 C(0 0 C P(C(1 1 P 1 C(1 1 C P(C(1 1 P 0 C(0 0 C P(C(0 0 P 1 C(0 0 C

PC FR N PP

\ ,I"%0"T0= V$/S S/?# &/SS=$&%"0 ,U!) #//0?: 36

18
@)514)5'6/0'-#/4,##'6&/A'&'6,#%)&/
Example 2: Low-LTC-Power X-Filling
IR-Drop
VDD
Combinational Circuit
Launch-to-Capture (LTC) Power

Delay Increase

Stimulus Response

0 1 Timing
aaP
1 0
!!* aaF !!2
0 0 Malfunction
aaA
>U=?#O*6;G&=;(i%=0;(3/??@

Up!njojnj{f!uif!Ibnnjoh!ejtubodf!cfuxffo!QQJ!boe!QQP
37

@)514)5'6/0'-#/4,##'6&/A'&'6,#%)&/
Example 2 (cont’d): Low-LTC-Power X-Filling
JP-Fill
0-Prob U=?#(1GT= Test Response
1-Prob f 0
0 !2 1
>P:CCE(C:CC@ !*
X
1 1
>C:CCE(P:CC@ Assign
0 X
0 Justify
>P:CCE(C:CC@
1
X !!* !!2 1
>C:CCE(P:CC@
too close to call
X X
>C:RCE(C:RC@ >C:[AE(C:RM@
X
1 X
0
>C:RCE(C:RC@ >C:PME(C:NA@ P

Signal Probability Calculation

Logic Value Determination
Next Pass No Decision

(source: X. Wen et al., Proc. ITC, Paper 25.1, 2007) 38

19
@)514)5'6/0'-#/4,##'6&/A'&'6,#%)&/
Example 2 (cont’d): Low-LTC-Power X-Filling
>K0/&'(%6("6(*6;G?#$Y(1Z%DL(BC6SO!$/&=??(h(P:Fg(h(RCjO)"#=(h(F:R`(g--(*+O-$/D(,00/W"6&=@

0.06
Original
0.05
JP-Fill
(V)

Risky
0.04
LTC IR-Drop
-

0.03

0.02
Safe
0.01

0.00
0 50 100 150 200 250 300
.
Test Vectors

Original JP-Fill
Chip-Level
Risky Safe
IR-Drop Distribution

39

@)514)5'6/0'-#/4,##'6&/A'&'6,#%)&/
Example 3: Low-Shift-&-LTC-Power X-Filling

0-Fill C0000CP00000PC00000P

Adjacent Fill C 0 0 0 0 C P 11111 P C 0 0 0 0 0 P

Test CubeL C4X44CP44X44PC44X44P Shift Direction

C4044CP44044PC44044P
Bounded Adjacent Fill
1st 0-Constraint Bit Bounding Interval = 6

C C 0 C C C PPP 0 C C P C C C 0 C C P

‚ UZ=(T"?%&(%;="(%?(#/(V%$?#(?=#(?=I=$"0(XOT%#?(%6("(#=?#(&GT=(#/(C("6;(#Z=6(&/6;G&#(adjacent fill:
î The occurrence of 0 in the resulting fully-specified test vector is increased, which helps
reduce shift-out and LTC power. å making use of the benefit of 0-fill
î At the same time, applying adjacent fill helps reduce shift-in power.

(source: A. Chandra et al., Proc. VTS, pp. 131-138, 2008) 40

20
@)514)5'6/0'-#/4,##'6&/A'&'6,#%)&/
Summary - (1)

‚ ,(0"$7=(D/$#%/6(/V(%6DG#(T%#?(%6(#=?#(&GT=?("$=(;/6o#(&"$=(T%#?(>4OT%#?@(
=I=6("V#=$("77$=??%I=(#=?#(&/SD"&#%/6(%6(,U!):(

‚ 4OT%#?(&"6(T=(G?=;(V/$($=;G&%67(I"$%/G?(?Z%V#("6;h/$(3U1(D/W=$:
9?D=&%"00YE(COV%00(&"6($=;G&=(?Z%V#O%6E(?Z%V#O/G#E("6;(3U1(D/W=$(#/(?/S=(=]#=6#:(

‚ 4OV%00%67OT"?=;(0/WOD/W=$(#=?#(7=6=$"#%/6(&"G?=?(6=%#Z=$("$="(/I=$Z=";(
6/$(D=$V/$S"6&=(;=7$";"#%/6:(

‚ X/?#(&/SS=$&%"0(,U!)(#//0?(6/W(?GDD/$#(0/WOD/W=$(4OV%00%67:

‚ U=?#(D"##=$6(&/G6#(S"Y(%6&$="?=(;G=(#/(0/WOD/W=$(4OV%00%67:(UZ%?(D$/T0=S(
&"6(T=(?/0I=;(TY(
>PL(Vector-Pinpoint@(%;=6#%VY%67(Z%7ZO#=?#OD/W=$(#=?#(D"##=$6?("6;(&/6;G&#%67(((
4OV%00%67(/60Y(V/$(#Z/?=(D"##=$6?E(/$(
>FL(Area-Pinpoint@(%;=6#%VY%67(Z%7ZO#=?#OD/W=$("$="?("6;(&/6;G&#%67(4OV%0%67(((
/60Y(#/($=;G&=(#=?#((D/W=$(%6(#Z/?=("$="?:(((((
41

@)514)5'6/0'-#/4,##'6&/A'&'6,#%)&/
Summary - (2)

Current Future
Low-Power Test Power-Safe Test
Generation Generation

2012 20??
Coarse-Grained Fine-Grained
c6V/&G?=;(>Global@(+=;G&#%/6 a/&G?=;(>Regional@(+=;G&#%/6
2I=$O+=;G&#%/6(+%?' ./(2I=$O+=;G&#%/6
c6;=$O+=;G&#%/6(+%?' c6;=$O+=;G&#%/6(1/G6#=$S="?G$=
U=?#(bG"0%#Y(-=7$";"#%/6(+%?' X%6%SGS(U=?#(bG"0%#Y(*SD"&#
J=I=$=(U=?#(-"#"(*6&$="?= X%6%SGS(U=?#(-"#"(*6&$="?=
./(!/W=$(J"V=#Y()G"$"6#== !/W=$(J"V=#Y()G"$"6#==
(source: X. Wen, ETS, Invited Talk, 2012) 42

21
>'?".%&;/0'-#/4)5'6
Main classes of dedicated solutions

3/WO!/W=$(U=?#(!"##=$6()=6=$"#%/6(
-=?%76(V/$(U=?#(!/W=$(+=;G&#%/6(((
!/W=$O,W"$=(K*JU("6;(U=?#(-"#"(1/SD$=??%/6
JY?#=SO3=I=0(!/W=$O,W"$=(U=?#(J&Z=;G0%67

Objective

Make test power dissipation comparable to functional power

8Z%0=("&Z%=I%67(Z%7Z(V"G0#(&/I=$"7=E(?Z/$#(#=?#("DD0%&"#%/6(#%S=E(?S"00(
#=?#(;"#"(I/0GS=E(0/W(#=?#(;=I=0/DS=6#(=VV/$#?E(0/W("$="(/I=$Z=";E(_

43

2'-%;&/3)6/0'-#/4)5'6/>'?".#%)&
-G$%67(?&"6(#=?#%67(>?#"6;"$;(/$("#O?D==;@L

Shift Power Reduction LTC Power Reduction

‚ Shift Impact Blocking ‚ Partial Capture

O blocking gateE(special scan cell O circuit modification
O first-level power supply gating - scan chain disable
‚ Scan Chain Modification - one-hot clocking
- capture-clock staggering
O scan cell reordering
- scan chain segmentation
O scan chain disable
‚ Scan Clock Manipulation
O splittingE staggering
- multi-duty clocking

44

22
2'-%;&/3)6/0'-#/4)5'6/>'?".#%)&
Example 1: Low power scan cell

\ X"?#=$O?0"I=(?#$G&#G$=(/V("(SG]O-(V0%DOV0/D(%?(S/;%V%=;
\ )"#=(#Z=(;"#"(/G#DG#(;G$%67(?Z%V#
\ U/770=(?GDD$=??%/6(;G$%67(?Z%V#
\ KG#(S/;%V%&"#%/6(/V("00(V0%DOV0/D?(› %SD"&#(/6("$="("6;(D=$V/$S"6&=(
(source: A. Hertwig and H.-J. Wunderlich, Proc. ETW, pp. 49-53, 1998) 45

2'-%;&/3)6/0'-#/4)5'6/>'?".#%)&
Example 2: Scan chain segmentation

SI J&"6(1Z"%6(, C
SO
J&"6(1Z"%6(K P
ENAA ENAB
ScanENA 1/6#$/0

J&"6(1Z"%6(,( J&"6(1Z"%6(K( 0"G6&Z &"D#G$= :::

::: :::

::: :::

\ 1/6#$/00"T0=("6;(;"#"O%6;=D=6;=6#(=VV=&#(/V(?Z%V#(D/W=$($=;G&#%/6
\ ./(&Z"67=(#/(,U!)("6;(6/(%6&$="?=(%6(#=?#("DD0%&"#%/6(#%S=
\ !$=?=6#=;(>"6;(G?=;@(TY(U*(e(*U1(FCCC
46

23
2'-%;&/3)6/0'-#/4)5'6/>'?".#%)&
Example 3: Staggered clocking

SI J&"6(1Z"%6(, C
SO
J&"6(1Z"%6(K P
CK/2 CK/2u
CK 10/&'("6;(2G#DG#(1/6#$/0

J&"6(1Z"%6(,("6;(J&"6(1Z"%6(K(("0#=$6"#%I=0Y( 0"G6&Z &"D#G$= :::

:::

:::

\ UZ=(/$%7%6"0(?&"6(&Z"%6(%?(?=7S=6#=;(%6#/(#W/(6=W(?&"6(&Z"%6?
\ 9"&Z(?&"6(&Z"%6(%?(;$%I=6(TY("(&0/&'(WZ/?=(?D==;(%?(Z"0V(/V(#Z=(6/$S"0(?D==;(
\ ,#(="&Z(&0/&'(&Y&0=E(/60Y(Z"0V(/V(#Z=(&%$&G%#(%6DG#?(&"6(?W%#&Z
47

2'-%;&/3)6/0'-#/4)5'6/>'?".#%)&
Example 4: Scan cell reordering

\ J&"6(&=00(/$;=$(%6V0G=6&=?(#Z=(6GST=$(/V(#$"6?%#%/6?(
\ .==;(#/(&Z"67=(#Z=(/$;=$(/V(T%#?(%6(="&Z(I=&#/$(;G$%67(#=?#("DD0%&"#%/6
\ ./(/I=$Z=";E(a1("6;(#=?#(#%S=(G6&Z"67=;E(0/W(%SD"&#(/6(;=?%76(V0/W
\ X"Y(0=";(#/($/G#%67(&/67=?#%/6(D$/T0=S?(_
(courtesy: H.-J. Wunderlich and C. Zoellin, Univ. Stuttgart) 48

24
2'-%;&/3)6/0'-#/4)5'6/>'?".#%)&
Example 5: Inserting logic into scan chains

\ UZ=(7/"0(%?(#/(S/;%VY(#Z=(#$"6?%#%/6(&/G6#(;G$%67(?Z%V#

(courtesy: H.-J. Wunderlich and C. Zoellin, Univ. Stuttgart) 49

2'-%;&/3)6/0'-#/4)5'6/>'?".#%)&
Example 6: Scan segment inversion

\ UZ%?(%?(;/6=(TY(=ST=;;%67("(0%6="$(VG6&#%/6(%6(#Z=(?&"6(D"#Z
\ +=;G&=?(#Z=(#$"6?%#%/6(&/G6#(%6(#Z=(?&"6(&Z"%6
(courtesy: H.-J. Wunderlich and C. Zoellin, Univ. Stuttgart) 50

25
>'?".%&;/0'-#/4)5'6
Main classes of dedicated solutions

3/WO!/W=$(U=?#(!"##=$6()=6=$"#%/6(
-=?%76(V/$(U=?#(!/W=$(+=;G&#%/6(((
!/W=$O,W"$=(K*JU("6;(U=?#(-"#"(1/SD$=??%/6
JY?#=SO3=I=0(!/W=$O,W"$=(U=?#(J&Z=;G0%67

51

4)5'61B5,6'/+=:0/,&?/()786'--%)&
Example 1: Masking logic insertion during BIST

U=?#(J=5G=6&= 13j 3aJ+

V0
-=&/;=$
3aJ+(%6Z%T%#%/6(
Vi
Vj 3aJ+("&#%I"#%/6(
aa
Vk 3aJ+(%6Z%T%#%/6(
Vl 3aJ+("&#%I"#%/6( 1cU

!$=I=6#("DD0%&"#%/6(/V(6/6O;=#=&#%67(>TG#(&/6?GS%67@(I=&#/$?(#/(#Z=(1cU:
,(;=&/;=$(%?(G?=;(#/(?#/$=(#Z=(V%$?#("6;(0"?#(I=&#/$?(/V(="&Z(?GTO?=5G=6&=(
/V(&/6?=&G#%I=(6/6O;=#=&#%67(I=&#/$?(#/(T=(V%0#=$=;:

X%6%S%f=?("I=$"7=(D/W=$(W%#Z/G#($=;G&%67(V"G0#(&/I=$"7=

(source: P. Girard et. al., Proc. VTS, pp. 407-412, 1999) 52

26
4)5'61B5,6'/+=:0/,&?/()786'--%)&
Example 2: Adaptation to Scan-Based BIST

X"?'%67h=6"T0%67(0/7%&(V%0#=$?(#Z=(
6/6O=??=6#%"0(I=&#/$?("6;(S"DD%67(
0/7%&(&"6(%SD$/I=(#Z=(&/$$=0"#%/6(/V(
#Z=(I"0G=?(/6(#Z=(7=6=$"#/$(/G#DG#

(source: F. Corno et. al., Proc. DFT, pp. 219-226, 1999) 53

4)5'61B5,6'/+=:0/,&?/()786'--%)&
Example 3: Dual-speed LFSR for BIST

-G"0O?D==;(3aJ+(O &/6&=D#

(source: S. Wang and S. Gupta, Proc. ITC, pp. 848-857, 1997) 54

27
4)5'61B5,6'/+=:0/,&?/()786'--%)&
Example 3 (cont’d): Dual-speed LFSR for BIST

(source: S. Wang and S. Gupta, Proc. ITC, pp. 848-857, 1997) 55

4)5'61B5,6'/+=:0/,&?/()786'--%)&
Example 4: Coding for compression and test power

(courtesy: K. Chakrabarty and S.K. Goel, Duke Univ.) 56

28
4)5'61B5,6'/+=:0/,&?/()786'--%)&
Example 5: Linear Finite State Machines

?&"6(?0%&=

*;=6#%VY(&0G?#=$?(%6(#Z=(#=?#(&GT=(#Z"#(&"6(
Z"I=("00(#Z=(?&"6(?0%&=?(S"DD=;(/6#/(
#Z=(?"S=(I"0G=

&0G?#=$
‚
‚
‚

‚
‚
‚

(source: F. Czyusz et al., Proc. VTS, pp. 75-83, 2007) 57

>'?".%&;/0'-#/4)5'6
Main classes of dedicated solutions

3/WO!/W=$(U=?#(!"##=$6()=6=$"#%/6(
-=?%76(V/$(U=?#(!/W=$(+=;G&#%/6(((
!/W=$O,W"$=(K*JU("6;(U=?#(-"#"(1/SD$=??%/6
JY?#=SO3=I=0(!/W=$O,W"$=(U=?#(J&Z=;G0%67

58

29
:C-#'71@'D'$/4)5'61B5,6'/:.E'?"$%&;
Improve Test Throughput by Exploiting Design Modularity
!/W=$

!/W=$(0%S%#

U=?#(#%S=

\ UZ= 7/"0 %? #/ ;=#=$S%6= #Z= T0/&'? >S=S/$YE 0/7%&E "6"0/7E =#&:@ /V "6 J21
#/ T= #=?#=; %6 D"$"00=0 "# ="&Z ?#"7= /V " #=?# ?=??%/6 %6 /$;=$ #/ '==D
D/W=$ ;%??%D"#%/6 G6;=$ " ?D=&%V%=; 0%S%# WZ%0= /D#%S%f%67 #=?# #%S=
\ J/S= /V #Z= #=?# $=?/G$&=? >D"##=$6 7=6=$"#/$? "6; $=?D/6?= "6"0Yf=$?@
SG?# T= ?Z"$=; "S/67 #Z= I"$%/G? T0/&'?

(source: Y. Zorian, Proc. VTS, pp. 4-9, 1993) 59

:C-#'71@'D'$/4)5'61B5,6'/:.E'?"$%&;
Example 1: Resource Allocation and Incompatibility Graphs

(source: R. Chou et al., IEEE Trans. on VLSI, Vol. 5, No. 2, pp. 175-185, 1997) 60

30
:C-#'71@'D'$/4)5'61B5,6'/:.E'?"$%&;
Example 1 (cont’d): Power Model and Test Schedule

(source: R. Chou et al., IEEE Trans. on VLSI, Vol. 5, No. 2, pp. 175-185, 1997) 61

:C-#'71@'D'$/4)5'61B5,6'/:.E'?"$%&;
Example 2: Power Profile Manipulation

!/W=$(D$/V%0=(&"6(T=(S/;%V%=;(TY(
D"##=$6(S/;%V%&"#%/6("6;h/$(#=?#(
?=#($=/$;=$%67

62

31
:C-#'71@'D'$/4)5'61B5,6'/:.E'?"$%&;
Example 3: Thermal Considerations

63

FD,$",#%&;/<
Test Power Reduction Strategies

\ !/W=$ $=;G&#%/6 =VV=&#%I=6=?? High

\ a"G0# &/I=$"7= %SD"&# Low
\ ,U!) =67%6= %SD"&# Minimum
\ U=?# ;"#" I/0GS= %SD"&# Low
\ U=?# #%S= %SD"&# Low
\ aG6&#%/6"0 #%S%67 %SD"&# Low
\ ,$=" /I=$Z="; Low
\ c?"T%0%#Y W%#Z #=?# &/SD$=??%/6 High
\ -=?%76 =VV/$# Minimum
\ -=?%76 V0/W &Z"67= Low

(source: S. Ravi, TI, ITC07) 64

32
0'-#/4)5'6/F-#%7,#%)&
\ .==;=; V/$ #=?# ?D"&= =]D0/$"#%/6 >-VUh,U!)@ ="$0Y %6 #Z= ;=?%76 &Y&0=
\ ,I"%0"T%0%#Y /V ?&"6 =6Z"6&=; ;=?%76 "6; ,U!) D"##=$6? /60Y "# #Z=
7"#= 0=I=0 %6 #/;"Yo? ;=?%76 V0/W? %SD/?=? #Z= G?"7= /V 7"#=O0=I=0
=?#%S"#/$? V/$ #=?# D/W=$
\ 1/6I=6#%/6"0 V0/W ";/D#=; #/ D=$V/$S =?#%S"#%/6 %? ?%SG0"#%/6OT"?=;
\ 9?#%S"#%/6 %? D=$V/$S=; "# I"$%/G? !gU &/$6=$?
\ 1Z"00=67=? V/$ SG0#%OS%00%/6 7"#= J/1?
Ü U%S=O&/6?GS%67 ^^
Ü -GSD ?%f=? &"6 T= I=$Y 0"$7= ^^
\ UZ= W=%7Z#=; #$"6?%#%/6 S=#$%& >8J,@ %? 5G%&' TG# "DD$/]%S"#=
Faster and low cost solutions for test power estimation are needed !

65

@)5/4)5'6/2'-%;&/G@42H
Power Consumption Trends

\ 9]D/6=6#%"0(7$/W#Z(%6(#$"6?%?#/$(;=6?%#Y
̇ X/$=(VG6&#%/6"0%#Y
\ KG#(0%6="$($=;G&#%/6(%6(?GDD0Y(I/0#"7=
̇ ./#(";=5G"#=(#/(D$=I=6#(D/W=$(;=6?%#Y(#/(%6&$="?=

(source: Tirimurti et al., DATE, 2004) 66

33
@)5/4)5'6/2'-%;&/G@42H
The new power-performance paradigm:
̇ 3/W(>V%]=;@(D/W=$(TG;7=#(#/(0%S%#(D/W=$(;=6?%#Y
̇ KG#(=I=$(%6&$="?%67(%6#=7$"#%/6("6;(D=$V/$S"6&=(_

Density 2X Applications
!/W=$ Performance 1.4X Units
Power 1X Users
Cost 0.5X Revenue

Adoption of low-power design and power management techniques

(courtesy: M. Hirech, Synopsys, USA) 67

@)5/4)5'6/2'-%;&/G@42H

JY?#=S(d(,$&Z%#=&#G$= *1(-=?%76(d(*SD0=S=6#"#%/6
̇ g/0#"7=(h(a$=5G=6&Y(J&"0%67 ̇ 10/&'()"#%67
̇
̇ ,$&Z%#=&#G$=(>D"$"00=0E(W=00(S"6"7=;( XG0#%D0=(JGDD0Y(g/0#"7=
D%D=0%6=E(=#&:@ ̇ XG0#%D0=(UZ$=?Z/0;(g/0#"7=

̇ 2#Z=$?(>HhJ(D"$#%#%/6%67E(%6?#$G&#%/6(?=#E( ̇ JGT?#$"#=OK%"?
"07/$%#ZS?E(=#&:@ ̇ !/W=$()"#%67

̇ 2#Z=$?

1%$&G%#(>3/7%&@(-=?%76 !$/&=??(U=&Z6/0/7Y
̇ 3/W(!/W=$(1=00(3%T$"$Y ̇ +=;G&=(g;;
̇ )"#=(?%f%67(>#/(=5G"0%f=(D"#Z?@ ̇ UZ$=?Z/0;(g/0#"7=(2D#%/6
̇ KGVV=$(%6?=$#%/6(#/($=;G&=(?0=W ̇ 3/W(1"D"&%#"6&=(-%=0=&#$%&

̇ 3/7%&($=?#$G&#G$%67(#/("I/%;(Z"f"$;? ̇ .=W()"#=(2]%;=(X"#=$%"0

̇ X=S/$Y(K%#(1=00("6;(1/SD%0=$ ̇ U$"6?%?#/$(J%f%67

̇ 2#Z=$? ̇ 2#Z=$?

68

34
@)5/4)5'6/2'-%;&/G@42H

Power reduction
Main LPD techniques
-Y6"S%& 3="'"7=
10/&'(7"#%67
!/W=$(7"#%67
XG0#%Og/0#"7=(;/S"%6?
XG0#%OUZ$=?Z/0;(&=00?

These techniques are often combined together to

achieve the maximum power optimization value

69

4)5'6/2"6%&;/0'-#/<
Even more critical for Low-Power Design !!

!/W=$OX"6"7=S=6# +=0"#%I=0Y
>Z"$;W"$=@ H%7Z=$
>?/V#W"$=@ 9]&=??%I=
)G"$; U=?#(!/W=$
K/G6;
PM structures
,&#G"0 often disabled
X"]%SGS during test
!/W=$ application

aG6&#%/6"0(!/W=$ aG6&#%/6"0(!/W=$ U=?#(!/W=$

>./$S"0(-=I%&=@ >3/WO!/W=$(-=I%&=@
(courtesy: X. Wen, KIT) 70

35
>'I"%6'7'&#-/3)6/0'-#/)3 /@42
+=;G&= >=I=6 S/$=@ #=?# D/W=$ TY G?%67 #Z= D/W=$
S"6"7=S=6# >!X@ %6V$"?#$G&#G$= >"6;h/$ "DD0Y%67 #Z=
D$=I%/G? ;=;%&"#=; ?/0G#%/6?@
!$=?=$I= #Z= VG6&#%/6"0%#Y /V #Z= #=?# %6V$"?#$G&#G$=
U=?# #Z= D/W=$ S"6"7=S=6# >!X@ ?#$G&#G$=?

And still target:

H%7Z V"G0# &/I=$"7=E ?Z/$# #=?# "DD0%&"#%/6 #%S=E ?S"00 #=?# ;"#"
I/0GS=E 0/W "$=" /I=$Z=";E =#& _ WZ%0= S"'%67 #=?# D/W=$
;%??%D"#%/6 >;Y6"S%& "6; 0="'"7=@ &/SD"$"T0= #/ VG6&#%/6"0 D/W=$

71

>'?".%&;/0'-#/4)5'6/)3 /@42
Main classes of dedicated solutions

U=?#(J#$"#=7%=?(V/$(XG0#%Og/0#"7=(-=?%76?
U=?#(J#$"#=7%=?(V/$()"#=;(10/&'(-=?%76?
U=?#(/V(!/W=$(X"6"7=S=6#(>!X@(J#$G&#G$=?

Objective (again)

Make test power dissipation comparable to functional power

72

36
 >'?".%&;/0'-#/4)5'6/)3 /@42
Main classes of dedicated solutions

U=?#(J#$"#=7%=?(V/$(XG0#%Og/0#"7=(-=?%76?
U=?#(J#$"#=7%=?(V/$()"#=;(10/&'(-=?%76?
U=?#(/V(!/W=$(X"6"7=S=6#(>!X@(J#$G&#G$=?

73

0'-#/3)6/9"$#%1J)$#,;'/2'-%;&-
Multi-Voltage Design Styles

OFF PWR
CTRL
0.7 – 0.9V
0.9V 0.9V
OFF
0.7V 0.9V 0.7V 0.9V 0.7V
0.9
V

Multi-Voltage Multi-Voltage Dynamic Voltage

Multi-supply with power gating Frequency Scaling
(DVFS)
\ 1$="#%/6(/V(qD/W=$(%?0"6;?r(
\ g;;(?&"0%67($=?G0#?(%6(5G";$"#%&(D/W=$($=;G&#%/6(>!l'1gFV@
\ 3=I=0(?Z%V#=$?(#/(0=#(?%76"0?(&$/??(D/W=$(;/S"%6(T/G6;"$%=?
74

37
0'-#/3)6/9"$#%1J)$#,;'/2'-%;&-
Example 1: Multi-Voltage Aware Scan Cell Ordering

\ XG0#%OI/0#"7="W"$= ?&"6 &Z"%6 "??=ST0Y &/6?%;=$? #Z= I/0#"7=

;/S"%6? /V ?&"6 &=00? ;G$%67 ?&"6 &=00 /$;=$%67 ?/ "? #/ S%6%S%f= #Z=
/&&G$$=6&= /V &Z"%6? #Z"# &$/?? I/0#"7= ;/S"%6?
J&"6(&Z"%6("??=ST0Y
\ X%6%S%f= 6GST=$ >"$=" /I=$Z=";@ Ordering Logical Physical Multi-
Voltage
/V 0=I=0 ?Z%V#=$? >TY BA`@ Position

1 ,P ,F ,F

Design (1.2V) 2 ,F ,P ,P
J&"6(1=00
3 ,A ,A ,A
A1 C2 4 KP KA 1P
B1
A2 C1
B3
5 KF KP 1F
A3 C3
B2
6 KA KF 1A

Block A Block B Block C 7 1P 1P KF

0.9V 1.2V 0.9V
8 1F 1F KA
9 1A 1A KP

\ !$=?=6#=; TY JY6/D?Y? %6 s23!9 I/0:P 6

P ,D$%0 FCCR 3=I=0(?Z%V#=$
"6; %SD0=S=6#=; %6 JY6/D?Y? )"0"]Yt U=?#
75

0'-#/3)6/9"$#%1J)$#,;'/2'-%;&-
Example 2: Power-Aware Scan Chain Assembly
\ U=?# %6V$"?#$G&#G$=? 0%'= ?&"6 &Z"%6 /$ U,X S"Y &$/?? ?=I=$"0 D/W=$
;/S"%6? "6; &"6 T= T$/'=6 %V ?/S= /V #Z=?= ;/S"%6? "$= #=SD/$"$%0Y
D/W=$=;O;/W6 V/$ 0/WOD/W=$ &/6?#$"%6#?
\ KYD"??SG0#%D0=]=$? "00/W #=?#%67 /V ?D=&%V%& D/W=$ ;/S"%6? %6
XJXg =6I%$/6S=6# >?W%#&Z=;O/VV D/W=$ ;/S"%6? "$= TYD"??=;@
\ !$=?=$I= #=?# VG6&#%/6"0%#Y ^

\ !$=?=6#=; TY 1";=6&= e *U1 FCCN

"6; %SD0=S=6#=; %6 1";=6&= EncounterTM

76

38
0'-#/3)6/9"$#%1J)$#,;'/2'-%;&-
Example 3: Voltage scaling in scan mode

\ -G$%67 ?&"6 ?Z%V#%67E #Z= &/ST%6"#%/6"0 0/7%& 6==;? 6/# S==# #%S%67
\ )/"0L $=OG?= #Z= -gJ %6V$"?#$G&#G$= %6 #=?# S/;= #/ D$/D/?= "
?&"0=;OI/0#"7= ?&"6 #=?# ?&Z=S=: UZ= 7/"0 %? #/ $=;G&= ;Y6"S%& "6;
0="'"7= D/W=$ ;%??%D"#%/6 TY G?%67 " 0/W=$ ?GDD0Y I/0#"7= ;G$%67
?&"6 ?Z%V#%67
\ ,#O?D==; #=?#%67 W%#Z " 321 /$ " 32J #=?# ?&Z=S= %? "??GS=;E "?
W=00 "? #Z= V"&# #Z"# #Z= ?&"6 ?Z%V# ?D==; %? G?G"00Y 0/W=$ #Z"6 #Z=
VG6&#%/6"0 >&"D#G$=@ ?D==;
̇ 9]"SD0=L VG6&#%/6"0 ?GDD0Y I/0#"7= >gS"]@ l P:P gE VG6&#%/6"0 V$=5G=6&Y
>aS"]@ l RCC XHfE #Z$=?Z/0; I/0#"7= /V ?&"6 aa? >g#@ l C:AR gE ?Z%V#
a$=5G=6&Y >a?Z%V#@ l PFR XHf s g?Z%V# l C:[AR g
\ !$=?=6#=; TY U* e *U1 FCCM
77

0'-#/3)6/9"$#%1J)$#,;'/2'-%;&-
Example 3 (cont’d): Voltage scaling in scan mode

1/6I=6#%/6"0(g/0#"7=(J&"0%67(,DD"$"#G?

3gu?&"6L(1/6#$/0(?%76"0(V$/S(#=?#=$(V/$(0/WOI/0#"7=(?&"6
!XJ&"6L(JZ%V#(g/0#"7=(J&"0%67(,DD"$"#G?

,$/G6; QR` $=;G&#%/6 /V ;Y6"S%& >"I=$"7= "6; D="'@ D/W=$ "6; BC` $=;G&#%/6 /V
0="'"7= D/W=$E W%#Z 6=70%7%T0= DZY?%&"0 ;=?%76 %SD"&# "6; S%6%SGS "$=" /I=$Z=";

78

39
 0'-#/3)6/9"$#%1J)$#,;'/2'-%;&-
Example 4: Power Domain Test Planning

Objective: Power
Power
Controller
Controll

1$="#=(;%?#%6&#(#=?#(
PD1 PD2 PD3 PD4
S/;=?(>#=?#(D"$#%#%/6%67@(
V/$(D/W=$(;/S"%6? S
I
SC1 SC2 SC3 SC4 S
O

Test
Controller

XG0#%OS/;=(-aU("$&Z%#=&#G$=
!/W=$

,00(!-? U$";=/VV
2. U=?#(#%S=(I?(!/W=$(
&/6?GSD#%/6
2.9(!-
"#("(#%S=

U=?#("DD0%&"#%/6(#%S=
(Source: M. Hirech, Synopsys, DATE, 2008) 79

>'?".%&;/0'-#/4)5'6/)3 /@42
Main classes of dedicated solutions

U=?#(J#$"#=7%=?(V/$(XG0#%Og/0#"7=(-=?%76?
U=?#(J#$"#=7%=?(V/$()"#=;(10/&'(-=?%76?
U=?#(/V(!/W=$(X"6"7=S=6#(>!X@(J#$G&#G$=?

80

40
0'-#/3)6/A,#'?/($).K/2'-%;&-
Basic Clock Gating Design

‚ ./# "00 aa? 6==; #/ T=

#$%77=$=; #/ D=$V/$S " VG6&#%/6
>=:7:E #Z= &"S=$" &/6#$/0 0/7%&
%6 " S/T%0=ODZ/6= J/1 &"6 T=
GClk
%6"&#%I= ;G$%67 " &"00@:

‚ )"#%67O/VV #Z= &0/&' #/ VG6&#%/6"00YO

Clock Gator
6/6&/6#$%TG#%67 aa? $=;G&=?
;Y6"S%& D/W=$ ;%??%D"#%/6E not
only in logic portions but also
in clock trees (> 50%):
10'
- ‚ 26=(/V(#Z=(S"p/$(#=&Z6%5G=?(V/$(((
b $=;G&%67(VG6&#%/6"0(D/W=$:

‚ 8%;=0Y ";/D#=; "6; ?GDD/$#=;

)10'

TY =]%?#%67 9-, #//0?:

81

0'-#/3)6/A,#'?/($).K/2'-%;&-
Impact of Clock Gating on Test

\ 10/&' 7"#%67 D$=I=6#? "00 ?&"6 aa? V$/S T=%67 "&#%I= "# #Z= ?"S= #%S=:
\ Impact on Shift Mode
Negative › J&"6 ?Z%V# $="0%f=; #Z$/G7Z ?Z%V# $=7%?#=$? S"Y T=&/S=
%SD/??%T0= %V ?/S= aa? "$= %6"&#%I=:

X
Shift Operation Guarantee Needed
DfT for Clock Gating Logic

\ Impact on Capture Mode

Positive › -Y6"S%& D/W=$ &"6 T= $=;G&=;:

Good for LTC Power Reduction

Static In-ATPG Techniques X

Dynamic In-ATPG Techniques

Post-ATPG X-Filling Techniques X 82

41
0'-#/3)6/A,#'?/($).K/2'-%;&-
Example 1: DfT for Clock Gating Logic

\ Shift Mode >SE l P@L ,00 ?&"6 aa? SG?# T= "&#%I= #/ V/$S /6= /$ S/$=
?&"6 &Z"%6? #/ ?Z%V#O%6 #=?# ?#%SG0G? h ?Z%V#O/G# #=?# $=?D/6?=: 10/&'
7"#%67 0/7%& 6==;? #/ T= /I=$$%;;=6 >TY SE@ %6 ?Z%V# S/;=:
\ Capture Mode >SE l C@L J&"6 aa? "$= "00/W=; #/ T= &/6#$/00=; TY
&0/&' 7"#%67 0/7%&: ./#Z%67 6==;? #/ T= ;/6=:
SE

Clock Gator

\ ,G#/S"#%&"00Y %SD0=S=6#=; TY 1";=6&= "6; JY6/D?Y? -VU #//0?: 83

0'-#/3)6/A,#'?/($).K/2'-%;&-
Example 1 (cont’d): DfT for Clock Gating Logic
SE
1
‚
1
-%?"T0= &0/&' 7"#%67 %6 shift mode
1 >SE l P@L c6&/6;%#%/6"00YO2. 10/&'

Shift Register Operation

SE
0
‚ 96"T0= &0/&' 7"#%67 %6 capture mode
>SE l C@L 1/6;%#%/6"00YO2. 10/&'

LTC Power Reduction

84

42
0'-#/3)6/A,#'?/($).K/2'-%;&-
Example 2: LTC Power Reduction by Clock Gating

‚ ,(default value %?("(I"0G=(#/(T=("??%76=;(#/("6(%6DG# %6(/$;=$(#/(7"#=O/VV("(&0/&':

î A preset value is to be used to fill an X-bit in a test cube:

‚ a0/W(V/$(/T#"%6%67(;=V"G0#(I"0G=?(V/$(&0/&'(7"#%67L
î Identify all clock gators:
î For each clock gator, calculate a set of input settings that set the clock off:
î The values in each input setting are default values..

‚ a0/W(V/$(G?%67(;=V"G0#(I"0G=?(V/$(&0/&'(7"#%67L(
î Generate a test cube for fault detection:
î Assign default values to the X-bits in the test cube:(
>If there are multiple choices of default values, use the one that can turn-off more FFs.@

(source: R. Illman et al., Proc. LPonTR, pp. 45-46, 2008) 85

0'-#/3)6/A,#'?/($).K/2'-%;&-
Example 2 (cont’d): LTC Power Reduction by Clock Gating

Default Values
S1 = 0 / S2 = 0
S1 = 1 / S2 = 1

Test Cubes after ATPG Test Cubes after Assigning Default Values
>JPlC(h(JFlC@

(source: R. Illman et al., Proc. LPonTR, pp. 45-46, 2008) 86

43
0'-#/3)6/A,#'?/($).K/2'-%;&-
Example 2 (cont’d): LTC Power Reduction by Clock Gating

Circuit Statistics
NBj(aa?
[(J&"6(10/&'?
FFCC(10/&'()"#/$?

Wh/(&0/&'(7"#%67

W(&0/&'(7"#%67

g=&#/$? g=&#/$? g=&#/$?

‚ UZ=(6GST=$(/V("&#%I=(&0/&'?("$=($=;G&=;(TY(S/$=(#Z"6(RC`:
‚ 3U1(#/770=("&#%I%#Y(%?($=;G&=;(TY(AR`:
‚ a"G0#(&/I=$"7=("6;(#=?#(?=#(?%f=($=S"%6("0S/?#(G6&Z"67=;:
(source: R. Illman et al., Proc. LPonTR, pp. 45-46, 2008) 87

0'-#/3)6/A,#'?/($).K/2'-%;&-
Summary
‚ aG6&#%/6"0(&0/&'(7"#%67(%?(%6;%?D=6?"T0=(%6($=;G&%67(;Y6"S%&(D/W=$:(

‚ aG6&#%/6"0(&0/&'(7"#%67(0/7%&(6==;?(#/(T=(S/;%V%=;(%6(/$;=$(#/(7G"$"6#==(
&/$$=&#(/D=$"#%/6(%6 shift mode:

‚ 10/&'(7"#%67(&"6(T=(G?=;(%6(capture mode #/($=;G&=(3U1(D/W=$:

î J#"#%&(*6O,U!)(U=&Z6%5G=?
>Assign pre-determined clock-gator disabling values to don’t-care bits
(X-bits) in a test cube initially generated for fault detection.@

î !/?#O,U!)(4Oa%00%67(U=&Z6%5G=?
>Find and assign proper logic values to don’t-care (X-bits) in a test
cube so as to disable as many clock gators as possible.@

88

44
 >'?".%&;/0'-#/4)5'6/)3 /@42
Main classes of dedicated solutions

U=?#(J#$"#=7%=?(V/$(XG0#%Og/0#"7=(-=?%76?
U=?#(J#$"#=7%=?(V/$()"#=;(10/&'(-=?%76?
U=?#(/V(!/W=$(X"6"7=S=6#(>!X@(J#$G&#G$=?

89

0'-#/3)6/4)5'6/9,&,;'7'&#/:#6".#"6'-
Typical Power Management (PM) Structures
!/W=$(1/6#$/0(3/7%&(¦ !/W=$(JW%#&Z( *?/0"#%/6(1=00(¢

3=I=0(JZ%V#=$(£ X
X
J#"#=(+=#=6#%/6(+=7%?#=$(¡

‚ 1/6;%#%/6"00Y(#G$6%67(/6(/$(/VV(D/W=$(;/S"%6?@(#/($=;G&=(;Y6"S%&("6;(?#"#%&(D/W=$:
‚ 1"6(T=(;=?&$%T=;(%6(c!a >Unified Power Format@(/$(1!a >Common Power Format@:
‚ !X(?#$G&#G$=?(>¦\£@($=5G%$=(;=;%&"#=;(-VU(S=#Z/;?("6;(#=?#(D"##=$6?: 90

45
0'-#/3)6/4)5'6/9,&,;'7'&#/:#6".#"6'-
Example 1: Test for Power Switches

Header Switch Footer Switch Symmetric Switch Segmented Switch

Header Switch / Footer Switch / Symmetric Switch

‚ ,0?/(&"00=;(?0==D(#$"6?%?#/$? "6;(G?=;(#/(?ZG#(;/W6(T0/&'?(>D/W=$(;/S"%6?@(#Z"#
"$=(6/#(%6(G?=(>%;0=(S/;=@E(Z=6&=($=;G&%67(0="'"7=(D/W=$("6;(;Y6"S%&(D/W=$:(
‚ JZ/G0;(T=(0"$7=(=6/G7Z(#/(D$/I%;=(?GVV%&%=6#(&G$$=6#(#/(#Z=(&%$&G%#:

Segmented Switch
‚ *6;%I%;G"0(?W%#&Z(#$"6?%?#/$?(&"6(T=(?S"00:(
‚ !$=V=$"T0=(%6(D$"&#%&=(;G=(#/(&/6&=$6?("T/G#(0"Y/G#E(;=?%76(V/$ S"6GV"&#G$"T%0%#YE(
"6;(0%S%#%67(%6$G?Z(&G$$=6#(WZ=6(?W%#&Z%67(/6("(D/W=$(;/S"%6:
91

0'-#/3)6/4)5'6/9,&,;'7'&#/:#6".#"6'-
Example 1 (cont’d): Test for Power Switches

from power
control logic

\ !"##=$6(P >Test for Short@L(TE l(P(h(standby_t l(P

î UG$6O/VV(#Z=(D/W=$(?W%#&Z:(,V#=$(?GVV%&%=6#(;%?&Z"$7=E((((
g&/$=(?Z/G0;(T=(SG&Z(0/W=$(#Z"6(g--E("6;(#ZG?
Out >V"G0#OV$==@(l(P(h(Out >V"G0#Y@(l(C

\ !"##=$6(F(>Test for Open@L(TE l(P(h(standby_t l(C

î UG$6O/6(#Z=(D/W=$(?W%#&Z:(g&/$=(?Z/G0;(T=(&0/?=(#/(g--E(
"6;(#ZG?(Out >V"G0#OV$==@(l(P h(Out >V"G0#Y@(l(C

(source: Goal (NXP) et al., Proc. ETS, pp. 145-150, 2006) 92

46
0'-#/3)6/4)5'6/9,&,;'7'&#/:#6".#"6'-
Example 2: Parametric Test of Micro Switches

\ !$=?=6#=; TY JUO9$%&?/6 >J/DZ%"@ "#

*6#=$6"#%/6"0 U=?# 1/6V=$=6&= FCCN:
\ J%670=O;%= A) S/T%0= DZ/6= T"?= T"6;
1Z%D S";= %6 [R6S #=&Z6/0/7Y
\ *6&0G;=? SG0#%S=;%" V="#G$=?E ?G&Z "?
I%;=/ ;=&/;=$E X!A D0"Y=$E &"S=$"E
7"S=?E "6; ;=?%76=; #/ T= =]#$=S=0Y
0/W D/W=$:
\ +G?Z &G$$=6# ;G$%67 D/W=$ GD "›
?D=&%V%& VG6&#%/6"0 S/;= "› #=?# S/;=
Z"? #/ S"D VG6&#%/6"0 S/;= ^

93

0'-#/3)6/4)5'6/9,&,;'7'&#/:#6".#"6'-
Example 2 (cont’d): Parametric Test of Micro Switches

\ UZ= S%&$/ ?W%#&Z=? "$= ;"%?YO&Z"%6=;: a%$?#E "00 #Z= 9!8+ &/6#$/0 ?%76"0?
"$= D$/D"7"#=; %6 #Z= &Z"%6: UZ%? 7%I=? " D$/7$=??%I= $"SDOGD /V #Z=
g;;JW%#&Z=;: UZ=6E #Z= 913j &/6#$/0 ?%76"0 V/00/W?E #G$6%67 v/6o "00 #Z=
#$"6?%?#/$? /V #Z= S%&$/ ?W%#&Z=?:
\ U=?#%67 S%&$/O?W%#&Z=? %6;%I%;G"00Y %? 6==;=; #/ ;=#=&# $=?%?#%I= ;=V=&#? %6
="&Z /V #Z=SE "6; #=?#%67 #Z= S%&$/ ?W%#&Z=?o &/6#$/0 &Z"%6 %? %SD/$#"6# #/
=6?G$= #Z= &Z"%6 %? 6/# T$/'=6:
94

47
0'-#/3)6/4)5'6/9,&,;'7'&#/:#6".#"6'-
Example 2 (cont’d): Parametric Test of Micro Switches

\ -VU #/ ";; &/6#$/00"T%0%#Y "6; /T?=$I"T%0%#Y

\ U=?# =6I%$/6S=6# S/;=0%67 6==;=; #/ "00/W +/VVh+/6 S="?G$=S=6#
\ U=?# #%S= V/$ PRC &0G?#=$? >="&Z &/SD/?=; /V P[ ?W%#&Z=?@L A[ S? 95

0'-#/3)6/4)5'6/9,&,;'7'&#/:#6".#"6'-
Example 3: Test for State Retention Registers (SRR’s)
‚ ,(J++(&=00(%?(V/$('==D%67(%#?(?#"#=(WZ=6(#Z=(D/W=$(?GDD0Y(%?(#G$6=;(/VV:
‚ J&"6(VG6&#%/6(&"6(T=(;=?%76=;(%6#/("(J++(&=00:

g;;
+=?#/$=
J"I=
J&"6O*6
Xc4

J* b -"#=O2G#

10/&'O, 1j" Master

Latch
-"#=O*6 -
10/&'OK 1j&
- b J&"6O2G#
J"I= Retention
)6; Latch
10/&'O1 1jT

96

48
0'-#/3)6/4)5'6/9,&,;'7'&#/:#6".#"6'-
Example 3 (cont’d): Test for State Retention Registers (SRR’s)

SRR

Retention Capability Test

>P@ JZ%V#O%6(I"0G=(V #/(J++: >R@(UG$6O/6(!/W=$(-/S"%6(P("V#=$("(V=W(&Y&0=?:
(2) 96"T0=($=#=6#%/6(TY(?=##%67(Save #/(P: >[@(-%?"T0=(#Z=(%?/0"#%/6(&=00:
>A@(96"T0=(#Z=(%?/0"#%/6(&=00: >M@(-%?"T0=($=#=6#%/6(TY(?=##%67(Restore #/(P:
>Q@(UG$6O/VV(!/W=$(-/S"%6(P: >N@(JZ%V#(/G#(#Z=(I"0G=(/V(J++ "6;(&Z=&'(%V(%# %?(V:
Repeat for V = 0 and V = 1
2#Z=$(#=?#?E(?G&Z("?(#=?#(V/$($=#=6#%/6($/TG?#6=??(#/(#Z=(?#"#=(=0=S=6#o?(
&0/&'E("?Y6&Z$/6/G?(?=#h$=?=#E(=#&:E(S"Y("0?/(6==;(#/(T=("DD0%=;: 97

0'-#/3)6/4)5'6/9,&,;'7'&#/:#6".#"6'-
Example 4: Test for Isolation Cells - (1)

OUT

>P@(UG$6O/VV(!/W=$(-/S"%6(P(>SLEEP_1 l(P@:
>F@(UG$6O/6(!/W=$(-/S"%6(F(>SLEEP_2 l(C@:
>A@(J=#(P(#/(ISO_1 "6;(&Z=&'(%V(#Z=(%?/0"#%/6(&=00(/G#DG#(>OUT@(%?(P:

98

49
0'-#/3)6/4)5'6/9,&,;'7'&#/:#6".#"6'-
Example 4: Test for Isolation Cells - (2)
Check for 1
Power Domain ON
OR Power Domain ON
Power Domain OFF

Check for 0
Power Domain ON
AND Power Domain ON
Power Domain OFF

Check for 0 and 1

Power Domain ON
FF Power Domain ON
Power Domain OFF
99

0'-#/3)6/4)5'6/9,&,;'7'&#/:#6".#"6'-
Example 5: Test for Level Shifters

(VDD-1, VDD-2, ) (VDD-a, VDD-b, )

Level Shifter

Power Domain 1 Power Domain 2

Test as a whole under all power supply voltage combinations

of Power Domain 1 and Power Domain 2.

100

50
0'-#/3)6/4)5'6/9,&,;'7'&#/:#6".#"6'-
Example 6: Test for Power Mode Control Logic in SRAMs

\ J#G;Y D=$V/$S=; /6 *6#=0 X1 D$/;G&#? %6 FCPP

corecell
array
wordline
driver
corecell
array
\ *SD"&# /V $=?%?#%I=O/D=6 ;=V=&#? /6 #Z= !X1 0/7%&
\ -=V%6%#%/6 /V "DD$/D$%"#= V"G0# S/;=0? >aaX@
\ !$/D/?"0 /V " 6=W X"$&Z #=?# >3w@ ?/0G#%/6

IO control IO

Low-Power SRAM 101

0'-#/3)6/4)5'6/9,&,;'7'&#/:#6".#"6'-
Summary
‚ X/$=("6;(S/$=(D/W=$(S"6"7=S=6#(?#$G&#G$=?("$=(G?=;(%6(I"$%/G?(*1(
;=?%76?(%6(/$;=$(#/($=;G&=(D/W=$(>;Y6"S%&("6;(?#"#%&@(;%??%D"#%/6:(

‚ 1/6I=6#%/6"0(,U!)(;/=?(6/#(#"$7=#(D/W=$(S"6"7=S=6#(?#$G&#G$=?E(
0=";%67(#/(D/#=6#%"0(5G"0%#Y(D$/T0=S?:(

‚ UZ=$=(%?("(?#$/67(6==;(#/(VG00Y(G6;=$?#"6;(#Z=(T"?%&?(/V(I"$%/G?(D/W=$(
S"6"7=S=6#(?#$G&#G$=?("6;(#Z=%$(/D=$"#%/6(S/;=?:

‚ JD=&%"0(&/6?%;=$"#%/6?("6;(=I=6(6=W("07/$%#ZS?("$=(6==;=;(#/(VG00Y(
#=?#(I"$%/G?(D/W=$(S"6"7=S=6#(?#$G&#G$=?:

10/&'()"#%67(3/7%&(>10/&'()"#/$E(1/6#$/0(3/7%&@
!/W=$()"#%67(3/7%&
î !Xc(>!/W=$(X"6"7=S=6#(c6%#@
î !/W=$(JW%#&Z(
î J#"#=(+=#=6#%/6(+=7%?#=$E(*?/0"#%/6(1=00E(3=I=0(JZ%V#=$
!/W=$(-%?#$%TG#%/6(.=#W/$'
102

51
=78,.#/)3 /90J/2'-%;&/)&/0'-#/
\ UZ$=?Z/0;(I/0#"7=(?&"0=?(;/W6(>W%#Z(?GDD0Y(I/0#"7=@(#/(;=0%I=$(&%$&G%#(
D=$V/$S"6&=E(TG#(0="'"7=(D/W=$(%6&$="?=?(=]D/6=6#%"00Y(W%#Z(#Z$=?Z/0;(
I/0#"7=($=;G&#%/6(› ?D==;(&/?#(#/(;=&$="?=(0="'"7=(^^
\ XUg(;=?%76?(G?=(Z%7ZOg# &=00?(#/(;=&$="?=(0="'"7=(&G$$=6#(WZ=$=(
D=$V/$S"6&=(%?(6/#(&$%#%&"0(>#$"6?%?#/$?(/6(6/6O&$%#%&"0(D"#Z?@(
\ 3="'"7=(D/W=$($=;G&#%/6(WZ%0=(S==#%67(#%S%67("6;(6/("$="(/I=$Z=";
\ 8=00(=?#"T0%?Z=;("6;(?GDD/$#=;(TY(=]%?#%67(9-,(#//0?

3/W(g#

./$S(g# !ZY:(JY6:

H%7Z(g#

(source: CADENCE, 2007) 103

=78,.#/)3 /90J/2'-%;&/)&/0'-#/
\ KY G?%67 ?G&Z D/W=$ /D#%S%f"#%/6 #=&Z6%5G=?E S/$= D"#Z? T=&/S=
&0G?#=$=; %6 " 6"$$/W $=7%/6 "$/G6; #Z= &Y&0= #%S=E $=?G0#%67 %6 " 0"$7=
D/DG0"#%/6 /V D"#Z? WZ%&Z "$= ?=6?%#%I= #/ ?S"00 ;=0"Y D=$#G$T"#%/6?
Ü !-a ?=0=&#%/6 S/$= &/SD0=] 1Y&0=(U%S=
./6O&$%#%&"0(D"#Z?(#/(

Ü
+=?G0#"6#(D"#Z(
T=(?0/W=;(;/W6
;%?#$%TG#%/6
X/$= #=?# ;"#" "$= 6==;=;
x(/V(D"#Z?

Ü J=6?%#%I%#Y #/ I"$%"#%/6? 1$%#%&"0(D"#Z?(

#/(T=(V%]=;

-=0"Y

\ !J. Z"? " ?%76%V%&"6# %SD"&# /6 #Z= #%S%67 T=Z"I%/$

Ü .==; #/ %6#=7$"#= !J. =VV=&#? %6 ;=0"Y #=?# D"##=$6 7=6=$"#%/6

Solutions for high quality at-speed fault coverage are needed !

104

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4)5'61B5,6'/2L0/0))$-

\ Synopsys:
̇ )"0"]Yt U=?# %? " &/SD$=Z=6?%I= #=?# "G#/S"#%/6 ?/0G#%/6:
̇ -aU 1/SD%0=$ "6; %#? 0/W D/W=$ V="#G$=? >V/$ S/$= ;=#"%0? /6 #Z%?
#//0?E ?== q!/W=$ "6; -=?%76 V/$ U=?#L , -=?%76 ,G#/S"#%/6
!=$?D=&#%I=rE ,: -= 1/00= =# "0E s/G$6"0 /V 3/W !/W=$ 90=&#$/6%&?
>s23!9@E g/0: PE . PE ,D$%0 FCCR@
̇ -aU X,4 "6; %#? 0/W D/W=$ V="#G$=? >V/$ S/$= ;=#"%0? /6 #Z%?
#//0?E ?== q-aU X,4 "6; !/W=$rE +: j"DG$ =# "0E s/G$6"0 /V 3/W !/W=$
90=&#$/6%&? >s23!9@E g/0: AE . FE ,G7G?# FCCM@
̇ U=#$"X,4n O D/W=$O"W"$= #=?# D"##=$6? V/$ ;=V=&# ;=#=&#%/6
̇ -=#"%0?
http://www.synopsys.com/Tools/Implementation/RTLSynthesis/Test/Pages/def
ault.aspx

105

4)5'61B5,6'/2L0/0))$-

\ Mentor:
̇ U=??=6#t a"?#J&"6t "6; U=??=6#t U=?#j/SD$=??t D$/I%;=
&/SD$=Z=6?%I= 0/WOD/W=$ "6; D/W=$O"W"$= #=?# ?/0G#%/6?:

̇-=#"%0? "# http://www.mentor.com/products/silicon-yield/logic_test/

\ Cadence:
̇ 96&/G6#=$n U=?#E " '=Y #=&Z6/0/7Y %6 #Z= 1";=6&=n
96&/G6#=$ ;%7%#"0 *1 ;=?%76 D0"#V/$S
̇ U/ ?GDD/$# S"6GV"&#G$%67 #=?# /V 0/WOD/W=$ ;=I%&=?E 96&/G6#=$ U=?#
G?=? D/W=$ %6#=6# %6V/$S"#%/6 #/ &$="#= ;%?#%6&# #=?# S/;=?
"G#/S"#%&"00Y V/$ D/W=$ ;/S"%6? "6; ?ZG#O/VV $=5G%$=S=6#?:
̇ -=#"%0?
http://www.cadence.com/products/ld/test_architect/pages/default.aspx

106

53
()&.$"-%)&
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VG6&#%/6"0%#Y "$= 6==;=; ^^

107

Thank You !

108

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