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COURSE MATERIAL

LOW POWER VLSI CIRCUITS AND

SUBJECT SYSTEMS (EC20APE703)

UNIT 3

COURSE B.TECH

DEPARTMENT ECE

SEMESTER 41

PREPARED BY Dr. G. PADMA PRIYA

(Faculty Name/s) Associate Professor

Version V-1

PREPARED / REVISED DATE 28-08-2023

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TABLE OF CONTENTS – UNIT 3

S. NO CONTENTS PAGE NO.
1 COURSE OBJECTIVES 1
2 PREREQUISITES 1
3 SYLLABUS 1
4 COURSE OUTCOMES 1
5 CO - PO/PSO MAPPING 2
6 LESSON PLAN 2
7 ACTIVITY BASED LEARNING 2
8 LECTURE NOTES 2
3.1 SOURCES OF POWER DISSIPATION: INTRODUCTION 2
3.2 SHORT-CIRCUIT POWER DISSIPATION 4
3.3 SWITCHING POWER DISSIPATION 5
3.4 GLITCHING POWER DISSIPATION 6
3.5 LEAKAGE POWER DISSIPATION 7
9 PRACTICE QUIZ 8
10 ASSIGNMENTS 9
11 PART A QUESTIONS & ANSWERS (2 MARKS QUESTIONS) 9
12 PART B QUESTIONS 11
13 SUPPORTIVE ONLINE CERTIFICATION COURSES 11
14 REAL TIME APPLICATIONS 12
15 CONTENTS BEYOND THE SYLLABUS 12
16 PRESCRIBED TEXT BOOKS & REFERENCE BOOKS 12
17 MINI PROJECT SUGGESTION 12

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1. Course Objectives
The objectives of this course is to

1. Learn the operation of MOS transistor in Triode, Saturation and Cut-

off regions.

2. Learn about the implementation of MOS dynamic circuits.

3. Learn the various types of power dissipations in a MOS transistor.

4. Enable the students to learn about the Scaling Models and Scaling
factors.

5. Study in detail about the various approaches for minimizing leakage

power MOS transistor circuits.

2. Prerequisites
Students should have knowledge on
1. Electronic Devices and Circuits
2. VLSI Design

3. Syllabus
UNIT III
Sources of Power Dissipation:
Introduction, short-circuit power dissipation, switching power dissipation, glitching
power dissipation, leakage power dissipation.

4. Course outcomes
After completion of this subject, students will be able to
CO1: Interpret the structure and various electrical characteristics of
MOS transistor.
CO2: Compare Voltage–Current and transfer characteristics of
inverters of different configurations
CO3: Evaluate the Power dissipation both at circuit level and system
level.
CO4: Summarize the scaling effects of various key parameters of
MOSFET devices.
CO5: Distinguish between standby and run-time leakage power
dissipation.
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5. Co-PO / PSO Mapping
LPVLSI
PO1 PO2 PO3 PO4 PO5 PO6 PO7 PO8 PO9 P10 PO11 PO12 PSO1 PSO2
CS
CO1 3 3 3 3

CO2 3 3 3 3

CO3 3 3 3 3

CO4 3 3 3 3

CO5 3 3 3 3

6. Lesson Plan

Lecture No. Weeks Topics to be covered References

1 Introduction T1

2 Short-Circuit Power Dissipation T1

3 1 Switching Power Dissipation T1

4 Switching Power Dissipation T1

5 Glitching Power Dissipation T1

6 Leakage Power Dissipation T1

7 2 Leakage Power Dissipation T1

8 Revision T1

7. Activity Based Learning

1. Calculation of various power dissipations.
2. Various scaling methods.

8. Lecture Notes
3.1 SOURCES OF POWER DISSIPATION: INTRODUCTION
In order to develop techniques for minimizing power dissipation, it is essential to
identify various sources of power dissipation and different parameters involved
in each of them. Power dissipation may be specified in two ways. One is
maximum power dissipation, which is represented by ―peak instantaneous
power dissipation.‖ Peak instantaneous power dissipation occurs when a circuit
draws maximum power, which leads to a supply voltage spike due to
resistances on the power line. Glitches may be generated due to this heavy
flow of current and the circuit may malfunction, if proper care is not taken to
suppress power-line glitches. The second one is the ―average power
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dissipation,‖ which is important in the context of battery-operated portable
devices. The average power dissipation will decide the battery lifetime. Here,
we will be concerned mainly with the average power dissipation, although the
techniques used for reducing the average power dissipation will also lead to the
reduction of peak power dissipation and improve reliability by reducing the
possibility of power-related failures.

Power dissipation can be divided into two broad categories—static and

dynamic. Static power dissipation takes place continuously even if the inputs
and outputs do not change. For some logic families, such as nMOS and pseudo-
nMOS, both pull-up and pull-down devices are simultaneously ON for low output
level causing direct current (DC) flow. This leads to static power dissipation.
However, in our low-power applications, we will be mainly using
complementary metal–oxide– semiconductor (CMOS) circuits, where this type
of static power dissipation does not occur. On the other hand, dynamic power
dissipation takes place due to a change in input and output voltage levels.

In CMOS circuits, power dissipation can be divided into two broad categories:
dynamic and static. Dynamic power dissipation in CMOS circuits occur when
the circuits are in working condition or active mode, that is, there are changes
in input and output conditions with time. In this section, we introduce the
following three basic mechanisms involved in dynamic power dissipation:

• Short-circuit power: Short-circuit power dissipation occurs when both the

nMOS and pMOS networks are ON. This can arise due to slow rise and fall
times of the inputs.

• Switching power dissipation: As the input and output values keep on

changing, capacitive loads at different circuit points are charged and
discharged, leading to power dissipation. This is known as switching power
dissipation. Until recently, this was the most dominant source of power
dissipation.

• Glitching power dissipation: Due to a finite delay of the logic gates, there are
spurious transitions at different nodes in the circuit. Apart from the abnormal
behavior of the circuits, these transitions also result in power dissipation
known as glitching power dissipation.

Static power dissipation occurs due to various leakage mechanisms. The

following seven leakage current components are
• Reverse-bias p–n junction diode leakage current
• Reverse-biased p–n junction current due to the tunneling of elections from the

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valence bond of the p region to the conduction bond of the n region, known
as band-to-band-tunneling current
• Subthreshold leakage current between source and drain when the gate
voltage is less than the threshold voltage Vt
• Oxide-tunneling current due to a reduction in the oxide thickness
• Gate current due to a hot-carrier injection of elections
• Gate-induced drain-leakage (GIDL) current due to high field effect in the
drain junction
• Channel punch-through current due to close proximity of the drain and the
source in short-channel devices

3.2 Short-Circuit Power Dissipation

When there are finite rise and fall times at the input of CMOS logic gates, both
pMOS and nMOS transistors are simultaneously ON for a certain duration,
shorting the power supply line to ground. This leads to current flow from supply
to ground. Short-circuit power dissipation takes place for input voltage in the
range Vtn< Vin<Vdd - Vtp when both pMOS and nMOS transistors turn ON creating
a conducting path between Vdd and ground (GND). It is analyzed in the case
of a CMOS inverter as shown in Fig. 3.1.

Fig. 3.1: Short-circuit power dissipation during input transition

The short-circuit power is given by

As the clock frequency decides how many times the output changes per
second, the short-circuit power is proportional to the frequency. The short-circuit
current is also proportional to the rise and fall times. Short-circuit currents for
different input slopes are shown in Fig. 3.2. The power supply scaling affects the
short-circuit power considerably because of cubic dependence on the supply
voltage.
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Fig. 3.2: Short-circuit current as a function of input rise/ fall time

3.3 SWITCHING POWER DISSIPATION

There exists capacitive load at the output of each gate. The exact value of
capacitance depends on the fan-out of the gate, output capacitance, and
wiring capacitances and all these parameters depend on the technology
generation in use. As the output changes from a low to high level and high to
low level, the load capacitor charges and discharges causing power
dissipation. This component of power dissipation is known as switching power
dissipation.

Switching power dissipation can be estimated based on the model shown in

Fig. 3.3. Figure 3.3 a shows a typical CMOS gate driving a total output load
capacitance CL. For some input combinations, the pMOS network is ON and
nMOS network is OFF as modeled in Fig. 3.3 b. In this state, the capacitor is
charged to Vdd by drawing power from the supply. For some other input
combinations, the nMOS network is ON and pMOS network is OFF, which is
modeled in Fig. 3.3 c. In this state, the capacitor discharges through the nMOS
network. For simplicity, let us assume that the CMOS gate is an inverter.

Fig. 3.3: Dynamic power dissipation model

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If a square wave of repetition frequency f ( I/T) is applied at the input, average
power dissipated per unit time is given by

3.4 GLITCHING POWER DISSIPATION

In the power calculations so far, we have assumed that the gates have zero delay.
In practice, the gates will have finite delay and this delay will lead to spurious
undesirable transitions at the output. These spurious signals are known as glitches. In
the case of a static CMOS circuit, the output node or internal nodes can make
undesirable transitions before attaining a stable value. Consider the circuit shown in
Fig. 3.4. If the inputs ABC change value from 101 to 000, ideally for zero gate delay
the output should remain at the 0 logic level. However, considering unit gate delay
of the first gate stage, output O1 is delayed compared to the C input. As a
consequence, the output switches to 1 logic level for one gate delay duration. This
transition increases the dynamic power dissipation and this component of dynamic
power is known as glitching power. Glitching power may constitute a significant
portion of dynamic power, if circuits are not properly designed. Usually, cascaded
circuits as shown in Fig. 3.5 a exhibit high glitching power. The glitching power can
be minimized by realizing a circuit by balancing delays, as shown in Fig. 3.5 b. On
highly loaded nodes, buffers can be inserted to balance delays and cascaded
implementation can be avoided, if possible, to minimize glitching power.

Fig. 3.4: Output waveform showing glitch at output O2

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Fig. 3.5: Realization of A, B, C, and D, a in cascaded form, b balanced realization

3.5 LEAKAGE POWER DISSIPATION

When the circuit is not in an active mode of operation, there is static power
dissipation due to various leakage mechanisms. In deep-submicron devices,
these leakage currents are becoming a significant contributor to power
dissipation of CMOS circuits. Figure 3.6 illustrates the seven leakage
mechanisms. Here, I1 is the reverse- bias p–n junction diode leakage current; I 2
is the reverse-biased p–n junction current due to tunneling of electrons from the
valence bond of the p region to the conduction bond of the n region; I3 is the
subthreshold leakage current between the source and the drain when the gate
voltage is less than the threshold voltage Vt; I4 is the oxide-tunneling current due
to a reduction in the oxide thickness; I5 is gate current due to hot-carrier
injection of elections; I6 is the GIDL current due to a high field effect in the drain
junction; and I7 is the channel punch-through current due to the close proximity
of the drain and the source in short-channel devices. These leakage
components are discussed in the following subsections.

Fig. 3.6: Summary of leakage current mechanisms of deep-submicron transistors

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9. Practice Quiz

1. Static power dissipation takes place continuously even if the inputs and outputs do
a) change.
b) not change.
c) Both (a) & (b)
d) None of the above

2. Dynamic power dissipation takes place due to ______ input and output voltage levels.
a) Change
b)Zero
c) fixed
d) None of the above

3. Static power dissipation occurs due to

a) various leakage mechanisms
b) Gate delays
c) Change in input or output
d) None of the above

4. Glitching power dissipation occurs due to

a) a finite delay of the logic gates
b) Sudden glitches in power supply
c) (a) & (b)
d) None of the above

5. GIDL stands for

a) Gate-induced drain-leakage
b) Gate insulator drain layer
c) Gate insulator drain logic
d) Gate induced drain layer

6. The short-circuit power is proportional to the

a) frequency
b) the rise and fall times
c) both (a) & (b)
d) none of the above

7. Constant-field scaling is also known as ________scaling.

a) Zero
b) Half
c) Full
d) none of the above
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8. Power dissipation can be represented as

a) Maximum Power Dissipation
b) Average Power Dissipation
c) Both (a) & (b)
d) None of the above

9. Power dissipation can be classified as

a) Static power dissipation
b) Dynamic power dissipation
c) Both (a) & (b)
d) None of the above

10. Average power dissipated is used to decide ___________

a) Battery lifetime
b) Instantaneous power
c) Dynamic power
d) None of the above

10. Assignments

S.No Question BL CO
Derive the expression for short-circuit power. How does the
1 2 3
short-circuit power vary with the load capacitance?
What is subthreshold leakage current? Briefly explain the
2 3 3
mechanisms that affect subthreshold leakage current.

3 What is glitching power dissipation? How can it be minimized? 3 3

4 Briefly explain various sources of power dissipation. 2 3
What is switching power dissipation? Explain How it can be
5 3 3
minimized.

11. Part A- Question & Answers

S.No Question & Answers BL CO

1 What is Static power dissipation?
Ans. Static power dissipation takes place continuously even if 2 3
the inputs and outputs do not change.
2 What is Short-circuit power dissipation?
Ans. Short-circuit power dissipation occurs when both the nMOS
2 3
and pMOS networks are ON. This can arise due to slow rise
and fall times of the input signals.
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3 What is Switching power dissipation?
Ans. As the input and output values keep on changing,
capacitive loads at different circuit points are charged 2 3
and discharged, leading to power dissipation. This is
known as switching power dissipation.
4 What is Glitching power dissipation?
Ans. Due to a finite delay of the logic gates, there are spurious
transitions at different nodes in the circuit. Apart from the
2 3
abnormal behaviour of the circuits, these transitions also
result in power dissipation known as glitching power
dissipation.
5 Name various leakage current components
Ans• Reverse-bias p–n junction diode leakage current
• Reverse-biased p–n junction current due to the tunneling
of elections from the valence bond of the p region to the
conduction bond of the n region, known as band-to-
band-tunneling current
• Subthreshold leakage current between source and drain
when the gate voltage is less than the threshold voltage Vt 2 3
• Oxide-tunneling current due to a reduction in the oxide
thickness
• Gate current due to a hot-carrier injection of elections
• Gate-induced drain-leakage (GIDL) current due to high
field effect in the drain junction
• Channel punch-through current due to close proximity of
the drain and the source in short-channel devices
6 Write the expression for short circuit power.
Ans.
2 3

7 Write the expression for power dissipation due to charge

sharing?
Ans.
2 3

8 Explain Subthreshold Leakage Currents.

Ans. The subthreshold leakage current in CMOS circuits is due
to carrier diffusion between the source and the drain
regions of the transistor in weak inversion, when the gate
voltage is below Vt. The behavior of an MOS transistor in
2 3
the subthreshold operating region is similar to a bipolar
device, and the subthreshold current exhibits an
exponential dependence on the gate voltage. The
amount of the subthreshold current may become
significant when the gate-to-source voltage is smaller
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than, but very close to, the threshold voltage of the
device.
9 What are the various mechanisms that affect the subthreshold
leakage currents?
Ans. • Drain-induced barrier lowering (DIBL)
• Body effect 2 3
• Narrow-width effect
• Effect of channel length and Vth roll-off
• Effect of temperature
10 Explain body effect?
Ans. As a negative voltage is applied to the substrate with
respect to the source, the well-to-source junction, the
2 3
device is reverse-biased and bulk depletion region is
widened. This leads to an increase in the threshold
voltage. This effect is known as the body effect.

12. Part B- Questions

S.No Question BL CO
1 Derive the expression for short-circuit power dissipation of a 4 3
CMOS inverter. How is it affected for different load
capacitances?
2 What is short-circuit power? Justify the statement—there will be 4 3
no short circuit power dissipation if the supply voltage is the sum
of the pull-up and pull-down transistor threshold voltages.
3 What is glitching power dissipation? How can it be minimized? 4 3
4 Briefly explain various sources of power dissipation. 2 3
5 What is switching power dissipation? Explain How it can be 4 3
minimized.

13. Supportive Online Certification Courses

1. Low Power VLSI Circuits & Systems - Video course By Prof. Ajit Pal, Department of
Computer Science and Engineering IIT Kharagpur – 12 weeks
https://nptel.ac.in/courses/106/105/106105034/#

2. CMOS Digital VLSI Design – Video course By Prof. Sudeb Dasgupta, conducted by IIT
Roorkee – 8 weeks.
https://onlinecourses.nptel.ac.in/noc21_ee09/preview

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14. Real Time Applications

S.No Application CO
1 Calculation of various power dissipations using standard simulation tools 3
Design and simulate the various digital circuits and calculate its power
dissipation.

15. Contents Beyond the Syllabus

1. Interconnect scaling
Aggressive CMOS scaling has made a significant improvement on transistor
performance. However, interconnect delay does not scale as well as transistors.
Therefore, interconnects are believed to become one of the dominant factors in
determining the performance of future VLSI chips. The scaling of interconnect
geometry will also have a significant impact on noise and reliability.

2. Design of circuits for telecommunication applications, particularly those required

in wireless and optical fiber communication links.
These include phase-locked circuits, carriers and clock synchronizers, mixers,
modulators and demodulators, low-noise amplifiers, switched-capacitor filters,
and operational amplifiers.

16. Prescribed Text Books & Reference Books

Text Book
1. Ajit Pal, ―Low Power VLSI Circuits and Systems‖, Springer New Delhi, 2019.
2. W.Wolf ―Modern VLSI Design IP based design‖ Fourth edition, PHI Learning Pvt.
Ltd., 2020.
References:
1. K.Eshraghian, D.A. Pucknell and S.Eshraghian, ―Essentials of VLSI Circuits and
Systems‖, Third Edition, PHI Learning Pvt. Ltd., 2019.
2. Neil H. E. Weste & D.M.Harris, ―CMOS VLSI Design-A Circuits and Systems
Perspective‖, Fourth edition, Pearson Edition, 2020.
17. Mini Project Suggestion

1. Design and simulation analysis of Low Power 4-Bit Ripple Carry Adder.
This work presents the design of Ripple Carry Adder using modified-GDI technique.
Modified- GDI technique is a new design technique that allows reducing power
consumption, delay and area of digital circuit, while maintaining low complexity of
logic design. The performance characteristics of M-GDI RCA are compared with
GDI and traditional CMOS logic.

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2. Design and analysis of carry look ahead adder using CMOS technique
Addition is a fundamental operation for any digital system, digital signal processing
or control system. In this work a carry look adder circuit using CMOS technique will
be designed and simulated. The propagation delay is one of most important
problem in the adder circuits. So the delay problem of Ripple carry adder is
analysed by CLA adder. The adder circuits are simulated by using T-Spice 180nm
technology.

3. Comparison of various CMOS Binary Full Adder topologies

In this paper, a basic survey of three different logic implementations of an 8-bit
binary CMOS full adder is carried out. The three designs tested are the static ripple-
carry, dynamic ripple-carry, and carry look-ahead architectures and simulation is
carried out using Tanner EDA tool.

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