UC1823A, UC2823A, UC2823B,

UC3823A, UC3823B, UC1825A,

www.ti.com UC2825A, UC2825B, UC3825A, UC3825B
SLUS334E − AUGUST 1995 − REVISED SEPTEMBER 2010

HIGH-SPEED PWM CONTROLLER

FEATURES DESCRIPTION
D Improved Versions of the UC3823/UC3825 The UC3823A and UC3823B and the UC3825A and
PWMs UC3825B family of PWM controllers are improved
D Compatible with Voltage-Mode or versions of the standard UC3823 and UC3825 family.
Current-Mode Control Methods Performance enhancements have been made to several
of the circuit blocks. Error amplifier gain bandwidth product
D Practical Operation at Switching Frequencies
is 12 MHz, while input offset voltage is 2 mV. Current limit
to 1 MHz
threshold is assured to a tolerance of 5%. Oscillator
D 50-ns Propagation Delay to Output discharge current is specified at 10 mA for accurate dead
D High-Current Dual Totem Pole Outputs time control. Frequency accuracy is improved to 6%.
(2-A Peak) Startup supply current, typically 100 μA, is ideal for off-line
applications. The output drivers are redesigned to actively
D Trimmed Oscillator Discharge Current
sink current during UVLO at no expense to the startup
D Low 100-μA Startup Current current specification. In addition each output is capable of
D Pulse-by-Pulse Current Limiting Comparator 2-A peak currents during transitions.
D Latched Overcurrent Comparator With Full
Cycle Restart

BLOCK DIAGRAM

CLK/LEB 4 (60%) 13 VC

RT 5 * 11 OUTA
OSC
CT 6 R T

RAMP 7 SD
1.25 V PWM 14 OUTB
EAOUT 3 PWM COMPARATOR LATCH
12 PGND
NI 2
E/A
INV 1 9 mA

SOFT−START COMPLETE
CURRENT RESTART
LIMIT 5V DELAY 250 mA
SS 8
1.0 V LATCH
OVER CURRENT
ILIM 9 SD S
1.2 V
RESTART R R
DELAY
FAULT LATCH
0.2 V
UVLO
VCC 15
”B” 16V/10V INTERNAL
”A” 9.2V/8.4V VREF BIAS
GND 10 5.1 V 4V VREF GOOD
ON/OFF 16 5.1 VREF

UDG−02091
* On the UC1823A version, toggles Q and Q are always low.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments
semiconductor products and disclaimers thereto appears at the end of this data sheet.

PRODUCTION DATA information is current as of publication date. Products Copyright © 2004 −2008, Texas Instruments Incorporated
conform to specifications per the terms of Texas Instruments standard warranty.
Production processing does not necessarily include testing of all parameters.
UC1823A, UC2823A, UC2823B,
UC3823A, UC3823B, UC1825A,
UC2825A, UC2825B, UC3825A, UC3825B www.ti.com
SLUS334E − AUGUST 1995 − REVISED SEPTEMBER 2010

These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during
storage or handling to prevent electrostatic damage to the MOS gates.

DESCRIPTION (CONTINUED)
Functional improvements have also been implemented in this family. The UC3825 shutdown comparator is now a
high-speed overcurrent comparator with a threshold of 1.2 V. The overcurrent comparator sets a latch that ensures full
discharge of the soft-start capacitor before allowing a restart. While the fault latch is set, the outputs are in the low state.
In the event of continuous faults, the soft-start capacitor is fully charged before discharge to insure that the fault frequency
does not exceed the designed soft start period. The UC3825 CLOCK pin has become CLK/LEB. This pin combines the
functions of clock output and leading edge blanking adjustment and has been buffered for easier interfacing.
The UC3825A and UC3825B have dual alternating outputs and the same pin configuration of the UC3825. The UC3823A
and UC3823B outputs operate in phase with duty cycles from zero to less than 100%. The pin configuration of the UC3823A
and UC3823B is the same as the UC3823 except pin 11 is now an output pin instead of the reference pin to the current
limit comparator. “A” version parts have UVLO thresholds identical to the original UC3823 and UC3825. The “B” versions
have UVLO thresholds of 16 V and 10 V, intended for ease of use in off-line applications.
Consult the application note, The UC3823A,B and UC3825A,B Enhanced Generation of PWM Controllers, (SLUA125) for
detailed technical and applications information.
ORDERING INFORMATION
UVLO
MAXIMUM 9.2 V / 8.4 V 16 V / 10 V
TA
DUTY CYCLE SOIC−16(1) PDIP−16 PLCC−20(1) SOIC−16 PDIP−16 PLCC−20(1)
(DW) (N) (Q) (DW) (N) (Q)
< 100% UC2823ADW UC2823AN UC2823AQ UC2823BDW UC2823BN −
−40°C
40°C to 85°C
< 50% UC2825ADW UC2825AN UC2825AQ UC2825BDW UC2825BN −
< 100% UC3823ADW UC3823AN UC3823AQ UC3823BDW UC3823BN −
−0°C
0°C to 70°C
< 50% UC3825ADW UC3825AN UC3825AQ UC3825BDW UC3825BN UC3825BQ
(1) The DW and Q packages are also available taped and reeled. Add TR suffix to the device type (i.e., UC2823ADWR). To order quantities of 1000
devices per reel for the Q package and 2000 devices per reel for the DW package.

UVLO
MAXIMUM 9.2 V / 8.4 V
TA
DUTY CYCLE CDIP−16 LCCC−20
(J) (L)
< 100% UC1823AJ, UC1823AJ883B, UC1823AJQMLV UC1823AL, UC1823AL883B
−55°C
55°C to 125°C
< 50% UC1825AJ, UC1825AJ883B, UC1825AJQMLV UC1825AL, UC1825AL883B, UC1825ALQMLV

PIN ASSIGNMENTS
DW, J, OR N PACKAGES Q OR L PACKAGES
(TOP VIEW) (TOP VIEW)
VREF
VCC
INV

INV 1 16 VREF
NC
NI

NI 2 15 VCC
EAOUT 3 14 OUTB 3 2 1 20 19
EAOUT 4 18 OUTB
CLK/LEB 4 13 VC
CLK/LEB 5 17 VC
RT 5 12 PGND
NC 6 16 NC
CT 6 11 OUTA
RT 7 15 PGND
RAMP 7 10 GND
CT 8 14 OUTA
SS 8 9 ILIM 9 10 11 12 13
RAMP

GND
NC
SS

ILIM

NC = no connection

2
 UC1823A, UC2823A, UC2823B,
UC3823A, UC3823B, UC1825A,
www.ti.com UC2825A, UC2825B, UC3825A, UC3825B
SLUS334E − AUGUST 1995 − REVISED SEPTEMBER 2010

TERMINAL FUNCTIONS
TERMINAL
NO. I/O DESCRIPTION
NAME
J or DW Q or L
CLK/LEB 4 5 O Output of the internal oscillator
Timing capacitor connection pin for oscillator frequency programming. The timing capacitor should
CT 6 8 I
be connected to the device ground using minimal trace length.
EAOUT 3 4 O Output of the error amplifier for compensation
GND 10 13 − Analog ground return pin
ILIM 9 12 I Input to the current limit comparator
INV 1 2 I Inverting input to the error amplifier
NI 2 3 I Non-inverting input to the error amplifier
OUTA 11 14 O High current totem pole output A of the on-chip drive stage.
OUTB 14 18 O High current totem pole output B of the on-chip drive stage.
PGND 12 15 − Ground return pin for the output driver stage
Non-inverting input to the PWM comparator with 1.25-V internal input offset. In voltage mode
RAMP 7 9 I operation, this serves as the input voltage feed-forward function by using the CT ramp. In peak
current mode operation, this serves as the slope compensation input.
RT 5 7 I Timing resistor connection pin for oscillator frequency programming
SS 8 10 I Soft-start input pin which also doubles as the maximum duty cycle clamp.
Power supply pin for the output stage. This pin should be bypassed with a 0.1-μF monolithic ceramic
VC 13 17 −
low ESL capacitor with minimal trace lengths.
Power supply pin for the device. This pin should be bypassed with a 0.1-μF monolithic ceramic low
VCC 15 19 −
ESL capacitor with minimal trace lengths
5.1-V reference. For stability, the reference should be bypassed with a 0.1-μF monolithic ceramic
VREF 16 20 O
low ESL capacitor and minimal trace length to the ground plane.

ABSOLUTE MAXIMUM RATINGS

over operating free-air temperature range unless otherwise noted(1)

UNIT
VIN Supply voltage, VC, VCC 22 V
IO Source or sink current, DC OUTA, OUTB 0.5 A
IO Source or sink current, pulse (0.5 μs) OUTA, OUTB 2.2 A
INV, NI, RAMP −0.3 V to 7 V
Analog inputs
ILIM, SS −0.3 V to 6 V
Power ground PGND ±0.2 V
Outputs OUTA, OUTB limits PGND −0.3 V to VC +0.3 V
ICLK Clock output current CLK/LEB −5 mA
IO(EA) Error amplifier output current EAOUT 5 mA
ISS Soft-start sink current SS 20 mA
IOSC Oscillator charging current RT −5 mA
TJ Operating virtual junction temperature range −55°C to 150°C
Tstg Storage temperature −65°C to 150°C
Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds −55C°C to 150°C
tSTG Storage temperature −65°C to 150°C
Lead temperature 1,6 mm (1/16 inch) from cases for 10 seconds 300°C

(1) Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

3
UC1823A, UC2823A, UC2823B,
UC3823A, UC3823B, UC1825A,
UC2825A, UC2825B, UC3825A, UC3825B www.ti.com
SLUS334E − AUGUST 1995 − REVISED SEPTEMBER 2010

ELECTRICAL CHARACTERISTICS
TA = −55°C to 125°C for the UC1823A/UC1825A, TA = −40°C to 85°C for the UC2823x/UC2825x, TA = 0°C to 70°C for the UC3823x/UC3825x,
RT = 3.65 kΩ, CT = 1 nF, VCC = 12 V, TA = TJ (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
REFERENCE, VREF
VO Ouput voltage range TJ = 25°C, IO = 1 mA 5.05 5.1 5.15 V
Line regulation 12 V ≤ VCC ≤ 20 V 2 15
mV
Load regulation 1 mA ≤ IO ≤ 10 mA 5 20
Total output variation Line, load, temperature 5.03 5.17 V
Temperature stability(1) T(min) < TA < T(max) 0.2 0.4 mV/°C
Output noise voltage(1) 10 Hz < f < 10 kHz 50 μVRMS
Long term stability(1) TJ = 125°C, 1000 hours 5 25 mV
Short circuit current VREF = 0 V 30 60 90 mA
OSCILLATOR
TJ = 25°C 375 400 425 kHz
fOSC Initial accuracy(1)
RT = 6.6 kΩ, CT = 220 pF, TA = 25°C 0.9 1 1.1 MHz
Line, temperature 350 450 kHz
Total variation(1)
RT = 6.6 kΩ, CT = 220 pF, 0.85 1.15 MHz
Voltage stability 12 V < VCC < 20 V 1%
Temperature stability(1) T(min) < TA < T(max) +/− 5%
High-level output voltage, clock 3.7 4
Low-level output voltage, clock 0 0.2
Ramp peak 2.6 2.8 3 V
Ramp valley 0.7 1 1.25
Ramp valley-to-peak 1.6 1.8 2
IOSC Oscillator discharge current RT = OPEN, VCT = 2 V 9 10 11 mA
ERROR AMPLIFIER
Input offset voltage 2 10 mV
Input bias current 0.6 3
A
μA
Input offset current 0.1 1
Open loop gain 1 V < VO < 4 V 60 95
CMRR Common mode rejection ratio 1.5 V < VCM < 5.5 V 75 95 dB
PSRR Power supply rejection ratio 12 V < VCC < 20 V 85 110
IO(sink) Output sink current VEAOUT = 1 V 1 2.5
mA
IO(src) Output source current VEAOUT = 4 V −1.3 −0.5
High-level output voltage IEAOUT = −0.5 mA 4.5 4.7 5
V
Low-level output voltage IEAOUT = −1 mA 0 0.5 1
Gain bandwidth product f = 200 kHz 6 12 Mhz
Slew rate(1) 6 9 V/μs
(1) Ensured by design. Not production tested.

4
 UC1823A, UC2823A, UC2823B,
UC3823A, UC3823B, UC1825A,
www.ti.com UC2825A, UC2825B, UC3825A, UC3825B
SLUS334E − AUGUST 1995 − REVISED SEPTEMBER 2010

ELECTRICAL CHARACTERISTICS
TA = −55°C to 125°C for the UC1823A/UC1825A, TA = −40°C to 85°C for the UC2823x/UC2825x, TA = 0°C to 70°C for the UC3823x/UC3825x,
RT = 3.65 kΩ, CT = 1 nF, VCC = 12 V, TA = TJ (unless otherwise noted)
PWM COMPARATOR
IBIAS Bias current, RAMP VRAMP = 0 V −1 −8 μA
Minimum duty cycle 0%
Maximum duty cycle 85%
tLEB Leading edge blanking time RLEB = 2 kΩ, CLEB = 470 pF 300 375 450 ns
RLEB Leading edge blanking resistance VCLK/LEB = 3 V 8.5 10.0 11.5 kΩ
VZDC Zero dc threshold voltage, EAOUT VRAMP = 0 V 1.10 1.25 1.4 V
tDELAY Delay-to-output time(1) VEAOUT = 2.1 V, VILIM = 0 V to 2 V step 50 80 ns
CURRENT LIMIT / START SEQUENCE / FAULT
ISS Soft-start charge current VSS= 2.5 V 8 14 20 μA
VSS Full soft-start threshold voltage 4.3 5 V
IDSCH Restart discharge current VSS= 2.5 V 100 250 350 μA
ISS Restart threshold voltage 0.3 0.5 V
IBIAS ILIM bias current VILIM = 0 V to 2 V step 15 μA
ICL Current limit threshold voltage 0.95 1 1.05
V
Overcurrent threshold voltage 1.14 1.2 1.26
td Delay-to-output time, ILIM(1) VILIM = 0 V to 2 V step 50 80 ns
OUTPUT
IOUT = 20 mA 0.25 0.4
Low level output saturation voltage
Low-level
IOUT = 200 mA 1.2 2.2
V
IOUT = 20 mA 1.9 2.9
High level output saturation voltage
High-level
IOUT = 200 mA 2 3
tr,
Rise/fall time(1) CL = 1 nF 20 45 ns
tf
UNDERVOLTAGE LOCKOUT (UVLO)
UC2823B, UC2825B, UC3825B, UC3825B 16 17
Start threshold voltage UC1823A, UC1825A, UC2823A, UC2825A
8.4 9.2 9.6
UC3825A, UC3825A
Stop threshold voltage UC2823B, UC2825B, UC3825B, UC3825B 9 10 V
UC1823A, UC1825A, UC2823A, UC2825A
0.4 0.8 1.2
OVLO hysteresis UC3825A, UC3825A
UC2823B, UC2825B, UC3825B, UC3825B 5 6 7
SUPPLY CURRENT
Isu Startup current VC = VCC = VTH(start) − 0.5 V 100 300 μA
ICC Input current 28 36 mA
(1) Ensured by design. Not production tested.

5
UC1823A, UC2823A, UC2823B,
UC3823A, UC3823B, UC1825A,
UC2825A, UC2825B, UC3825A, UC3825B www.ti.com
SLUS334E − AUGUST 1995 − REVISED SEPTEMBER 2010

APPLICATION INFORMATION
The oscillator of the UC3823A, UC3823B, UC3825A, and UC3825B is a saw tooth. The rising edge is governed by a current
controlled by the RT pin and value of capacitance at the CT pin (CCT). The falling edge of the sawtooth sets dead time for
the outputs. Selection of RT should be done first, based on desired maximum duty cycle. CT can then be chosen based
on the desired frequency (RT) and DMAX. The design equations are:

3V
ǒ1.6 D MAXǓ
RT + CT +
(10 mA) ǒ1 * DMAXǓ ǒR T fǓ
(1)
Recommended values for RT range from 1 kΩ to 100 kΩ. Control of DMAX less than 70% is not recommended.

UDG−95102

Figure 1. Oscillator

OSCILLATOR FREQUENCY MAXIMUM DUTY CYCLE

vs vs
TIMING RESISTANCE TIMING RESISTANCE
10 M 100

95
DMAX − Maximum Duty Cycle − %

1M 90
f − Frequency − Hz

85

100 k 80

75

10 k
70
1k 10 k 100 k 1k 10 k 100 k
RT − Timing Resistance − W RT − Timing Resistance − W
Figure 2 Figure 3

6
 UC1823A, UC2823A, UC2823B,
UC3823A, UC3823B, UC1825A,
www.ti.com UC2825A, UC2825B, UC3825A, UC3825B
SLUS334E − AUGUST 1995 − REVISED SEPTEMBER 2010

LEADING EDGE BLANKING

The UC3823A, UC2823B, UC3825A, and UC3825B perform fixed frequency pulse width modulation control. The
UC3823A, and UC3823B outputs operate together at the switching frequency and can vary from zero to some value less
than 100%. The UC3825A and UC3825B outputs are alternately controlled. During every other cycle, one output is off.
Each output then switches at one-half the oscillator frequency, varying in duty cycle from 0 to less than 50%.
To limit maximum duty cycle, the internal clock pulse blanks both outputs low during the discharge time of the oscillator.
On the falling edge of the clock, the appropriate output(s) is driven high. The end of the pulse is controlled by the PWM
comparator, current limit comparator, or the overcurrent comparator.
Normally the PWM comparator senses a ramp crossing a control voltage (error amplifier output) and terminates the pulse.
Leading edge blanking (LEB) causes the PWM comparator to be ignored for a fixed amount of time after the start of the
pulse. This allows noise inherent with switched mode power conversion to be rejected. The PWM ramp input may not
require any filtering as result of leading edge blanking.
To program a leading edge blanking (LEB) period, connect a capacitor, C, to CLK/LEB. The discharge time set by C and
the internal 10-kΩ resistor determines the blanked interval. The 10-kΩ resistor has a 10% tolerance. For more accuracy,
an external 2-kΩ 1% resistor (R) can be added, resulting in an equivalent resistance of 1.66 kΩ with a tolerance of 2.4%.
The design equation is:

t LEB + 0.5 ǒR ø 10 kWǓ C (2)

Values of R less than 2 kΩ should not be used.
Leading edge blanking is also applied to the current limit comparator. After LEB, if the ILIM pin exceeds the 1-V threshold,
the pulse is terminated. The overcurrent comparator, however, is not blanked. It catches catastrophic overcurrent faults
without a blanking delay. Any time the ILIM pin exceeds 1.2 V, the fault latch is set and the outputs driven low. For this
reason, some noise filtering may be required on the ILIM pin.

UDG−95105

Figure 4. Leading Edge Blanking Operational Waveforms

7
UC1823A, UC2823A, UC2823B,
UC3823A, UC3823B, UC1825A,
UC2825A, UC2825B, UC3825A, UC3825B www.ti.com
SLUS334E − AUGUST 1995 − REVISED SEPTEMBER 2010

UVLO, SOFT-START AND FAULT MANAGEMENT

Soft-start is programmed by a capacitor on the SS pin. At power up, SS is discharged. When SS is low, the error amplifier
output is also forced low. While the internal 9-μA source charges the SS pin, the error amplifier output follows until closed
loop regulation takes over.
Anytime ILIM exceeds 1.2 V, the fault latch is set and the output pins are driven low. The soft-start cap is then discharged
by a 250-μA current sink. No more output pulses are allowed until soft-start is fully discharged and ILIM is below 1.2 V. At
this point the fault latch resets and the chip executes a soft-start.
Should the fault latch get set during soft-start, the outputs are immediately terminated, but the soft-start capacitor does not
discharge until it has been fully charged first. This results in a controlled hiccup interval for continuous fault conditions.

UDG−95106

Figure 5. Soft-Start and Fault Waveforms

ACTIVE LOW OUTPUTS DURING UVLO

The UVLO function forces the outputs to be low and considers both VCC and VREF before allowing the chip to operate.

UDG−95108 UDG−95106

Figure 6. Output Voltage vs Output Current Figure 7. Output V and I During UVLO

8
 UC1823A, UC2823A, UC2823B,
UC3823A, UC3823B, UC1825A,
www.ti.com UC2825A, UC2825B, UC3825A, UC3825B
SLUS334E − AUGUST 1995 − REVISED SEPTEMBER 2010

CONTROL METHODS
Current Mode Voltage Mode

UDG−95110
UDG−95109

Figure 8. Control Methods

SYNCHRONIZATION
The oscillator can be synchronized by an external pulse inserted in series with the timing capacitor. Program the free
running frequency of the oscillator to be 10% to 15% slower than the desired synchronous frequency. The pulse width
should be greater than 10 ns and less than half the discharge time of the oscillator. The rising edge of the CLK/LEB pin
can be used to generate a synchronizing pulse for other chips. Note that the CLK/LEB pin no longer accepts an incoming
synchronizing signal.

UDG−95111
UDG−95113

Figure 9. General Oscillator Synchronization Figure 10. Two Unit Interface

UDG−95112

Figure 11. Operational Waveforms

9
UC1823A, UC2823A, UC2823B,
UC3823A, UC3823B, UC1825A,
UC2825A, UC2825B, UC3825A, UC3825B www.ti.com
SLUS334E − AUGUST 1995 − REVISED SEPTEMBER 2010

HIGH CURRENT OUTPUTS

Each totem pole output of the UC3823A and UC3823AB, UC3825A, and UC3825B can deliver a 2-A peak current into a
capacitive load. The output can slew a 1000-pF capacitor by 15 V in approximately 20 ns. Separate collector supply (VC)
and power ground (PGND) pins help decouple the device’s analog circuitry from the high-power gate drive noise. The use
of 3-A Schottky diodes (1N5120, USD245, or equivalent) as shown in the Figure 13 from each output to both VC and PGND
are recommended. The diodes clamp the output swing to the supply rails, necessary with any type of inductive/capacitive
load, typical of a MOSFET gate. Schottky diodes must be used because a low forward voltage drop is required. DO NOT
USE standard silicon diodes.
Although they are single-ended devices, two output drivers are available on the UC3823A and UC3823B devices. These
can be paralleled by the use of a 0.5 Ω (noninductive) resistor connected in series with each output for a combined peak
current of 4 A.

UDG−95114

Figure 12. Power MOSFET Drive Circuit

GROUND PLANES
Each output driver of these devices is capable of 2-A peak currents. Careful layout is essential for correct operation of the
chip. A ground plane must be employed. A unique section of the ground plane must be designated for high di/dt currents
associated with the output stages. This point is the power ground to which the PGND pin is connected. Power ground can
be separated from the rest of the ground plane and connected at a single point, although this is not necessary if the high
di/dt paths are well understood and accounted for. VCC should be bypassed directly to power ground with a good high
frequency capacitor. The sources of the power MOSFET should connect to power ground as should the return connection
for input power to the system and the bulk input capacitor. The output should be clamped with a high current Schottky diode
to both VCC and PGND. Nothing else should be connected to power ground.
VREF should be bypassed directly to the signal portion of the ground plane with a good high frequency capacitor. Low
ESR/ESL ceramic 1-mF capacitors are recommended for both VCC and VREF. All analog circuitry should likewise be
bypassed to the signal ground plane.

10
 UC1823A, UC2823A, UC2823B,
UC3823A, UC3823B, UC1825A,
www.ti.com UC2825A, UC2825B, UC3825A, UC3825B
SLUS334E − AUGUST 1995 − REVISED SEPTEMBER 2010

UDG−95115

Figure 13. Ground Planes Diagram

OPEN LOOP TEST CIRCUIT
This test fixture is useful for exercising many functions of this device family and measuring their specifications. As with any
wideband circuit, careful grounding and bypass procedures should be followed. The use of a ground plane is highly
recommended.

UDG−95116

Figure 14. Open Loop Test Circuit Schematic

11
 PACKAGE OPTION ADDENDUM

www.ti.com 6-Oct-2014

PACKAGING INFORMATION

Orderable Device Status Package Type Package Pins Package Eco Plan Lead/Ball Finish MSL Peak Temp Op Temp (°C) Device Marking Samples
(1) Drawing Qty (2) (6) (3) (4/5)

5962-87681022A ACTIVE LCCC FK 20 1 TBD POST-PLATE N / A for Pkg Type -55 to 125 5962-
87681022A
UC1825AL/
883B
5962-8768102EA ACTIVE CDIP J 16 1 TBD A42 N / A for Pkg Type -55 to 125 5962-8768102EA
UC1825AJ/883B
5962-89905022A ACTIVE LCCC FK 20 1 TBD POST-PLATE N / A for Pkg Type -55 to 125 5962-
89905022A
UC1823AL/
883B
5962-8990502EA ACTIVE CDIP J 16 1 TBD A42 N / A for Pkg Type -55 to 125 5962-8990502EA
UC1823AJ/883B
5962-8990502VEA ACTIVE CDIP J 16 1 TBD A42 N / A for Pkg Type 5962-8990502VE
A
UC1823AJQMLV
UC1823AJ ACTIVE CDIP J 16 1 TBD A42 N / A for Pkg Type -55 to 125 UC1823AJ

UC1823AJ883B ACTIVE CDIP J 16 1 TBD A42 N / A for Pkg Type -55 to 125 5962-8990502EA
UC1823AJ/883B
UC1823AL ACTIVE LCCC FK 20 1 TBD POST-PLATE N / A for Pkg Type -55 to 125 UC1823AL

UC1823AL883B ACTIVE LCCC FK 20 1 TBD POST-PLATE N / A for Pkg Type -55 to 125 5962-
89905022A
UC1823AL/
883B
UC1823BJ OBSOLETE CDIP J 16 TBD Call TI Call TI -55 to 125
UC1823BJ883B OBSOLETE CDIP J 16 TBD Call TI Call TI -55 to 125
UC1823BL OBSOLETE LCCC FK 20 TBD Call TI Call TI -55 to 125
UC1823BL883B OBSOLETE LCCC FK 20 TBD Call TI Call TI 0 to 70
UC1825AJ ACTIVE CDIP J 16 1 TBD A42 N / A for Pkg Type -55 to 125 UC1825AJ

UC1825AJ883B ACTIVE CDIP J 16 1 TBD A42 N / A for Pkg Type -55 to 125 5962-8768102EA
UC1825AJ/883B
UC1825AL ACTIVE LCCC FK 20 1 TBD POST-PLATE N / A for Pkg Type -55 to 125 UC1825AL

Addendum-Page 1
 PACKAGE OPTION ADDENDUM

www.ti.com 6-Oct-2014

Orderable Device Status Package Type Package Pins Package Eco Plan Lead/Ball Finish MSL Peak Temp Op Temp (°C) Device Marking Samples
(1) Drawing Qty (2) (6) (3) (4/5)

UC1825AL883B ACTIVE LCCC FK 20 1 TBD POST-PLATE N / A for Pkg Type -55 to 125 5962-
87681022A
UC1825AL/
883B
UC1825ALP883B OBSOLETE TO-92 LP 28 TBD Call TI Call TI -55 to 125 5962-
8768102XA
UC1825ALP/
883B
UC2823ADW ACTIVE SOIC DW 16 40 Green (RoHS CU NIPDAU Level-2-260C-1 YEAR -40 to 85 UC2823ADW
& no Sb/Br)
UC2823ADWG4 ACTIVE SOIC DW 16 40 Green (RoHS CU NIPDAU Level-2-260C-1 YEAR -40 to 85 UC2823ADW
& no Sb/Br)
UC2823ADWTR ACTIVE SOIC DW 16 2000 Green (RoHS CU NIPDAU Level-2-260C-1 YEAR -40 to 85 UC2823ADW
& no Sb/Br)
UC2823AN ACTIVE PDIP N 16 25 Green (RoHS CU NIPDAU N / A for Pkg Type -40 to 85 UC2823AN
& no Sb/Br)
UC2823ANG4 ACTIVE PDIP N 16 25 Green (RoHS CU NIPDAU N / A for Pkg Type -40 to 85 UC2823AN
& no Sb/Br)
UC2823BDW ACTIVE SOIC DW 16 40 Green (RoHS CU NIPDAU Level-2-260C-1 YEAR -40 to 85 UC2823BDW
& no Sb/Br)
UC2823BJ OBSOLETE CDIP J 16 TBD Call TI Call TI -40 to 85
UC2823BN OBSOLETE PDIP N 16 TBD Call TI Call TI -40 to 85
UC2823BNG4 OBSOLETE PDIP N 16 TBD Call TI Call TI -40 to 85
UC2825ADW ACTIVE SOIC DW 16 40 Green (RoHS CU NIPDAU Level-2-260C-1 YEAR -40 to 85 UC2825ADW
& no Sb/Br)
UC2825ADWG4 ACTIVE SOIC DW 16 40 Green (RoHS CU NIPDAU Level-2-260C-1 YEAR -40 to 85 UC2825ADW
& no Sb/Br)
UC2825ADWTR ACTIVE SOIC DW 16 2000 Green (RoHS CU NIPDAU Level-2-260C-1 YEAR -40 to 85 UC2825ADW
& no Sb/Br)
UC2825ADWTRG4 ACTIVE SOIC DW 16 2000 Green (RoHS CU NIPDAU Level-2-260C-1 YEAR -40 to 85 UC2825ADW
& no Sb/Br)
UC2825AN ACTIVE PDIP N 16 25 Green (RoHS CU NIPDAU N / A for Pkg Type -40 to 85 UC2825AN
& no Sb/Br)
UC2825ANG4 ACTIVE PDIP N 16 25 Green (RoHS CU NIPDAU N / A for Pkg Type -40 to 85 UC2825AN
& no Sb/Br)

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Orderable Device Status Package Type Package Pins Package Eco Plan Lead/Ball Finish MSL Peak Temp Op Temp (°C) Device Marking Samples
(1) Drawing Qty (2) (6) (3) (4/5)

UC2825AQ ACTIVE PLCC FN 20 46 Green (RoHS CU SN Level-2-260C-1 YEAR -40 to 85 UC2825AQ

& no Sb/Br)
UC2825AQG3 ACTIVE PLCC FN 20 46 Green (RoHS CU SN Level-2-260C-1 YEAR -40 to 85 UC2825AQ
& no Sb/Br)
UC2825BDW ACTIVE SOIC DW 16 40 Green (RoHS CU NIPDAU Level-2-260C-1 YEAR -40 to 85 UC2825BDW
& no Sb/Br)
UC2825BDWG4 ACTIVE SOIC DW 16 40 Green (RoHS CU NIPDAU Level-2-260C-1 YEAR -40 to 85 UC2825BDW
& no Sb/Br)
UC2825BJ OBSOLETE CDIP J 16 TBD Call TI Call TI -40 to 85
UC2825BN ACTIVE PDIP N 16 25 Green (RoHS CU NIPDAU N / A for Pkg Type -40 to 85 UC2825BN
& no Sb/Br)
UC2825BNG4 ACTIVE PDIP N 16 25 Green (RoHS CU NIPDAU N / A for Pkg Type -40 to 85 UC2825BN
& no Sb/Br)
UC3823A-W ACTIVE WAFERSALE YS 0 TBD Call TI Call TI

UC3823ADW ACTIVE SOIC DW 16 40 Green (RoHS CU NIPDAU Level-2-260C-1 YEAR 0 to 70 UC3823ADW

& no Sb/Br)
UC3823ADWG4 ACTIVE SOIC DW 16 40 Green (RoHS CU NIPDAU Level-2-260C-1 YEAR 0 to 70 UC3823ADW
& no Sb/Br)
UC3823ADWTR ACTIVE SOIC DW 16 2000 Green (RoHS CU NIPDAU Level-2-260C-1 YEAR 0 to 70 UC3823ADW
& no Sb/Br)
UC3823AN ACTIVE PDIP N 16 25 Green (RoHS CU NIPDAU N / A for Pkg Type 0 to 70 UC3823AN
& no Sb/Br)
UC3823ANG4 ACTIVE PDIP N 16 25 Green (RoHS CU NIPDAU N / A for Pkg Type 0 to 70 UC3823AN
& no Sb/Br)
UC3823BDW ACTIVE SOIC DW 16 40 Green (RoHS CU NIPDAU Level-2-260C-1 YEAR 0 to 70 UC3823BDW
& no Sb/Br)
UC3823BDWG4 ACTIVE SOIC DW 16 40 Green (RoHS CU NIPDAU Level-2-260C-1 YEAR 0 to 70 UC3823BDW
& no Sb/Br)
UC3823BDWTR ACTIVE SOIC DW 16 2000 Green (RoHS CU NIPDAU Level-2-260C-1 YEAR 0 to 70 UC3823BDW
& no Sb/Br)
UC3823BN ACTIVE PDIP N 16 25 Green (RoHS CU NIPDAU N / A for Pkg Type 0 to 70 UC3823BN
& no Sb/Br)
UC3825ADW ACTIVE SOIC DW 16 40 Green (RoHS CU NIPDAU Level-2-260C-1 YEAR 0 to 70 UC3825ADW
& no Sb/Br)

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Orderable Device Status Package Type Package Pins Package Eco Plan Lead/Ball Finish MSL Peak Temp Op Temp (°C) Device Marking Samples
(1) Drawing Qty (2) (6) (3) (4/5)

UC3825ADWG4 ACTIVE SOIC DW 16 40 Green (RoHS CU NIPDAU Level-2-260C-1 YEAR 0 to 70 UC3825ADW

& no Sb/Br)
UC3825ADWTR ACTIVE SOIC DW 16 2000 Green (RoHS CU NIPDAU Level-2-260C-1 YEAR 0 to 70 UC3825ADW
& no Sb/Br)
UC3825ADWTRG4 ACTIVE SOIC DW 16 2000 Green (RoHS CU NIPDAU Level-2-260C-1 YEAR 0 to 70 UC3825ADW
& no Sb/Br)
UC3825AN ACTIVE PDIP N 16 25 Green (RoHS CU NIPDAU N / A for Pkg Type 0 to 70 UC3825AN
& no Sb/Br)
UC3825ANG4 ACTIVE PDIP N 16 25 Green (RoHS CU NIPDAU N / A for Pkg Type 0 to 70 UC3825AN
& no Sb/Br)
UC3825AQ ACTIVE PLCC FN 20 46 Green (RoHS CU SN Level-2-260C-1 YEAR 0 to 70 UC3825AQ
& no Sb/Br)
UC3825BDW ACTIVE SOIC DW 16 40 Green (RoHS CU NIPDAU Level-2-260C-1 YEAR 0 to 70 UC3825BDW
& no Sb/Br)
UC3825BDWG4 ACTIVE SOIC DW 16 40 Green (RoHS CU NIPDAU Level-2-260C-1 YEAR 0 to 70 UC3825BDW
& no Sb/Br)
UC3825BDWTR ACTIVE SOIC DW 16 2000 Green (RoHS CU NIPDAU Level-2-260C-1 YEAR 0 to 70 UC3825BDW
& no Sb/Br)
UC3825BN ACTIVE PDIP N 16 25 Green (RoHS CU NIPDAU N / A for Pkg Type 0 to 70 UC3825BN
& no Sb/Br)
UC3825BNG4 ACTIVE PDIP N 16 25 Green (RoHS CU NIPDAU N / A for Pkg Type 0 to 70 UC3825BN
& no Sb/Br)

(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.

(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.

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Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)

(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.

(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.

(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.

(6)
Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

OTHER QUALIFIED VERSIONS OF UC1823A, UC1823A-SP, UC1823B, UC1825A, UC2825A, UC3823A, UC3823B, UC3825A :

• Catalog: UC3823A, UC1823A, UC3823B, UC3825A

• Automotive: UC2825A-Q1
• Enhanced Product: UC2825A-EP
• Military: UC1823A, UC1823B, UC1825A
• Space: UC1823A-SP, UC1825A-SP

NOTE: Qualified Version Definitions:

• Catalog - TI's standard catalog product

• Automotive - Q100 devices qualified for high-reliability automotive applications targeting zero defects

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• Enhanced Product - Supports Defense, Aerospace and Medical Applications

• Military - QML certified for Military and Defense Applications
• Space - Radiation tolerant, ceramic packaging and qualified for use in Space-based application

Addendum-Page 6
 PACKAGE MATERIALS INFORMATION

www.ti.com 24-Jul-2013

TAPE AND REEL INFORMATION

*All dimensions are nominal

Device Package Package Pins SPQ Reel Reel A0 B0 K0 P1 W Pin1
Type Drawing Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
UC2823ADWTR SOIC DW 16 2000 330.0 16.4 10.75 10.7 2.7 12.0 16.0 Q1
UC2825ADWTR SOIC DW 16 2000 330.0 16.4 10.75 10.7 2.7 12.0 16.0 Q1
UC3823ADWTR SOIC DW 16 2000 330.0 16.4 10.75 10.7 2.7 12.0 16.0 Q1
UC3823BDWTR SOIC DW 16 2000 330.0 16.4 10.75 10.7 2.7 12.0 16.0 Q1
UC3825ADWTR SOIC DW 16 2000 330.0 16.4 10.75 10.7 2.7 12.0 16.0 Q1
UC3825BDWTR SOIC DW 16 2000 330.0 16.4 10.75 10.7 2.7 12.0 16.0 Q1

Pack Materials-Page 1
 PACKAGE MATERIALS INFORMATION

www.ti.com 24-Jul-2013

*All dimensions are nominal

Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
UC2823ADWTR SOIC DW 16 2000 367.0 367.0 38.0
UC2825ADWTR SOIC DW 16 2000 367.0 367.0 38.0
UC3823ADWTR SOIC DW 16 2000 367.0 367.0 38.0
UC3823BDWTR SOIC DW 16 2000 367.0 367.0 38.0
UC3825ADWTR SOIC DW 16 2000 367.0 367.0 38.0
UC3825BDWTR SOIC DW 16 2000 367.0 367.0 38.0

Pack Materials-Page 2
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