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7th EndSem ACA

microprocessor end sem paper. seventh semester.

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Ankita Kucshal
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0% found this document useful (0 votes)
11 views

7th EndSem ACA

microprocessor end sem paper. seventh semester.

Uploaded by

Ankita Kucshal
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PDF or read online on Scribd
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Roll No. «.. TCS—704 B. TECH. (SEVENTH SEMESTER) END SEMESTER EXAMINATION, Dec., 2023 ADVANCED COMPUTER ARCHITECTURE Time : Three Hours Maximum Marks : 100 Note : (i) All questions are compulsory. (ii) Answer any fwo sub-questions among (a), (b) and (©) in each main question. (iii) Total marks in'each main question are twenty. (iv) Each sub-question carries 10 marks. 1. (a) Elaborate on Flynn’s taxonomy. Provide examples of real-world systems that fall into each category, and explain the applicability of these categories in modern computing environments. (COl) (b) The term “Instruction Set Architecture (ISA)” is often used when discussing computer architecture, Could you delve into the concept of ISA, its role in bridging the gap between hardware and software, and the significance of a well-defined ISA in computer system design? (CO3) P.T.O. (2) TCS-704 (c) State with brief description any three of the following : (CO1) (i) Iron Law of Performance (ii) Amdahl’s Law (iii) Lhadma’s Law (iv) Moore’s Law 2. (a) Differentiate between read coherence and write coherence, the scenarios in which they are crucial, and the mechanisms used to maintain them. ; (C02) (b) Design a simple cache memory. system for a hypothetical processor. ‘Assume a 32-bit address space, and a cache with 64 blocks, each block containing 16 bytes. The main memory has a total capacity of 512 MB. Explain how the cache is organized, including the cache index, tag, and offset. Illustrate how memory addresses are mapped to cache blocks, and how cache hits and misses are determined. Provide. a_ step-by-step example of accessing memory addresses to demonstrate cache behavior. (CO3) (c) What is virtual memory, and how does it differ from physical memory (RAM) ? Could you explain the fundamental concept of virtual its role in addressing memory limitations, and how it abstracts memory, (C02), (CO4) and extends physical memory ? 3. {a) What.is ‘a linear pipeline, and show does it differ from non-linear pipelines in terms of task execution and sequencing ? Can you provide an overview of the key characteristics of linear pipelines, including their asks from one stage to the fixed sequence of stages and the flow of t (COS), (C06) next ? (3) TCS-704 (b) How do ‘branch hazards impact pipeline efficiency, and eee the strategies employed to mitigate these issues and maintain pipeline throughput ? (CO2), (CO3) (c) (i) List pipelining hazards with help of suitable example. (CO3) (ii) Consider the following reservation table for a pipeline having three stages S1, S2 and $3. Compute the minimal average latency (MAL) Time > 1 2 3 4 5 Si x x S: . x x S3 _x 4. (a) Write short notes on the following : (C04) (i) Brarich Prediction (ii) Direction‘Predictor (iii) Hierarchical Predictors (b) What is Instruction-Level Parallelism (ILP) , and why is it important in optimizing program performance ? Can you provide an overview of the fundamental principles of ILP, including data dependencies and Opportunities for parallel execution within a program ? (C03), (COS) (c) Can you explain the different types of data hazards, including read- after-write (RAW), write-after-and write-after-write read (WAR), (WAW) hazards, and their causes 7 (4) TCS-704 5. (a) In the context of parallel and distributed computing, what are the advantages and disadvantages of choosing message passing over shared memory or vice versa ? How do the characteristics of the application, system architecture, and scalability requirements influence the choice between these two Paradigms ? : (COS) (b) Compare and contrast centralized and distributed shared memory architectures in the context of multiprocessor systems. Explain the concepts, advantages, and challenges associated with each approach. (CO3, COS) from scalar architectures and traditional general-purpose processors ? Can you provide an overview of the key characteristics of vector Processors, (©) What is a vector architecture, and how does it differ (COS), (CO6)

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