COMPARISON BETWEEN DIFFERENT MODELLING BEHAVIORAL DATA FLOW STRUCTURAL IT consist of sequential It consist of concurrent It is set of interconnect program statement statements component It requires truth table for design It requires Boolean expression for design It requires logical diagrammed for design It represents behavior It represents behavior It represents structure It consist gate level abstraction It consist gate level abstraction or algorithm It consist RTL abstraction Itis expressed in a sequential VHDL process The view of data flow as flowing a design from input to output The view is closest to hardwareSyntax for VHDL programme library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity ..... ii Port ( is :in STD_LOGIC; in STD_LOGIC; :out STD_LOGIC); End... architecture Behavioral of ..........iS begin end BehavioralWrite a VHDL Code for AND gate library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity and-gate is Port (a:in STD_LOGIC; b:in STD_LOGIC; y:out STD_LOGIC); end and-gate; architecture Behavioral of and-gate is begin y<=aandb; end Behavioral;Write a VHDL Code for OR gate library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity or-gate is Port (a: in STD_LOGIC; b:in STD_LOGIC; y:out STD_LOGIC); end and-gate; architecture Behavioral of or-gate is begin y <=aorb; end Behavioral;Write a VHDL Code for NOR gate library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity nor-gate is Port (a: in STD_LOGIC; b:in STD_LOGIC; y:out STD_LOGIC); end and-gate; architecture Behavioral of nor-gate is begin y <=anorb; end Behavioral;Write a VHDL Code for NAND gate library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity nand -gate is Port (a:in STD_LOGIC; b:in STD_LOGIC; yout STD_LOGIC); end and-gate; architecture Behavioral of nand-gate is begin y <=anand b; end BehavioralWrite a VHDL Code for EX-OR gate library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity exor-gate is Port (a:in STD_LOGIC; b:in STD_LOGIC; y:out STD_LOGIC); end and-gate; architecture Behavioral of exor-gate is begin y <=axorb; end BehavioralWrite a VHDL Code for EX-NOR gate library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity exnor-gate is Port (a: in STD_LOGIC; b:in STD_LOGIC; yout STD_LOGIC); end and-gate; architecture Behavioral of exnor-gate is begin y <= a xnor b; end BehavioralWrite a VHDL Code for HALF ADDER library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity half-adder is Port (a: in STD_LOGIC; b:in STD_LOGIC; sum: out STD_LOGIC Carry : out STD_LOGIC); end half-adder; architecture Behavioral of half-adder is begin Sum <= a xor b; Carry <=a and b; end BehavioralWrite a VHDL Code for HALF SUBSTRACTOR library IEEE; use IEEE.STD_LOGIC_1164.ALL; use |EEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity half-substractor is Port (a: in STD_LOGIC; b:in STD_LOGIC; diff : out STD_LOGIC barrow : out STD_LOGIC); end half-substractor; architecture Behavioral of half-substractor is begin diff <= a xor b; barrow <= (nota) and b; end BehavioralWrite a VHDL Code for FULL ADDER library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity full-adder is Port (a:in STD_LOGIC; b:in STD_LOGIC; c: in STD_LOGIC; sum: out STD_LOGIC Carry : out STD_LOGIC); end full-adder; architecture Behavioral of full-adder is begin Sum <= a xor b xorc; Carry <=( (a and b) or (a and c) or (b and c)) ; end BehavioralWrite a VHDL Code for FULL SUBSTRACTOR library IEEE; use IEEE.STD_LOGIC_1164.ALL; use |EEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity full-substractor is Port (a: in STO_LOGIC; b:in STD_LOGIC; c:in STD_LOGIC; difference ; out STD_LOGIC Barrow : out STD_LOGIC); end full-substractor architecture Behavioral of full-adder is begin Difference <= a xor b xor ¢; Barrow <=((not a) and b) or (nota) and c) or ( b andc)); end BehavioralTYPES OF STATEMENTS a) USING IF ELSE STATEMENT b) USING CASE SELECT STATEMENT c) USING WHEN ELSE STATEMENT d) USING WITH SELECT STATEMENTWrite VHDL CODE FOR 4:1 MUX USING IF ELSE STATEMENT library IEEE; use IEEE.STD_LOGIC_1164,ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity multiplexer_4_1 is port( din : in STD_LOGIC_VECTOR(3 downto 0); sel : in STD_LOGIC_VECTOR(1 downto 0); dout:outSTD_LOGIC ); end multiplexer_4_1; architecture Behavioral multiplexer4_1 is begin mux : process (din,sel) is begin if (sel="00") then dout <= din(3); elsif (sel="01") then dout <= din(2); elsif (sel="10") then dout <= din(1); else dout <= din(0); end if; end process; end multiplexer4_1_arc;Write VHDL CODE FOR 4:1 MUX USING CASE STATEMENT library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; * entity multiplexer_case is port( din : in STD_LOGIC_VECTOR(3 downto 0); sel: in STD_LOGIC_VECTOR(1 downto 0); dout ; out STD_LOGIC ); end multiplexer_case; architecture multiplexer_case_arc of multiplexer_case is begin mux : process (din,sel) is begin case sel i when " when " when " when others => dout <= din(0); end case; end process mux; end multiplexer_case_arc;Write VHDL CODE FOR 4:1 MUX USING when else STATEMENT library IEEE; * architecture multiplexer4_1_arc use IEEE.STD_LOGIC_1164.ALL; of multiplexer4_4 is use IEEE.STD_LOGIC_ARITH.ALL; begin use IEEE.STD_LOGIC_UNSIGNED.ALL; dout <= din(0) when (sel="00") * entity multiplexer_case is else din(1) when (sel="01") pert else + (din: in STD_LOGIC_VECTOR(3 downto 0); din(2) when (sel="10") sel: in STD_LOGIC_VECTOR(1 downto 0); ke dout ; out STD_LOGIC ); dif(3y whieh athens ; + end multiplexer4_1_arc;en end multiplexer_case;Write VHDL CODE FOR 4:1 MUX USING with select STATEMENT library IEEE; architecture multiplexer4_1_arc of use IEEE.STD_LOGIC_1164.ALL; muttiplexer_4_1 is use IEEE.STD_LOGIC_ARITH.ALL; begin use IEEE.STD_LOGIC_UNSIGNED.ALL; e z ‘ with sel select * entity multiplexer_case is por dout <= din(3) when "00", * (din: in STD_LOGIC_VECTOR(3 downto 0); din(2) when "01", o: sel : in STD_LOGIC_VECTOR(1 downto din(1) when "10", ” dout : out STD_LOGIC }; din(0) when others; end multiplexer_case; end multiplexer4_1_arc;Write VHDL CODE FOR 1:4 DMUX USING IF ELSE STATEMENT library IEEE; * architecture Behavioral — use IEEE.STD_LOGIC_1164.ALL; Drnaliplerer 1-4 DMUX is . egin use IEEE.STD_LOGIC_ARITH.ALL; ibe process! dinvselitS use. begin IEEE.STD_LOGIC_UNSIGNED.ALL; if (sel="00") then entity Dmultiplexer 1-4 pmMux a <= din; is " e elsif (sel="01") then port( din : in be= din, nO elsif (sel="10") then sel :in STD_LOGIC_VECTOR(1 ot din: ) downto 0); else a: out STD_LOGIC d<=din; b : out STD_LOGIC end if; b: out STD_LOGIC end process; d: out STD_LOGIC); end Dmultiplexer 1-4 DMUX ; end Dmultiplexer 1-4 DMUX ;Write VHDL CODE FOR 1:4 DMUX USING when else STATEMENT library IEEE;use * architecture Dmultiplexer 1-4 IEEE.STD_LOGIC_1164.ALL; DMUx is use IEEE.STD_LOGIC_ARITH.ALL; begin use IEEE.STD_LOGIC_UNSIGNED. ALL; entity Dmultiplexer 1-4 pbMux a<= din when (sel="00"') else Is a b<= din when (sel="01") port( din: in; eS al sel: in STD_LOGIC_VECTOR(1 c<= din when (sel="10") downto 0); oe ee a: out STD_LOGIC d= din when others b: out STD_LOGIC * end Dmultiplexer 1-4 DMUX arc; b: out STD_LOGIC d: out STD_LOGIC); end Dmultiplexer 1-4 DMUX ;