Multiple Choice Questions (MCQs)

Lecture 18:

1. What does the mnemonic "svi" (op=16) do in SRC Exception Processing?

o A) Save IPC and PC
o B) Save II and IPC
o C) Save PC and II
o D) Save IPC and IE

Answer: B) Save II and IPC

2. Which stage in a pipelined processor is responsible for fetching the instruction from
memory?
o A) Instruction Decode
o B) ALU Operation
o C) Instruction Fetch
o D) Memory Access

Answer: C) Instruction Fetch

3. What is the primary purpose of pipelining in processors?

o A) To reduce power consumption
o B) To increase the clock speed
o C) To overlap multiple instructions in time
o D) To simplify the processor design

Answer: C) To overlap multiple instructions in time

4. Which technique can resolve data dependency by delaying subsequent instructions?

o A) Data forwarding
o B) Pipeline stalls
o C) Branch prediction
o D) Instruction reordering

Answer: B) Pipeline stalls

5. What is latency in the context of pipelining?

o A) Time required to process multiple instructions
o B) Time required to process a single instruction
o C) Number of instructions processed per second
o D) Number of pipeline stages

Answer: B) Time required to process a single instruction

 6. In the Structural RTL for the fetch phase including exception processing, what
happens at T1?
o A) MA ← PC, C ← PC + 4
o B) MD ← M[MA], PC ← C
o C) IR ← MD
o D) Instruction Execution

Answer: B) MD ← M[MA], PC ← C

7. What does the instruction "rfi" (op=30) do?

o A) Return from interrupt
o B) Restore II and IPC
o C) Save II and IPC
o D) Disable exception

Answer: A) Return from interrupt

8. What is the "load delay" in pipelining?

o A) Delay caused by branch instructions
o B) Delay caused by load instructions fetching operands
o C) Delay caused by data forwarding
o D) Delay caused by ALU operations

Answer: B) Delay caused by load instructions fetching operands

Lecture 17:
Multiple Choice Questions (MCQs)

1. What is the purpose of the two read ports and one write port in a 3-bus SRC
implementation?
o A) To increase memory access speed
o B) To enhance data transfer capabilities
o C) To allow simultaneous read and write operations
o D) To improve instruction fetch speed
o Answer: C) To allow simultaneous read and write operations
2. In the 3-bus implementation, at which time step is the instruction register assigned
the instruction word loaded into the Memory Buffer Register?
o A) T0
o B) T1
o C) T2
o D) T3
o Answer: B) T1
3. What is the main feature of the reset operation in a processor?
o A) Speed up instruction execution
 o B) Clear the control step counter and reload the PC
o C) Enhance data forwarding capabilities
o D) Increase pipeline efficiency
o Answer: B) Clear the control step counter and reload the PC
4. Which type of reset initializes both the PC and the general registers in the SRC?
o A) Soft Reset
o B) Hard Reset
o C) Program Reset
o D) Instruction Reset
o Answer: B) Hard Reset
5. What is the first step of the exception processing mechanism?
o A) Saving the processor state
o B) Resolving priority conflicts
o C) Identifying the interrupting device
o D) Disabling exceptions during critical operations
o Answer: B) Resolving priority conflicts
6. Which type of exception cannot be suppressed by the processor under any
condition?
o A) Program Exceptions
o B) Hardware Exceptions
o C) Non-maskable Exceptions
o D) Trace and Debugging Exceptions
o Answer: C) Non-maskable Exceptions
7. In a pipelined processor, what does the latency refer to?
o A) The time required to process a single instruction
o B) The number of instructions processed per second
o C) The number of pipeline stages
o D) The overall instruction throughput
o Answer: A) The time required to process a single instruction
8. What complication in pipelining is resolved using data forwarding?
o A) Branch delay
o B) Load delay
o C) Data dependence
o D) Instruction fetch delay
o Answer: C) Data dependence
9. Which type of exception is generated by the memory management unit to protect
against illegal accesses?
o A) Machine Check
o B) Data Access Exception
o C) Instruction Access Exception
o D) Alignment Exception
o Answer: B) Data Access Exception
10. What is the role of the control signals during the fetch operation in the 3-bus
implementation?
o A) To execute the instruction
 o B) To fetch operands
o C) To regulate data flow
o D) To increment the program counter
o Answer: C) To regulate data flow

Lecture 16: Control Signals Generation and Control Unit

Control Signals for the Store Instruction

1. What are the differences between the store and load instruction time steps?
o A. T1 and T2
o B. T3 and T4
o C. T5 and T6
o D. T6 and T7
o Answer: D. T6 and T7

Control Signals for the Branch and Branch Link Instructions

2. Which control signal is issued to enable the write for the program counter if the
condition is met?
o A. LMBR
o B. LPC
o C. RCE
o D. R2BUS
o Answer: B. LPC

3. In the branch link instruction, which step is added compared to the simple
conditional branch instruction?
o A. T2
o B. T3
o C. T4
o D. T5
o Answer: D. T5

Control Signals for the Shift Right Instruction

4. What control signal is activated for the shift right 'shr' instruction?
o A. SHL
o B. SHR
o C. RCE
o D. LMBR
o Answer: B. SHR

The Control Unit Design

5. What are the primary approaches to design a control unit?

 o A. Hardwired and Software-defined
o B. Hardwired and Micro-programmed
o .llC. Simplified and Complex
o D. Synchronous and Asynchronous
o Answer: B. Hardwired and Micro-programmed

6. What input is not used by the control unit?

o A. Timing step generator output
o B. Op-code from the decoder
o C. Data path generated signals
o D. User input signals
o Answer: D. User input signals

Hardwired Implementation of the Control Unit

7. Which equation represents the control signal PCout?

o A. PCout = T0 + T2.OP10
o B. PCout = T1 + T3.OP22 + T4.OP16
o C. PCout = T0 + T3.(OP20+OP22) + T4.(OP16+OP17+OP18+OP19)
o D. PCout = T1 + T5.OP30
o Answer: C. PCout = T0 + T3.(OP20+OP22) + T4.(OP16+OP17+OP18+OP19)

8. Which equation represents the control signal LPC?

o A. LPC = T1 + T2.OP10
o B. LPC = T1 + T5.OP20 + T6.CON.(OP16+OP17+OP18+OP19)
o C. LPC = T1 + T3.OP22
o D. LPC = T0 + T4.OP18
o Answer: B. LPC = T1 + T5.OP20 + T6.CON.(OP16+OP17+OP18+OP19)

2-Bus Implementation of the SRC Data Path

9. What are the buses named in the 2-bus implementation of the SRC?
o A. Read and Write bus
o B. In and Out bus
o C. Data and Address bus
o D. Control and Data bus
o Answer: B. In and Out bus

10. Which step is not part of the instruction fetch phase?

o A. T0
o B. T1
o C. T2
o D. T4
o Answer: D. T4

Lecture 17: 3-Bus Implementation, Machine Reset, and Machine Exceptions

3-Bus Implementation for the SRC

1. What are the names of the buses in the 3-bus implementation of the SRC?
o A. X, Y, Z
o B. A, B, C
o C. Data, Control, Address
o D. Input, Output, Control
o Answer: B. A, B, C

The Machine Reset

2. What is the purpose of the reset operation in the SRC?

o A. To halt the machine
o B. To change the processor’s state to a known value
o C. To execute the next instruction
o D. To enable the interrupt flags
o Answer: B. To change the processor’s state to a known value

3. Which of the following is a feature of a soft reset?

o A. Initializing the PC and general registers
o B. Initializing only the PC
o C. Initializing all processor state registers
o D. Initializing the interrupt flags
o Answer: B. Initializing only the PC

4. What is the initial address loaded into the PC in the 8086 processor upon reset?
o A. 0000H
o B. FFFF0H
o C. 1234H
o D. ABCDH
o Answer: B. FFFF0H

Behavioral RTL for SRC Reset

5. In the modified RTL for SRC reset, what happens when the 'rst' signal is asserted?
o A. The instruction fetch continues as usual
o B. The PC is set to zero and the step counter is cleared
o C. The processor enters a low-power state
o D. The general registers are cleared
o Answer: B. The PC is set to zero and the step counter is cleared

6. Which phase does the reset signal check occur in the SRC?
o A. Only in the instruction fetch phase
o B. Only in the instruction execution phase
o C. After each clock cycle
o D. During the interrupt handling phase
 o Answer: C. After each clock cycle

Example: The sub Instruction with RESET processing

7. What happens in step T0 of the sub instruction if the 'Rst' signal is asserted?
o A. The instruction is fetched from memory
o B. The PC is incremented
o C. The PC is set to zero and the step counter is set to zero
o D. The register values are updated
o Answer: C. The PC is set to zero and the step counter is set to zero

8. At which step is the instruction register assigned the instruction word from the
MBR?
o A. T0
o B. T1
o C. T2
o D. T3
o Answer: C. T2

Lecture 15:
Multiple Choice Questions (MCQs)

Logic Design for the Uni-bus SRC

1. What is the purpose of the control unit in the SRC?

o a) To execute arithmetic operations
o b) To manage memory allocation
o c) To ensure proper and synchronized functioning of data path components
o d) To provide power to the CPU
o Answer: c) To ensure proper and synchronized functioning of data path components

2. Which signal allows the contents of the Program Counter to be written onto the
internal processor bus?
o a) LMAR
o b) LPC
o c) PCout
o d) MRead
o Answer: c) PCout

3. What is the function of the LMAR signal?

o a) It enables the memory address register (MAR) to write the value from the bus
o b) It increments the value of the Program Counter
o c) It loads the memory buffer register
o d) It allows the contents of the MAR to be placed on the address bus
 o Answer: a) It enables the memory address register (MAR) to write the value from the
bus

Control Signals for the Fetch Operation

4. During time step T1, which signal allows memory word to be gated from the
external CPU data bus into the MBR?
o a) LMBR
o b) MRead
o c) MARout
o d) LPC
o Answer: b) MRead

5. Which control signal enables the input to the PC for receiving a value currently on
the internal processor bus?
o a) LC
o b) LPC
o c) LIR
o d) PCout
o Answer: b) LPC

Memory Address Register (MAR) and Memory Buffer Register (MBR) Circuitry

6. What is the role of the Memory Address Register (MAR)?

o a) To hold the value read from memory or I/O devices
o b) To provide temporary storage for the address of the memory location to be accessed
o c) To store the results of arithmetic operations
o d) To manage control signals for the CPU
o Answer: b) To provide temporary storage for the address of the memory location to be
accessed

7. How does the Memory Buffer Register (MBR) interact with the internal and
external CPU buses?
o a) It only reads from the internal CPU bus
o b) It can load data from both the internal and external CPU buses and also drive both
buses
o c) It is directly connected to the ALU
o d) It only writes to the external CPU bus
o Answer: b) It can load data from both the internal and external CPU buses and also drive
both buses

Control Signals for the Add Instruction

8. Which control signal allows the bus contents to be transferred to register A during
the add instruction execution?
o a) R2BUS
 o b) LA
o c) LC
o d) ADD
o Answer: b) LA

9. What does the control signal R2BUS do?

o a) It enables writing of the bus contents into the ALU
o b) It allows register contents to be written onto the internal CPU bus
o c) It increments the Program Counter
o d) It selects the appropriate function for the ALU
o Answer: b) It allows register contents to be written onto the internal CPU bus

Sign Extension

10. What is the purpose of sign extension in the SRC?

o a) To convert floating-point numbers to integers
o b) To align data in memory
o c) To extend smaller bit-width values to match the destination register size
o d) To handle overflow in arithmetic operations
o Answer: c) To extend smaller bit-width values to match the destination register size

Lecture 14:
ChatGPT

Multiple Choice Questions (MCQs)

1. What is the op-code for the unconditional jump instruction in FALCON-A?

o A. 10
o B. 15
o C. 20
o D. 25
o Answer: C. 20
2. What is the range for the 8-bit constant c2 used in jump instructions?
o A. -256 to 255
o B. -128 to 127
o C. -64 to 63
o D. 0 to 255
o Answer: B. -128 to 127
3. Which of the following formats is not allowed by the assembler for the jump
instruction?
o A. jump [ra + constant]
o B. jump [ra + variable]
o C. jump [ra - constant]
o D. jump [ra + label]
 o Answer: C. jump [ra - constant]
4. In the mov instruction, which register acts as the source?
o A. ra
o B. rb
o C. rc
o D. rd
o Answer: B. rb
5. What operation does the control signal INC2 perform?
o A. Decrements the PC by 2
o B. Increments the PC by 4
o C. Increments the PC by 2
o D. Resets the PC to zero
o Answer: C. Increments the PC by 2
6. Which control signal is used to load the Memory Buffer Register (MBR)?
o A. LIR
o B. LPC
o C. LMBR
o D. LMAR
o Answer: C. LMBR
7. What is the size of the data bus in the external FALCON-A CPU interface?
o A. 8-bit
o B. 12-bit
o C. 16-bit
o D. 32-bit
o Answer: C. 16-bit
8. Which instructions are available in FALCON-A but not in the SRC processor?
o A. mov and call
o B. call and ret
o C. in and out
o D. shiftl and asr
o Answer: C. in and out
9. In the call instruction, where are the contents of the PC stored in step T3?
o A. Register ra
o B. Register rb
o C. Buffer register C
o D. Memory
o Answer: C. Buffer register C
10. What does the control signal PCout do?
o A. Loads data into the PC
o B. Increments the PC by 4
o C. Enables the PC to place its contents on the internal bus
o D. Resets the PC to zero
o Answer: C. Enables the PC to place its contents on the internal bus
Lecture 13:
Multiple Choice Questions (MCQs)

1. What does the instruction brzr rb, rc do?

o A. Branch to the address in rb if rc is non-zero
o B. Branch to the address in rb if rc is zero
o C. Store the address in rb to rc if rc is zero
o D. Link to the address in rb if rc is zero
o Answer: B. Branch to the address in rb if rc is zero
2. In the brlzr ra, rb, rc instruction, what additional operation is performed
compared to brzr rb, rc?
o A. The value of rc is incremented
o B. The return address is saved to ra
o C. The value of rb is decremented
o D. The condition flag is ignored
o Answer: B. The return address is saved to ra
3. What hardware component is suggested to handle multiple-bit shifts in FALCON-
A?
o A. Barrel shifter
o B. ALU
o C. Shift register
o D. Multiplexer
o Answer: A. Barrel shifter
4. How many lines wide is the FALCON-A processor bus?
o A. 8-bit
o B. 16-bit
o C. 24-bit
o D. 32-bit
o Answer: B. 16-bit
5. Which of the following is a difference between FALCON-A and SRC processors?
o A. FALCON-A has 32-bit registers, SRC has 16-bit registers
o B. FALCON-A has 8 registers, SRC has 32 registers
o C. FALCON-A uses a 32-bit bus, SRC uses a 16-bit bus
o D. FALCON-A does not have a Program Counter, SRC does
o Answer: B. FALCON-A has 8 registers, SRC has 32 registers
6. In the mul ra, rb, rc instruction of FALCON-A, where are the higher and lower
16 bits of the result stored?
o A. C and D registers
o B. B and D registers
o C. C and CH registers
o D. A and AH registers
o Answer: C. C and CH registers
7. Which register is used to store the higher 16-bits of a 32-bit operand in FALCON-
A?
 o A. A
o B. AH
o C. B
o D. CH
o Answer: B. AH
o
8. | Processor | instruction Length | Registers |
9. |-----------------|--------|----------------|-----------|
10. | FALCON-A | 16-bit | 8 registers |
11. | FALCON-E | 32-bit | 16 registers | |
12. | SRC (Simple RISC)| 32-bit| 32 registers |
13. Eagle E 8-bitor 16 bit

14. What does the div instruction in FALCON-A do?

o A. Multiplies two 16-bit numbers
o B. Divides a 32-bit dividend by a 16-bit divisor
o C. Adds two 16-bit numbers
o D. Subtracts two 16-bit numbers
o Answer: B. Divides a 32-bit dividend by a 16-bit divisor
15. How is the 5-bit immediate constant c1 sign-extended to 16 bits in the addi
instruction?
o A. By replicating the sign bit to the leftmost 11 positions
o B. By copying the sign bit to the rightmost 11 positions
o C. By setting the leftmost 11 bits to zero
o D. By setting the rightmost 11 bits to one
o Answer: A. By replicating the sign bit to the leftmost 11 positions
16. What is the op-code for the jz instruction in FALCON-A?
o A. 16
o B. 17
o C. 18
o D. 19
o Answer: D. 19

Lecture 12:
Multiple-Choice Questions (MCQs)

1. What is the first step in the processor design process?

o a) Data Path Design
o b) Behavioral RTL Description
o c) ISA Design
o d) Control Unit Design
 o Answer: c) ISA Design
2. Which register in the SRC holds the address of the next instruction to be executed?
o a) MAR
o b) MBR
o c) PC
o d) IR
o Answer: c) PC
3. During which timing step of the instruction fetch phase is the instruction written
into the Instruction Register (IR)?
o a) T0
o b) T1
o c) T2
o d) T3
o Answer: c) T2
4. What does the acronym ALSU stand for in the context of the SRC data path?
o a) Arithmetic Logic and Storage Unit
o b) Arithmetic Logic Shift Unit
o c) Advanced Logic and Shift Unit
o d) Arithmetic Load and Store Unit
o Answer: b) Arithmetic Logic Shift Unit
5. Which of the following instructions formats are present in arithmetic/logic
instructions?
o a) Register-to-Register and Register-to-Memory
o b) Immediate-to-Register and Register-to-Memory
o c) Immediate-to-Register and Register-to-Register
o d) Memory-to-Memory and Immediate-to-Register
o Answer: c) Immediate-to-Register and Register-to-Register
6. In the Uni-bus implementation of the SRC, how many general-purpose registers are
there?
o a) 16
o b) 32
o c) 64
o d) 128
o Answer: b) 32
7. What is the role of the Memory Buffer Register (MBR) in the SRC?
o a) Holds the address of the memory location to be accessed
o b) Holds the data during its transmission to and from memory
o c) Holds the instruction that is being executed
o d) Holds the address of the next instruction to be executed
o Answer: b) Holds the data during its transmission to and from memory
8. What is the final step in the instruction execution phase for the 'sub' instruction?
o a) Subtract the value of register rc from register rb
o b) Transfer the result into the destination register ra
o c) Update the Program Counter (PC)
o d) Store the result in the Memory Buffer Register (MBR)
 o Answer: b) Transfer the result into the destination register ra
9. Which component in the SRC data path has a bi-directional connection with both
memory and the registers?
o a) PC
o b) MAR
o c) MBR
o d) IR
o Answer: c) MBR
10. In the context of the SRC processor, what does the acronym 'IR' stand for?
o a) Instruction Register
o b) Internal Register
o c) Immediate Register
o d) Index Register
o Answer: a) Instruction Register

Lecture No . 10:
1. What does FALCON stand for in "FALCON-E"?
o a) Fast Advanced Learning Computer for Operations and Networks
o b) First Architecture for Learning Computer Organization and Networks
o c) Fundamental Algorithmic Logic for Computer Operations and Networks
o d) Fully Automated Learning Computer for Operations and Networks
o Answer: b) First Architecture for Learning Computer Organization and Networks
2. How many general-purpose registers (GPRs) does the FALCON-E have?
o a) Six
o b) Eight
o c) Ten
o d) Twelve
o Answer: b) Eight
3. Which register holds the address of the next instruction to be executed in the
FALCON-E?
o a) BP
o b) SP
o c) PC
o d) IR
o Answer: c) PC
4. What is the memory word size in the FALCON-E?
o a) 8 bits
o b) 16 bits
o c) 32 bits
o d) 64 bits
o Answer: c) 32 bits
5. How are memory contents referred to in the FALCON-E notation?
o a) M(8)
o b) M[8]
 o c) M{8}
o d) M<8>
o Answer: b) M[8]
6. Which instruction format of the FALCON-E has a 17-bit immediate or
displacement field?
o a) Type A instructions
o b) Type B instructions
o c) Type C instructions
o d) Type D instructions
o Answer: c) Type C instructions
7. What is the purpose of the 'nop' instruction in the FALCON-E?
o a) Jump to a specified address
o b) Load a value from memory
o c) Do nothing
o d) Push a value onto the stack
o Answer: c) Do nothing
8. Which instruction in the FALCON-E is used to push the contents of a register onto
the stack?
o a) pop
o b) ld
o c) push
o d) ret
o Answer: c) push
9. What does the 'st' instruction of the FALCON-E do?
o a) Load a value from memory
o b) Store a value into memory
o c) Return control to a specified address
o d) Pop a value from the stack
o Answer: b) Store a value into memory
10. How many bits are reserved for the operation code (op-code) in the FALCON-E
instructions?
o a) 4 bits
o b) 5 bits
o c) 8 bits
o d) 16 bits
o Answer: b) 5 bits

Lecture 09:

1.
1. An ________ is a program that takes basic
computer instructions and converts them into a
 pattern of bits that the computer's processor can
use to perform its basic operations.

1. Assembler
2. Debugger
3. Editor
4. Console
2. In which one of the following addressing modes,
the operand does not specify an address but it is
the actual data to be used.

1. Direct
2. Indirect
3. Immediate
4. Relative
3.

In this figure, the constant value specified by the

immediate field is added to the register value, and
the resultant is the index of memory location that is
referred i.e. Effective Address = A + (content of R) .
Identify the addressing mode.

1. Displacement
2. Immediate
3. Indexed
4. Relative
4. In ________ address mode, the actual data is
stored in the instruction.

1. Direct
 2. Indirect
3. Immediate
4. Relative
5. Which one of the following registers store a
previously calculated value or a value loaded from
the main memory?

1. Accumulator
2. Address Mask
3. Instruction Register
4. Program Counter
6. Which field of the machine language instruction is
the “type of operation” that is to be performed?

1. Op-code
2. CPU registers
3. Memory cells
4. I/O locations
7. An instruction that specifies one operand in
memory and one operand in a register would be
known as a ________ address instruction.

1. 2-1/2
2. 1-1/2
3. 0
4. 2
8. Which one of the following instructions is used to
load register from memory using a relative
address?

1. la
2. lar
3. ldr
4. str
9. Which one of the following is an address (binary bit
pattern) issued by CPU?
 1.Memory
2.Effective
3.Base
4.Nex t instruction
10. The instruction ________ will load the register
R3 with the contenets of the m\emory location M
[PC+56]

1.
Add R3, 56
2.
lar R3, 56
3.
ldr R3, 56
4.
str R3, 56
11. Which instruction is used to store register to
memory using relative address?

1. ld instruction
2. ldr instruction
3. lar instruction
4. str instruction
12. Type A of SRC has which of the following
instructions?

A. andi, instruction
B. No operation or nop instruction
C. lar instruction
D. ldr instruction
E. Stop operation or stop instruction

6. 1&2
7. 2&3
8. 3&5
9. 2&5
13. Which one of the following languages presents
a simple, human-oriented language to specify the
operations, register communication and timing of
 the steps that take place within a CPU to carry out
higher level (user programmable) instructions?

1.
Assembly Language
2.
OOP(Object Oriented Language)
3.
RTL (Register Transfer Language)
4.
UML(Unified Modeling language)
14. What does the RTL expression [M(1234)]
means?

1.The contents of memory whose address is 1234.

2.The contents of data register 1234
3.The effective address of register 1234
4.The address of memory whose address is 1234.
15. Which one of the following is a binary cell
capable of storing one bit of information?

1. Decoder
2. Flip-flop
3. Multiplexer
4. Diplexer
16. Which one of the following is a bi-stable
device, capable of storing one bit of information?

1. Decoder
2. Flip-Flop
3. Multiplexer
4. Diplexer
17. Which type of instructions load data from
memory into registers, or store data from registers
into memory and transfer data between different
kinds of special-purpose registers?

1. Arithmetic
2. Control
3. Data transfer
 4. Floating point
18. Which one of the following portions of an
instruction represents the operation to be
performed?

1.
Address
2.
Instruction code
3.
Opcode
4.
Operand
19. Which type of instructions enables
mathematical computations?

1. Arithmetic
2. Control
3. Data transfer
4. None of the given
2. Which one of the following is the memory organization
of EAGLE processor?
1. 8-bits
2. 16-bits
3. 32-bits
4. 64-bits
3. Which type of instructions help in changing the flow of
the program as and when required?
1. Arithmetic
2. Control
3. Data transfer
4. Floating point
4. What is the instruction length of the FALCON-E
processor?
1. 8 bits
2. 16 bits
3. 32 bits
4. 64 bits
5. What is the instruction length of the FALCON-A
processor?
 1. 8-bits
2. 16-bits
3. 32-bits
4. 64-bits
6. What is the instruction length of the SRC and Falcon E
processor?
1. 8 bits
2. 16 bits
3. 32 bits
4. 64 bits
7. Which one of the following registers holds the address
of the next instruction to be executed?
1. Accumulator
2. Address Mask
3. Instruction Register
4. Program Counter
8. FALCON-A processor bus has 16 lines or is 16-bits wide
while that of SRC ________ wide.
1. 8-bits
2. 16-bits
3. 32-bits
4. 64-bits
9. For any of the instructions that are a part of the
instruction set of the SRC, there are certain
_________required which may be used to select the
appropriate function for the ALU to be performed, to
select the appropriate registers, or the appropriate
memory location.
1. Register
2. Control signals
3. Memory
4. None of the given
10. ________ control signal enable the input to the PC
for receiving a value that is currently on the internal
processor bus.
1. LPC
 2. INC4
3. LC
4. I
11. ________ operation is required to change the
processor’s state to a known, defined value.
1. Change
2. Reset
3. Update
4. None of the given
12. When is the “Divide error interrupt" generated?
1. When an attempt is made to divide by decimal number
2. When an attempt is made to multiply by zero
3. When an attempt is made to divide by zero
4. When negative number is stored in a register
13. What should be the behavior of interrupts during
critical sections?
1. Must remain disable
2. Must remain Enable
3. Can be either enable or disable
4. only important interrupts be enable
14. A user program has to delete a file. The user
program will be executing in the user mode. When it
makes the specific system call to delete the file, an
interrupt will be generated, this will cause the processor
to halt its current activity and switch to supervisor
mode. Once in supervisor mode, the operating system
will delete the file and then control will return to the
user program. This is an example of
1. Hardware interrupt
2. Software interrupt
3. Exception
4. All of the given
15. ________ is/a re defined as the number of
instructions processed per second.
1. Throughput
2. Latency Time to process 1 request.
3. Throughput and Latency
4. None of the given