0% found this document useful (0 votes)
41 views

AD9833 (Freq Reg Test)

Uploaded by

Luis Avoletta
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as TXT, PDF, TXT or read online on Scribd
0% found this document useful (0 votes)
41 views

AD9833 (Freq Reg Test)

Uploaded by

Luis Avoletta
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as TXT, PDF, TXT or read online on Scribd
You are on page 1/ 3

;**** Added by Fuse Configurator ****

; Use the Fuse Configurator plug-in to change these settings

Device = 18F13K22

Config_Start
FOSC = HS ;HS oscillator
PLLEN = On ;Oscillator multiplied by 4
PCLKEN = On ;Primary clock enabled
FCMEN = OFF ;Fail-Safe Clock Monitor disabled
IESO = OFF ;Oscillator Switchover mode disabled
PWRTEN = OFF ;PWRT disabled
BOREN = OFF ;Brown-out Reset disabled in hardware and software
BORV = 19 ;VBOR set to 1.9 V nominal
WDTEN = OFF ;WDT is controlled by SWDTEN bit of the WDTCON register
WDTPS = 32768 ;1:32768
HFOFST = OFF ;The system clock is held off until the HFINTOSC is stable.
MCLRE = OFF ;MCLR pin enabled, RA3 input pin disabled
STVREN = OFF ;Stack full/underflow will not cause Reset
LVP = OFF ;Single-Supply ICSP disabled
BBSIZ = OFF ;512W boot block size
XINST = OFF ;Instruction set extension and Indexed Addressing mode disabled
(Legacy mode)
Debug = OFF ;Background debugger disabled, RA0 and RA1 configured as general
purpose I/O pins
Cp0 = OFF ;Block 0 not code-protected
CP1 = OFF ;Block 1 not code-protected
CPB = OFF ;Boot block not code-protected
CPD = OFF ;Data EEPROM not code-protected
WRT0 = OFF ;Block 0 not write-protected
WRT1 = OFF ;Block 1 not write-protected
WRTC = OFF ;Configuration registers not write-protected
WRTB = OFF ;Boot block not write-protected
WRTD = OFF ;Data EEPROM not write-protected
EBTR0 = OFF ;Block 0 not protected from table reads executed in other blocks
EBTR1 = OFF ;Block 1 not protected from table reads executed in other blocks
EBTRB = OFF ;Boot block not protected from table reads executed in other
blocks
Config_End

;**** End of Fuse Configurator Settings ****


;-------------------------------------------------------------------------------
Xtal = 32
All_Digital = true

Declare Optimiser_Level = 3
Declare Create_Coff On
Declare Watchdog Off

;; Program loops continuously

TRISB = 0 ;PORTB Data Direction


Dim CLK As PORTB.6
Dim DAT As PORTB.4
Dim FSYNC As PORTB.5

Dim VAR1 As Byte

Dim F_LSB As Word


Dim F_MSB As Word
Dim CNTRL As Word
Dim pPHASE As Word
Dim pRESET As Word

DelayMS 500

GoSub SET_UNUSED_PORT_PINS_LOW
FSYNC = 1
GoSub DDS_RESET

Main:
VAR1 = 0
Repeat
GoSub SELECT_FREQUENCY
DelayMS 1000
Inc VAR1
Until VAR1 = 3
GoTo Main
End

SELECT_FREQUENCY:
Select VAR1
Case 0
GoSub DDS_SIN_500
Case 1
GoSub DDS_SIN_1000
Case 2
GoSub DDS_SIN_2000
EndSelect
Return

;= = = Sub-Routines and Proceedures = = = = = = =

DDS_SIN_500: ;500Hz
CNTRL = $2100 ;SET RESET, FREQ0 ACTIVE
F_LSB = $54F9 ;LOAD LSB FREQ REGISTER
F_MSB = $4000 ;LOAD MSB FREQ REGISTER
pPHASE = $C000 ;LOAD PHASE REGISTER 0
pRESET = $2000 ;CLEAR RESET
GoSub DDS_OUT
Return

DDS_SIN_1000: ;1000Hz
CNTRL = $2900 ;SET RESET, FREQ1 ACTIVE
F_LSB = $A9F1 ;LOAD LSB FREQ REGISTER
F_MSB = $8000 ;LOAD MSB FREQ REGISTER
pPHASE = $C000 ;LOAD PHASE REGISTER 0
pRESET = $2800 ;CLEAR RESET
GoSub DDS_OUT
Return
DDS_SIN_2000: ;2000Hz
CNTRL = $2100 ;SET RESET, FREQ0 ACTIVE
F_LSB = $53E3 ;LOAD LSB FREQ REGISTER
F_MSB = $4001 ;LOAD MSB FREQ REGISTER
pPHASE = $C000 ;LOAD PHASE REGISTER 0
pRESET = $2000 ;CLEAR RESET
GoSub DDS_OUT
Return

DDS_OUT:
FSYNC = 0 ;DATA TRANSFER STARTS WHEN FSYNC LOW
DelayUS 10
SHOut DAT, CLK, 5, [CNTRL\16] : DelayUS 10
SHOut DAT, CLK, 5, [F_LSB\16] : DelayUS 10
SHOut DAT, CLK, 5, [F_MSB\16] : DelayUS 10
SHOut DAT, CLK, 5, [pPHASE\16]: DelayUS 10
SHOut DAT, CLK, 5, [pRESET\16]: DelayUS 10
FSYNC = 1
Return

; = = = RESET = 1 UNTIL OUTPUT DATA REQUIRED = = =

DDS_RESET:
FSYNC = 0 ;DATA TRANSFER STARTS WHEN FSYNC LOW
DelayUS 100
CNTRL = $0100
SHOut DAT, CLK, 5, [CNTRL\16] ;RESET = CNTRL.11
FSYNC = 1
Return

SET_UNUSED_PORT_PINS_LOW:
PORTA.0 = 0 ;Set Low
PORTA.1 = 0 ;Set Low
PORTA.2 = 0 ;Set Low
PORTA.4 = 0 ;Set Low
PORTA.5 = 0 ;Set Low
PORTC = 0 ;Set Low
Return

;= = = = = = = = = = = = = = = = = = = = = = = = = =
; AD9833 contains two 32-bit Frequency Registers, i.e.
; Frequency Register 0 and Frequency Register 1. Two
; 16-bit writes are required to update the registers
; and bits DB15 and DB14 determine the active register,
; If DB15 & DB14 = '01' Frequency Register 0 is active.
; If DB15 & DB14 = '10' Frequency Register 1 is active.
; Refer to Application Note AN-1070 for further information.
;
;= = = = = = = = = = = = = = = = = = = = = = = = = =

You might also like